NetFPGA Tutorial Slides

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NSF GEC4 1 March 2009 http://NetFPGA.org/ NSF GENI Engineering Conference 4 (GEC4) March 31, 2009 John W. Lockwood http://stanford.edu/~jwlockwd/ [email protected] NetFPGA Update at GEC4

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Page 1: NetFPGA Tutorial Slides

NSF GEC4 1 March 2009

http://NetFPGA.org/

NSF GENI Engineering Conference 4 (GEC4) March 31, 2009

John W. Lockwoodhttp://stanford.edu/~jwlockwd/

[email protected]

NetFPGA Update at GEC4

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What is the NetFPGA?A line-rate, flexible, open networking platform for teaching and network research

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Outline• What is a NetFPGA system

– Open hardware and software• Why do we use reconfigurable hardware

– Strengths and weaknesses • Who uses the NetFPGA

– Update on worldwide deployments• What’s new

– Upcoming 2.0 Release • Where is the NetFPGA

– Source code and documentation • How are projects contributed

– Regression tests• When is the 2009 Developers workshop

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FPGA

Memory

1GE

1GE

1GE

1GE

What is a NetFPGA System

PCI

CPU Memory

NetFPGA Board

PC with NetFPGA

Softwarerunning on a standard PC

+

A hardware acceleratorbuilt with Field Programmable Gate Arraydriving Gigabit network links

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FPGA

Memory

1GE

1GE

1GE

1GE

How do I Run the Router Kit

User-space development, 4x1GE line-rate forwarding

PCI

CPU MemoryOSPF BGP

My Protocoluser

kernelRouting

Table

IPv4Router

1GE

1GE

1GE

1GE

FwdingTable

PacketBuffer

“Mirror”

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FPGA

Memory

1GE

1GE

1GE

1GE

Building Modular Router Modules

PCI

CPU Memory

NetFPGA Driver

Java GUIFront Panel(Extensible)

PW-OSPF

In QMgmt

IPLookup

L2Parse

L3Parse

Out QMgmt

1GE

1GE

1GE

1GEVerilog modules interconnected by FIFO interfaces

MyBlock

VerilogEDA Tools

(Xilinx, Mentor, etc.)

1. Design2. Simulate3. Synthesize4. Download

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FPGA

Memory

1GE

1GE

1GE

1GE

How do I create new systems

PCI

CPU Memory

NetFPGA Driver

1GE

1GE

1GE

1GE

My Design

(1GE MAC is soft/replaceable)

VerilogEDA Tools

(Xilinx, Mentor, etc.)

1. Design2. Simulate3. Synthesize4. Download

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Strengths of Reconfigurable Networks• Implement Wire-speed Processing

– Header Processing• Switching, routing, firewalls

– Full Payload Processing• Content distribution and intrusion prevention

• Enhance and create new datapath functions– Monitor network flows

• NetFlow probe– Control network flows

• OpenFlow switch– Generate traffic

• Traffic generator– Process new protocols ..

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Weaknesses of Reconfiguration Nets

• Device configuration must be secure– Hackers will try to reconfigure devices– Competitors will try to reverse engineer applications

• Network systems are complex– Cisco routers contains 18M+ lines of code– Modular components needed for large systems

• Must be power efficient– FPGAs use 5-50x more power than ASIC, however– FPGAs use 5-50x less power than software

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Time to Prototype New systems

• Network systems use Multiple Languages– VHDL, Verilog (Synthesizable Hardware)– Bluespec, Handel-C, SystemC (High-Level)– C, C++, Perl, PHP, Java (SW, Verification, GUIs)

• Networks are implemented in – Software:

• Compile in seconds to minutes– FPGAs:

• Synthesize in minutes to hours– ASICs:

• Fabricate in months to years

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Goals for an Ideal Network Platform• Provide a large library of elements

– With modular interfaces• Enable systems to easily compose

– By combining multiple, standard elements• Clearly define the functionality

– By verification to a set of regression tests• Widely disseminate projects

– Make download as easy as using iTunes • Build a community of developers

– Organize projects– Document contributions– Respond to feedback from users– Encourage the community to contribute

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Inter-module Communication

data

ctrlwr

rdy

Table memory

Packet memory

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NetFPGA 1G Pipeline Stages

MACRxQ

CPURxQ

MACRxQ

CPURxQ

MACRxQ

CPURxQ

MACRxQ

CPURxQ

Input Arbiter

Output Port Lookup

MACTxQ

CPUTxQ

MACTxQ

CPUTxQ

MACTxQ

CPUTxQ

MACTxQ

CPUTxQ

Output Queues

DRAMForward

TableLogic

PacketBufferLogic

SRAM

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Building the NetFPGAroute from the Verilog

Source Code

Using the Xilinx ISE tools to synthesize the logic for the FPGA

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Building the NetFPGA Router

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Explore the Router

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NetFPGA 17 S T A N F O R D U N I V E R S I T Y

Look inside the Router

Click

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Why do we use the NetFPGA

• To run laboratory courses on network routing– Professors teach courses (CS344, Workshops, ..)

• To teach students how to build real Internet routers– Train students to build routers (Cisco, Juniper, Huawei, .. )

• To research how new features in the network– Build network services for data centers (Google, UCSD.. )

• To prototype systems with live traffic– That Buffer measurement (while maintaining throughput, ..)

• To help hardware vendors understand device requirements– Use of hardware (Xilinx, Micron, Cypress, Broadcom, ..)

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Where are NetFPGAs?– Over 500 users with ~1,000 cards deployed– Deployed in ~120 universities in 17 Countries

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Photos from NetFPGA Tutorials

http://netfpga.org/pastevents.php and http://netfpga.org/upcomingevents.phpEuroSys - Glasgow, Scotland, U.K.

Beijing, China

SIGMETRICS - San Diego, California, USA

Bangalore, India

SIGCOMM - Seattle, Washington, USA

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• PCs assembled from parts– Integrates into standard PC

• Pre-built systems available – From 3rd Party Vendor

• Details are in the Guide– http://netfpga.org/static/guide.html

NetFPGA Systems

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Rackmount NetFPGA Servers

NetFPGA inserts in PCI or PCI-X slot

2U Server (Dell 2950)

Thanks: Brian Cashman for providing machine

1U Server (Accent Technology, Inc)

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Stanford NetFPGA Cluster

Statistics• Rack of 40

• 1U PCs • NetFPGAs

• Manged • Power,• Console• VLANs

• Provides 160 Gbps of full line-rate processing bandwidth

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NetFPGAs in the Internet 2 & Japan

From GENI Engineering Conference – Oct 2008

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UCSD-NetFPGA Cluster

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Preview of Upcoming 2.0 Release

• Modular Registers– Shares – Project registers specified by XML list– Joined together at build time

• Packet buffering in DRAM– Deep buffer–

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Conclusions

• NetFPGA Provides– Open-source, hardware-accelerated Packet Processing– Modular interfaces arranged in reference pipeline – Extensible platform for packet processing

• NetFPGA Reference Code Provides– Large library of core packet processing functions– Scripts and GUIs for simulation and system operation– Set of Projects for download from repository

• The NetFPGA Community of Developers use– Well defined functionality defined by regression tests– Blogs that organize projects– Wiki pages that Document contributions– Forum for discussion of feedback from users

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NetFPGA 2008 Summer Camp

• Format : One week event at Stanford – 2.5 Days of Training on the reference router– 2 Days to work on projects– Final Projects presented on Friday Afternoon

• Participants– Professors– Graduate Students– Engineers from Industry

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NetFPGA Developers WorkshopAugust 13-14, 2009 at Stanford University

• You already know that the NetFPGA implements a Gigabit NIC, a hardware-accelerated Internet router, a traffic generator, an OpenFlow switch, a NetFlow probe and more. What else can it do? We invite you, our worldwide NetFPGA Developers, to show off your project. Submit a paper to describe your project, prepare a demo, and come to Stanford in August to demonstrate your work!

• Papers Due: – April 20, 2009

• Workshop Date: – Aug. 13-14, 2009

• Paper Format: – 4-8 page, ACM-style

• Demonstrations: – Run on NetFPGA(s)

• Program Chairs:– John W. Lockwood (Stanford University)– Andrew W. Moore (Cambridge University)

• Full Details– http://NetFPGA.org/DevWorkshop

“What have you built with your NetFPGA?”

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Additional Slides

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Need Help? – See Discussion Forums

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NetFPGA Hardware in North AmericaUSA - Jan 2009

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NetFPGA Hardware in EuropeEU - Jan 2009

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NetFPGA Hardware in Asia

China, Korea, Japan, Taiwan - Jan 2009

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AcknowledgementsSupport for the NetFPGA project is provided by the following organizations, companies, and institutions

Disclaimer: Any opinions, findings, conclusions, or recommendations expressed in this material do not necessarily reflect the views of the National Science Foundation or of any other sponsors supporting this project.

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Learn more About the NetFPGA

http://NetFPGA.org/-or-

Google: “NetFPGA”