NATIONAL RADIO ASTRONOMY OBSERVATORY … · of the stored data is sent over a 16-bit wide data...

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NATIONAL RADIO ASTRONOMY OBSERVATORY Charlottesville, Virginia ELECTRONICS DIVISION TECHNICAL NOTE NO. 154 Title: 140-ft MODCOMP CONTROL COMPUTER DATA OUTPUT Author(s): Ronald B. Weimer Date: April 25, 1989 DISTRIBUTION: GB CV TU VLA GB Library ER Library Library Downtown VIA Library R. Lacasse IR Library Library Mountain P. Napier R. Weimer M. Balister J. Payne J. Campbell D. Schiebel C. Burgess R. Freund W. Brundage E. Childers S-K Pan J. Lamb C. Brockway A. R. Kerr D. Emerson J. Coe N. Bailey P. Jewell R. Norrod S. Srikanth J. Cochran S. White L. D'Addario A. Perfetto G. Behrens N. Horner R. Fisher F. Crews B. Peery

Transcript of NATIONAL RADIO ASTRONOMY OBSERVATORY … · of the stored data is sent over a 16-bit wide data...

NATIONAL RADIO ASTRONOMY OBSERVATORYCharlottesville, Virginia

ELECTRONICS DIVISION TECHNICAL NOTE NO. 154

Title: 140-ft MODCOMP CONTROL COMPUTER DATA OUTPUT

Author(s): Ronald B. Weimer

Date: April 25, 1989

DISTRIBUTION:

GB CV TU VLAGB Library ER Library Library Downtown VIA LibraryR. Lacasse IR Library Library Mountain P. NapierR. Weimer M. Balister J. Payne J. CampbellD. Schiebel C. Burgess R. Freund W. BrundageE. Childers S-K Pan J. LambC. Brockway A. R. Kerr D. EmersonJ. Coe N. Bailey P. JewellR. Norrod S. Srikanth J. CochranS. White L. D'Addario A. PerfettoG. Behrens N. HornerR. FisherF. CrewsB. Peery

140-FT MODCOMP CONTROL COMPUTER DATA OUTPUT

Ronald B. Weimer

Introduction

The control computer at the 140-ft telescope collects observing data,stores it on the disk and does some preliminary data reduction. The data comesfrom the autocorrelator, digital standard receiver, or A/D converter. Loginformation is also included along with the data At the present time a copyof the stored data is sent over a 16-bit wide data channel to the analysisModcomp. In order to improve the data analysis at the telescope we needed tomake the data available in real time to a more modern computer system. Noethernet interface to the Modcomp computers is available. Changing the programsto handle a new interface would be difficult. What we tried to do is developan interface that would be transparent to the current program and hardware. Itturned out that Bob Vance, Ron Maddalena, and Allen Farris modified the datatransmission program slightly to make synchronization easier. The originalintent was to pipe the data to a Sun model 3/60 workstation. It would acceptthe data, convert Modcomp floating point numbers to standard numbers, store thedata on disk, and make it available for reduction either on itself or over theethernet loop to a remote terminal. We got the data link running but had troublewith missing data when the Sun got busy doing data reduction. As a consequence,the system was modified so that the data is first piped to an Apple Mac II whichmodifies the numbers and sends it over ethernet to the Sun. This reportdescribes the electronics in the Modcomp that captures the control computer toanalysis computer data stream and transmits it to the Mac II.

Description of Electronics

The Modcomp link was built on a General Purpose Controller by DwayneSchiebel. The signals of interest are 16 bits of data (OUT1N to OUT16N), anoutput data strobe (OUDCM), a transfer initiate signal (XFERN), and Master Clear(ICBFB). A 5 MHz clock (CLKFBN) was brought in but was not used. The input dataword is broken up into two 8-bit bytes, stored in a first in/first out (FIFO)memory and then sent to the Mac II over an RS-232 serial-data link.

The maximum buffer size was around 5000 16-bit words. The FIFO will handle12 K bytes--3 each 4 K x 9 bits.

Figure 1 schematic. The FIFO's are cleared by Master Clear or by thestart of a new Modcomp transfer (6G). Data input is bussed thru the 74LS240(9C, 9D) into the input of the FIFO's (11A, 11B, 11C). A 4.90 MHz crystaloscillator (0) is used for local clocks and the baud rates for the serial datalinks. A data sheet is included on the IDT 7204 used as a FIFO.

figure 2 schematic. An OUDCMN pulse starts a sequence of loading 2 bytesinto the FIFO input (7F, 7E). OEMS and OELS selects which byte is to be loaded,and W signal strobes the data into the FIFO. The FIFO output buss QO thru Q7is used on page 3. EF signal (6F, 6A) is high if all 3 chips are empty.

2

Figure 3 schematic. Chip 6D divides the crystal oscillator clock down toprovide baud rate clocks. Note: A switch is shown for baud rate select but only9600 should be used. EF is gated with either DTR or the XON/XOFF signal (sheet5) to initiate the serial data out. DTR is not used in the Mac II link. Chips7B, 7C, 7D, and 8B generate the signals to read a byte out of the FIFO, load itin a shift register, and shift the data out. Chips 7A and 8A form the data shiftregister. The chip in 1B shifts the TTL level to RS-232 signal levels. A datasheet for this chip is also included. One TTL to RS-232 circuits is not used.The same chip shifts RS-232 levels back to TTL. One circuit is used for the DTRsignal and one for the receive data on page 5.

Figure 4 schematics. These circuits are for test only. To use, the ribboncables from the GPC are removed and test jumpers from 4F and 4G to 8E and 8F areplugged in. A dip carrier holding two switches is then plugged into slot 4A.The jumpers and switches are in the brown folder for the circuits. Pressing thereset switch simulates a transfer initiate; then pressing the start switch loads5 K words into FIFO, which starts the serial data output sequence.

Figure 5 schematics. This is the XON/XOFF circuit added. Receive datais level shifted by the 232 chip and fed to a UART (1D). XON/XOFF is decoded(3F, 3C) and sets or resets a flip flop (3D). A data sheet for the CDP 1854 isincluded. (UART is the courtesy of Ed Childers.)

Physical Layout

The circuit was constructed on a Shalloway card, mounted in an empty slotin the same page as the Modcomp to Modcomp link transmitter. Two 16-pin ribboncables connect from the GPC to the Shalloway card. Data link connections arevia the edge connector as well as +5 V power supply. A male DB 25 connector ismounted on the back of the PCI. The Mac II cable ended up with three conductor,ground and two data. A copy of the card layout is included (Figures 6 and 7).Also, a wire list from the GPC is included (Figure 8). Wirewrap lists are notincluded. They are in the brown folder.

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leTELEDYNE SEMICONDUCTORThe Analog Signal Processing Company

TSC232 Dual RS-232 Transmitter/Receiver

General DescriptionThe TSC232 from Teledyne Semiconductor is a

dual RS-232 transmitter/receiver that complies withElA RS-232C guidelines and is ideal for all RS-232Ccommunication links. This device has a 5 V powersupply and two charge pump voltage converters thatproduce +10 V/-10 V power supplies.

The TSC232 has four level translators. Two areRS-232 transmitters that convert TTL/CMOS inputlevels to 9 V RS-232 outputs. The other twotranslators are RS-232 receivers that convert RS-232inputs to 5 V TTUCMOS output levels. Thereceivers have a nominal threshold of 1.3V, a typicalhysteresis of 0.5 V, and can operate with up to ±30 Vinputs.

Functional Diagram

Features• Meets all RS-232C Specifications• Operates from Single 5 V Power Supply• 2 Drivers and 2 Receivers• Onboard Voltage Quadrupler• ±30V input Levels• ±9 V Output Swing with +5 V Supply• Low Power CMOS: 5 mA

CALL 1-800-888-9966

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RAMARRAY2048 a 940961 9

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MILITARY AND COMMERCIAL TEMPERATURE RANGESantes Inhogvated Donn. Technology, Inc.Prmted in U.S.A.

FEBRUARY 1986Pfiro•• In U S A

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FEATURES:• First-tn. First-Out dual port memory• 2048 x 9 organization (IDT7203)• 4096 x 9 organization ((017204)• Low power consumption

—Active: 660mW (max.)—Power down: 66mW (max.)

• Asynchronous and simultaneous read and write• Fully expandable by both word depth and/or bit width• Pin and functionally compatible with IDT7201/02• I017204 allows 4096 word structure without expansion• Half-full flag capability in single device mode• Master/slave multiprocessing applications• Bidirectional and rate buffer applications• Empty and full warning flags• Auto retransmit capability• High-performance CEMOS" II technology• Available in DIP and LCC• Military product available 100% screened to MIL-STD-883,

Class B

DESCRIPTION:The 017203/7204 is a dual port memory that utilizes a special

First-In, First-Out algorithm that loads and empties data on afirst-in, first-out basis. The device uses full and empty flags toprevent data overflow and underflow and expansion logic toallow for unlimited expansion capability in both word size anddepth.

The reads and writes are internally sequential through the useof ring pointers, with no address information required to load andunload data. Data is toggled in and out of the device through theuse of the WRITE (W) and READ (R) pins. The device has aread/write cycle time of 65ns (15MHz).

The device utilizes a 9-bit wide data array to allow for controland parity bits at the user's option. This feature is especiallyuseful in data communications applications where it is necessaryto use a parity bit for transmission/reception error checking. Italso features a RETRANSMIT (RI) capability that allows for resetof the read pointer to its initial position when RI is pulsed low toallow for retransmission from the beginning of data. A half-fullflag is available in the single device mode and width expansionmodes.

The 1017203/7204 is fabricated using the high-speedCEMOS"II, 1.5 micron technology and is available in DIP andLCC screened to MIL-STD-883, Method 5004. It is designed forthose applications requiring asynchronous and simultaneousread/writes in multiprocessing and rate buffet' applications.The 4096 x 9 organization for the 1017204 allows a 4096 deepword structure without the need for expansion.

PIN CONFIGURATIONS FUNCTIONAL BLOCK DIAGRAM

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05P7203-001CBAOS is a trademark of Integrated Device Technology, Inc.

I0T7203/10T7204 CMOS PARALLELFIRST-IN/FIRST-OUT FIFO 2048 x 9-BIT & 4096 x 9-811 MILITARY AND COMMERCIAL TEMPERATURE RANGES

SIGNAL DESCRIPTIONS:INPUTS:

DATA IN (DO - D8)Data inputs for 9-bit wide data.

CONTROLS:

RESET (Rs)Reset is accomplished whenever the RESET (RS) input is

taken to a low state. During reset, both internal read and writepointers are set to the first location. A reset is required afterpower up before a write operation can take place. Both theREAD ENABLE (P) and WRITE ENABLE (W) inputs must bein the high state during reset. HALF FULL FLAG (HF) will bereset to high after master RESET (RS).

WRITE ENABLE (W)A write cycle is initiated on the falling edge of this input if

the FULL FLAG ( R) is not set. Data setup and hold timesmust be adhered to with respect to the rising edge of theWRITE ENABLE (W). Data is stored in the RAM arraysequentially and independently of any ongoing readoperation.

After half of the memory is filled. and at the falling edge ofthe next write operation, the HALF FULL FLAG (HF) will beset to low and will remain set until the difference between thewrite pointer and read pointer is less than or equal to one halfof the total memory of thedevice. The HALF FULL FLAG (HF)is then reset by the rising edge of the read operation.

To prevent data overflow, the FULL FLAG (FP) will go low,inhibiting further write operations. Upon the completion of avalid read operation, the FULL FLAG (FF) will go high aftertRFF, allowing a valid write to begin.

READ ENABLE (g)A read cycle is initiated on the falling edge of the READ

ENABLE (R) provided the EMPTY FLAG (EF) is not set. Thedata is accessed on a First-In, First-Out basis independent ofany ongoing write operations. After READ ENABLE (A) goeshigh, the Data Outputs (QO through 08) will return to a highimpedance condition until the next READ operation. Whenall the data has been read from the FIFO, the EMPTY FLAG(EF) will go low, inhibiting further read operations with thedata outputs remaining in a high impedance state. Once avalid write operation has been accomplished, the EMPTYFLAG (EF) will go high after twEF, and a valid READ can thenbegin.

FIRST LOAD/RETRANSMIT (FL/RT)This is a dual purpose output. In the Multiple Device Mode,

this pin is grounded to indicate that it is the first device

loaded. (See Operating Modes.) In the Single DeviceMode, this pin acts as the retransmit input. The SingleDevice Mode is initiated by grounding the EXPANSION IN(XI).

The IDT7203/4 can be made to retransmit data when theRETRANSMIT ENABLE CONTROL (RT) input is pulsedlow. A retransmit operation will set the internal read pointerto the first location and will not affect the write pointer.READ ENABLE (R) and WRITE ENABLE (W) must be in thehigh state during retransmit. This feature is useful whenless than 2048/4096 writes are performed between resets.The retransmit feature is not compatible with Depth Expansion Mode and will affect HALF FULL FLAG (HF)depending on the relative locations of the read and writepointers.

EXPANSION IN (II)This input is a dual purpose pin. EXPANSION IN (XI) is

grounded to indicate an operation in the single device mode.EXPANSION IN (XI) I S connected to EXPANSION OUT (XO)of the previous device in the Depth Expansion or Daisy ChainMode.

OUTPUTS:FULL FLAG (FF)

The FULL FLAG (FF) will go low, inhibiting further writeoperation, when the write pointer is one location from theread pointer, indicating that the device is full. If the readpointer is not moved after RESET (RS), the FULL FLAG(FF) will go low after 2048 writes for the IDT7203 and 4096writes for the IDT7204.

EXPANSION OUT/HALF FULL FLAG (XO/HF)This is a dual purpose output. In the single device.mode,

when EXPANSION IN (RI) is grounded, this output acts as anindication of a half full memory.

After half of the memory is filled, and at the falling edge ofthe next write operation, the HALF FULL FLAG (HF) will beset to low and will remain set until the difference between thewrite pointer and read pointer is less than or equal to one halfof the total memory of the device. The HALF FULL FLAG (HF)is then reset by the rising edge of the read operation.

In the Multiple Device Mode, EXPANSION IN (TO isconnected to EXPANSION OUT (X0) of the previous device.This output acts as a signal to the next device in the DaisyChain by providing a pulse to the next device when theprevious device reaches the last location of memory.

DATA OUTPUTS (00 - 08)Data outputs for 9-bit wide data. This output is in a high

imedance condition whenever READ (A) is in a high state.

tas

NOTES:/. /RSC /RS /RSR.

2. W and q = v,„ during RESET.Figure 2 Reset DSP7201-005

4-24

IDT7203110T7204 CMOS PARALLELFIRST-IN/FIRST-OUT FIFO 2048 x 9-BIT & 4096 x 9-BIT MILITARY AND COMMERCIAL TEMPERATURE RANGES

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LAST WRITE FIRST READ ADDITIONALREADS

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IDT7203/IDT7204 CMOS PARALLELFIRST-IN/FIRST-OUT FIFO 2048 x 9-BIT & 4096 x 9-BIT MILITARY AND COMMERCIAL TEMPERATURE RANGES

OPERATING MODES:SINGLE DEVICE MODE

A single DT7203/4 may be used when the application require-ments are for 2048/4096 words or less. The IDT7203/4 is in aSingle Device Configuration when the EXPANSION IN (T) con-trol input is grounded. (See Figure 10.) In this mode the HALFFULL FLAG (HF), which is an active low output, is shared withEXPANSION OUT (TO).

(HALF FULL FLAG) ITO'

WRITE ( W) (R) READ

9

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9

DATA IN / (0) (0) DATA OUT

FULL FLAG (FF) (FE) EMPTY FLAG

DEPTH EXPANSION (DAISY CHAIN) MODEThe IDT7203/4 can easily be adapted to applications when the

requirements are for greater than 2048/4906 words. Figure 12demonstrates Depth Expansion using three IDT7203/4s. Anydepth can be attained by adding additional IDT7203/4s. TheI DT7203/4 operates in the Depth Expansion configuration whenthe following conditions are met:

1. The first device must be designed by grounding the FIRSTLOAD ( rt. ) control input.

2. All other device must have VC in the high state.3. The EXPANSION OUT (XO) pin of each device must be tied to

the EXPANSION IN (Xi) pin of the next device. See Figure 12.4. External logic is needed to generate a composite FULL FLAG

(FF) and EMPTY FLAG (EF). This requires the ORing of all EFsand ORing of all FFs. (I e. all must be set to generate the correctcomposite FF or E. -E). See Figure 12.

5. The RETRANSMIT (RT) function and HALF FULL FLAG (HF)are not available in the Depth Expansion Mode.

COMPOUND EXPANSION MODEThe two expansion techniques described above can be applied

together in a straightforward manner to achieve large FIFO arrays.(See Figure 13.)

RESET (RS) (AT) RETRANSMIT.41

EXPANSION IN (XI) tDSP7203-003

Figure 10. Block Diagram of Single 2048 x 9/4096 x 9 FIFO

WIDTH EXPANSION MODEWord width may be increased simply by connecting the cor-

responding input control signals of multiple devices. Status flags(ET, FF and HF) can be detected from any one device. Figure 11demonstrates an 18-bit word width by using two IDT7203/4s. Anyword width can be attained by adding additional I DT7203/4s.

DATAIN (D)

WRITE (w)1.••••••••

FULL FLAG (FF)41

RESET(RS)

( VT) RETRANSMIT

BIDIRECTIONAL MODEApplications which require data buffering between two systems

(each system capable of READ and WRITE operations) can beachieved by pairing IDT7203/4s as is shown in Figure 14. Caremust be taken to assure that the appropriate flag is monitored byeach system. (I.e. r-E- is monitored on the device where T.,C, is used;EF is monitored on the devtce where A is used.) Both DepthExpansion and Width Expansion may be used in this mode.

DATA FLOW THRU MODESTwo types of flow through modes are permitted with the

I DT7203/7204. A read flow through and write flow through mode.For the read flow through mode (Figure 15), the FIFO permits areading of a single word of data immediately after writing oneword of data into the completely empty FIFO.

In the write flow through mode (Figure 16), the FIFO permits awriting of a single word of data immediately after reading oneword of data from a completely full FIFO.

(DI7203/4 IOT

7203/4

411,

(R) READ

EMPTY FLAG

kit

DSP7203-004NOTES:Flag detection is accomplished by monitoring the FF, EF, and the Hi

,' signals on

either (any) device used in the width expansion configuration. Do not connectany output control signals together.

Figure 11. Block Diagram of 2048 x 18/4096 x 18 FIFO MemoryUsed in Width Expansion Mode

4-27

E?

XI

vcc

EMPTY

RS

CFI DT

7203/4

CF

FL,

FL

X0

I DT7203/4

I DT7203/4

I0T7203/ID17204 CMOS PARALLELFIRST-1N/FIRST-OUT FIFO 2048 x 9-BIT & 4096 x 9-BIT MILITARY AND COMMERCIAL TEMPERATURE RANGES

TRUTH TABLESTABLE I - RESET AND RETRANSMIT -SINGLE DEVICE CONFIGURATION/WIDTH EXPANSION MODE

MODEINPUTS INTERNAL STATUS OUTPUTS

RS RT Ri Read Pointer Write Pointer ET FF HF

Reset 0 X 0 Location Zero Location Zero 0 1 1

Retransmit 1 0 0 Location Zero Unchanged X X X

Read/Write 1 1 0 Increment(1) Increment(1) X X XNOTE:1. Pointer will increment it flag is high.

TABLE II - RESET AND FIRST LOAD TRUTH TABLE -DEPTH EXPANSION/COMPOUND EXPANSION MODE

MODEINPUTS INTERNAL STATUS OUTPUTS

RS FL -ii.

Read Pointer Write Pointer EF FF

Reset-First Device

.

0 0 (1) Location Zero Location Zero 0 1

Reset all Other Devices

0 1 (I)

.

Location Zero Location Zero 0 1

Read/Write 1 X (1) _ X X X XNOTES:

1. R-1 is connected to X0 of previous device. See Figure 12RS = Reset Input. FLAT = First Load/Retransmit, = Empty Flag Output. = Full Flag Output. TI = Expansion Input. HF = Half Full Flag Output.

DSP7203-005Figure 12. Block Diagram of 6,144 x 9/12,288 x 9 FIFO Memory (Depth Expansion)

4-28

CDP1854ADCOP1854ACO H-1891

CDP1854AECOP1854ACE 14-1892

2-3456

34 CRL.33 T BUS 7

9 T BUS 610 31 T BUS 5

30 — T BUS 412 291-- T BUS 313 281— T 8US 21 4 271— T BUS Ii s 26 T BUS 016 25 SOO17 24 TSRE1 8 23 THRLi9 22 THRE20 21 MR

40 T CLOCK39 EPE38 WLS I37 WLS 236 S8S35 PI

NC • NO CONNECTION92CS-28455.

TOP VIEWPIN 2 NO CONNECTIONON COP6402 qcs. .456.

Mode 1Terminal Assignment

Mode 0Terminal Assignment

CMOS Peripherals 315

CDP1854A, CDP1854AC

ProgrammableUniversal AsynchronousReceiver/Transmitter (UART)Features:• Two operating modes: • Baud rate-DC to 200 K bits/sec

Mode 0-functionally compatible with VDD=5 Vindustry types such as the TR1602A DC to 400 K bits/secMode 1-interfaces directly with VDD=10 VCDP1800-series microprocessors • Fully programmable with externally se•without additional components lectable word length (5-8 bits), panty

▪ Full- or half duplex operation inhibit, even/odd parity, and 1, /1/2, or• Parity, framing, and overrun error 2 stop bits

detection I False start bit detection

T he RCA CDP1854A and CDP1854AC are silicon-gateCMOS Universal Asynchronous Receiver/Transmitter'UART) circuits. They are designed to provide the necessary'ormatting and control for interfacing between serial and:arailel data. For example, these UARTs can be used tof, terface between a peripheral or terminal with serial I/O:orts and the 8-bit CDP1800-series microprocessor parallel:ata bus system. The C0P1854A is capable of full duplexz eration. i.e., simultaneous conversion of serial input data

parallel output data and parallel input data to serial:utput data.

The CDP1854A UART can be programmed to operate inOne of two modes by using the mode control input. Whenhe mode input is high (MODE=1), the CDP1854A is

directly compatible with the CDP1800-series micro-processor system without additional interface circuitry.When the mode input is low (MODE=0), the device isfunctionally compatible with industry standard UART'ssuch as the TR1602A. It is also pin compatible with thesetypes. except that pin 2 is used for the mode control inputinstead of a VGG .---12 V supply connection.

The CDP1854A and the CDP1854AC are functionallyidentical. The CDP1854A has a recommended operating-voltage range of 4-10.5 volts. and the CDP1854AC has arecommended operating voltage range of 4-6.5 volts.

The CDP1854A and CDP1854AC are supplied in hermetic40-lead dual-in-line ceramic packages (D suffix) and in40-lead dual-in-line plastic packages (E suffix). TheCDP1854AC is also available in chip form (H suffix).

VDD T CLOCK2 39MODE tYpa) — CTS yoo

VSS 3 38 ES `MOOENss)tr"S-2 4 37 PSt VSS

R BUS 7 — 5 36 --- NC RROR SUS 6 6 35 — CS3 R BUS 7R BUS 5 7 34 RO/WR R BUS 6R BUS 4 33 T 8US 7 R BUS 5R BUS 3 9 32 T BUS 6 R BUS 4R BUS 2 -- 1 0, 31 T BUSS R SUS 3R BUS 1 11 /30 T 8US4 R BUS 2R BUS 0 12 i 29 T BUS 3 R BUS 1

iNT 13 / \ 28 T OUS 2 R BUS 0FE --- 4 / 27 T BUS 1 PE

PE/OE — 15 26 T BUSO F ERSEL 16 25 SOO OE

R CLOCK -- 17 24 R TS SFOTP8 18 23 R CLOCK

(TA 19 22 THRE b—A-4

SOI 20 21 — CLEAR CA

TOP VIEW SOX

File Number 1193

TPA

SCI

TCPU PB

COP i800NO

EF3

/ T CLOCK R CLOCK

Pi

DAR

RRD

SAS

%QS,

WLS2

EPETHRL

UARTCDPI854A

TSRE

....-••••••••••••<<1■•••••■ DA

(8) T BuS SDI

SDOR BUS

MR MODE

1

VSS

92CS-34506

CLEAR

DMAI

BUS

326 CMOS Microprocessors, Memories and Peripherals

CDP1854A, CDP1854AC

Functional Definitions for CDP1854A TerminalsStandard Mode 0

SIGNAL: FUNCTIONVol):Positive supply voltage.

MODE SELECT (MODE):A low-level voltage at this input selects Standard Mode 0Operation.

VSS:Ground.

RECEIVER REGISTER DISCONNECT (RRD):A high-level voltage applied to this input disconnects theReceiver Holding Register from the Receiver Bus.RECEIVER BUS (R BUS 7 - R BUS 0):Receiver parallel data outputs.PARITY ERROR (PE):A high-level voltage at this output indicates that thereceived parity does not compare to that programmed bythe EVEN PARITY ENABLE (EPE) control. This output isupdated each time a character is transferred to the ReceiverHolding Register. PE lines from a number of arrays can bebused together since an output disconnect capability isprovided by the STATUS FLAG DISCONNECT (SFD) line.FRAMING ERROR (FE):A high-level voltage at this output indicates that thereceived character has no valid stop bit, i.e., the bitfollowing the parity bit (if programmed) is not a high-levelvoltage. This output is updated each time a character istransferred to the Receiver Holding Register. FE lines froma number of arrays can be bused together since an outputdisconnect capability is provided by the STATUS FLAGDISCONNECT (SFD) line.OVERRUN ERROR (OE):A high-level voltage at this output indicates that the DATAAVAILABLE (DA) flag was not reset before the nextcharacter was transferred to the Receiver Holding Register.OE lines from a number of arrays can be bused togethersince an output disconnect capability is provided by theSTATUS FLAG DISCONNECT (SFD) line.

STATUS FLAG DISCONNECT (SFD):A high-level voltage applied to this input disables the 3-state output drivers for PE, FE, OE, DA, and THRE, allowingthese status outputs to be bus connected.

RECEIVER CLOCK (RCLOCK):Clock input with a frequency 16 times the desired receivershift rate.DATA AVAILABLE RESET (DAR):A low-level voltage applied to this input resets the DAflip-flop.DATA AVAILABLE (DA):A high-level voltage at this output indicates that an entirecharacter nas been received and transferred to the ReceiverHolding Register.SERIAL DATA IN (SDI):Serial data received at this input enters the receiver shiftregister at a point determined by the character length. Ahigh-level voltage must be present when data is not beingreceived.MASTER RESET (MR):A high-level voitage at this input resets the ReceiverHolding Register. Control Register, and Status Register,and sets the serial data output high.

TRANSMITTER HOLDING REGISTER EMPTY (THRE):A high-level voltage at this output indicates that theTransmitter Holding Register has transferred its contentsto the Transmitter Shift Register and may be reloaded witha new character.TRANSMITTER HOLDING REGISTER LOAD (THRL):A low-level voltage applied to this input enters the characteron the bus into the Transmitter Holding Register. Data islatched on the trailing edge of this signal.TRANSMITTER SHIFT REGISTER EMPTY (TSRE):A high-level voltage at this output indicates that theTransmitter Shift Register has completed serial transmissionof a full character including stop bit(s). It remains at thislevel until the start of transmission of the next character.SERIAL DATA OUTPUT (SDO):The contents of the Transmitter Shift Register (start bit,data bits, parity bit, and stop (bit(s)) are serially shifted outon this output. When no character is being transmitted, ahigh-level is maintained. Start of transmission is defined asthe transition of the start bit from a high-level to a low-leveloutput voltage.

TRANSMITTER BUS (T BUS 0 - T BUS 7):Transmitter parallel data inputs.CONTROL REGISTER LOAD (CRL):A high-level voltage at this input loads the Control Registerwith the control bits (PI, EPE, SBS, WLS1, WLS2). This linemay be strobed or hardwired to a high-level input voltage.PARITY INHIBIT (PI):A high-level voltage at this input inhibits the parity genera-tion and verification circuits and will clamp the PE outputlow. If parity is inhibited the stop bit(s) will immediatelyfollow the last data bit on transmission.STOP BIT SELECT (SBS):This input selects the number of stop bits to be transmittedafter the parity bit. A high-level selects two stop bits, alow-level selects one stop bit. Selection of two stop bitswith five data bits programmed selects 1.5 stop bits.

Fig. 8 - Mode 0 connection diagram.

CMOS Peripherals 327

CDP1854A, CDP1854AC

DYNAMIC ELECTRICAL CHARACTERISTICS at TA = -40 to +85°C, VDD ±5%, 4,4=20 flS VIHO 7 VDD, VIL=0.3 VDD,CL= 100 pF, see Flg. 9.

LIMITS

CHARACTERISTIC VDD CDP1854A CDF'1854AC UNITS

(V) Typ. Max.* Typ.' Max.*Interface Timing — Mode 0

Minimum Pulse Width: 5 100 150 100 150ns

CRL tCAL 10 50 75 —Minimum Pulse Width: 5 200 400 200 400

MR tmR 10 100 200 — —ns

.1ini mum Setup Time: 5 40 80 40 80. Control Word to CAL tcwc 10 20 50 — —

ns

Minimum Hold Time: 5 100 150 100 150Control Word after CAL tCCW 10 50 75 —

ns

P ropagation Delay Time: 5 200 300 200 300ns

SFD High to SOD tSFDH 10 100 150 — —

SFD Low to SOD tS F DL

RRD High to Receiver Register11 H i gh Impedance RON4:I

11111111111111111111

,

RRD Low to Receiver Register Active tARDL

itcaI values are for TA=25°C and nominal voltages.• Vaximum limits of minimum characteristics are the values above which all devices function.

CONTROL INPUT WORD TIMING

CONTROL WORDINPUT

tcwc

CRL

tcRL

STATUS OUTPUT TIMING

STATUSOUTPUTS

SP01.1.—

SPD

RECEIVER REGISTER DISCONNECT TIMING

R BUS O-R BUS 7

HRRDL.4

92Cm- 3,875

RR()

Fig. 9 - Mode 0 interface timing diagram.

WLS2 WLS1 Word LengthLowLowHighHigh

LowHigh

LowHigh

5 Bits6 Bits7 Bits8 Bits

328 CMOS Microprocessors, Memories and Peripherals

CDP1854A, CDP1854AC

WORD LENGTH SELECT 2 (WLS2):WORD LENGTH SELECT 1 (WLS1):These two inputs select the character length (exclusive ofparity) as follows:

EVEN PARITY ENABLE (EPE):A high-level voltage at this input selects even parity to begenerated by the transmitter and checked by the receiver. Alow-level input selects odd parity.TRANSMITTER CLOCK (TCLOCK):Clock input with a frequency 16 times the desired transmittershift rate.

Description of Standard Mode 0 Operation( Mode input.Vss)

1. Initialization and ControlsThe MASTER RESET (MR) input is pulsed. resetting theControl. Status, and Receiver Holding Registers and settingthe SERIAL DATA OUTPUT (SDO) signal high. Timing isgenerated from the clock inputs, Transmitter Clock(TCLOCK) and Receiver Clock (RCLOCK), at a frequencyequal to 16 times the serial data bit rate. When the receiverdata input rate and the transmitter data output rate are thesame. the TCLOCK and RCLOCK inputs may be connectedtogether. The CONTROL REGISTER LOAD (CRL) input ispulsed to store the control inputs PARITY INHIBIT (PI),EVEN PARITY ENABLE (EPE), STOP BIT SELECT (SBS).and WORD LENGTH SELECTs (WLS1 and WLS2). Theseinputs may be hardwired to the proper voltage levels (Vssor VDD) instead of being dynamically set and CRL may behardwired to VDD. The CDP1854A is then ready fortransmitter and/or receiver operation.

2. Transmitter OperationFor the transmitter timing diagram refer to Fig. 10. At thebeginning of a typical transmitting sequence the TransmitterHolding Register is empty (THRE is HIGH). A character istransferred from the transmitter bus to the Transmitter

holding Register by applying a low pulse to the TRANS-MITTER HOLDING REGISTER LOAD (THAL) input causingTHRE to go low. If the Transmitter Shift Register is empty(TSRE is HIGH) and the clock is low, on the next high-to-low transition of the clock the character is loaded into theTransmitter Shift Register preceded by a start bit. Serialdata transmission begins 1/2 clock period later with a stallbit and 5-8 data bits followed by the parity bit (if pro-grammed) and stop bit(s). The THRE output signal goeshigh 1/2 clock period later on the high-to-low transition ofthe clock. When THRE goes high, another character can beloaded into the Transmitter Holding Register for trans-mission beginning with a start bit immediately following thelast stop bit of the previous character. This process isrepeated until all characters have been transmitted. Whentransmission is complete, THRE and Transmitter ShiftRegister Empty (TSRE) will both be high. The format ofserial data is shown in Fig. 12. Duration of each serialoutput data bit is determined by the transmitter clockfrequency (fCLOCK) and will be 16/f CLOCK.

3. Receiver OperationThe receive operation begins when a start bit is detected atthe SERIAL DATA IN (SDI) input. After the detection of ahigh-to-low transition on the SDI line, a divide-by-16counter is enabled and a valid start bit is verified bychecking for a low-level input 7-1/2 receiver clock periodslater. When a valid start bit has been verified, the followingdata bits, parity bit (if programmed), and stop bit(s) areshifted into the Receiver Shift Register at clock pulse 7-1/2in each bit time. If programmed, the parity bit is checked,and receipt of a valid stop bit is verified. On count 7-1/2 ofthe first stop bit, the received data is loaded into theReceiver Holding Register. If the word length is less than 8bits, zeros (low output voltage level) are loaded into theunused most significant bits. If DATA AVAILABLE (DA)has not been reset by the time the Receiver HoldingRegister is loaded, the OVERRUN ERROR (OE) signal israised. One-half clock period later, the PARITv ERROR(PE) and FRAMING ERROR (FE) signals become valid forthe character in the Receiver Holding Register. The DAsignal is also raised at this time. The 3-state output driversfor DA, OE. PE and FE are enabled when STATUS FLAGDISCONNECT (SFD) is low. When RECEIVER REGISTERDISCONNECT (RRD) goes low, the receiver bus 3-stateoutput drivers are enabled and data is available at theRECEIVER BUS (R BUS 0 - R BUS 7) outputs. Applying anegative pulse to the DATA AVAILABLE RESET (DAR)resets DA. The preceding sequence of operation is repeatedfor each serial character received. A receiver timing diagramis shown in Fig. 11.

'Typical values are for TA=25°C and nominal voltages.

*Maximum limits of minimum characteristics are the values above which all devices function.

** TRANSMITTER SHIFT*TRANSMITTER HOLDING REGISTER LOADED

REGISTER LOADED

tcc

tcw'r.÷-4tjr4-LSL_r61_F-L5 31

tTH J 4I

I 1

...-- t THTH 1,-.41 4-t CO tr*--00

1 tPST OATA BIT

et ITHR re,- 0.-‘CT

1

T CLOCK

THRL

SOO

THRE

TSRE

T 81.15 0-T BUS 7

DATA

CMOS Peripherals 329

CDP1854A, CDP1854AC

DYNAMIC ELECTRICAL CHARACTERISTICS at TA = -40 to +85°C, VDD ±5%, 4,4 = 20 ns, Vili = 0.7 VDD, VIL= 0 .3 VDD,CL=100 pF, see Fig. 10.

CHARACTERISTIC VDD(V)

LIMITSUNITSCDP1854A CDP1854A

Typ.' Typ.* iJT

3105 250 310 250Minimum Clock Period tCC

MinimumPulseWidth: 5 100 125 100 125

115 100 125 100 125Clock High Level tCH

5 100 150 10G 150 nsTHAL tTHTH 10 50 75Minimum Setup Time:

THRL to Clock tTHC510

17590

275150 111

ligns

5 20 50 0 50 nsData to THRL tOT 10 0 40Minimum Hold Time: 5 80 120 120

nsData after THRL tTD 10 40 60P ropagation Delay Time: 5 300 450 300 450

nsClock to Data Start Bit tCD 10 150 225

Clock to THRE tcT

THRL to THR tTTHRE

1111111Clock to TSRE tTTS

THE HOLDING REGISTER IS LOADED ON THE TRAILING EDGE OF THAL** THE TRANSMITTER SHIFT REGISTER, IF EMPTY. IS LOADED ON THE FIRST HIGH-TO-LOW TRANSITION CF THE

CLOCK WHICH OCCURS AT LEAST 1/2 CLOCK PER100 ., THc AF TER THE TRAILING EDGE OF 11IRL,ANO TRANS-MISSION OF A START BIT OCCURS 1/2 CLOCK PERIOD • eco LATER

92C - 318 ?RotFig. 10 - Mode 0 transmitter timing diagram.

330 CMOS Microprocessors, Memories and Peripherals

CDP1854A, CDP1854AC= = , =DYNAMIC ELECTRICAL CHARACTERISTICS at TA = -40 to +85°C, VDD =5%, tr,tf20 ns, VIH0.7 VDD VIL0.3 VDD,

CL = 100 pF, see Fig. 11..LIMITS

,

CHARACTERISTIC VDD CDP1854A CDP1854AC UNITS(V) Typ.' I Max.* Typ.* ' Max.*

Receiver Timing — Mode 0

Minimum Clock Period tCC5

I250 310 250 310

,

ns10 125 155 — —

Minimum Pulse Width:Clock Low Level tCL

5

10

10075

125100

100

—125—

ns

Clock High Level tCH5

I 1010075

125100

.100—

125—

,

ns

tDD5 50 75 50 75

nsDATA AVAILABLE RESET10 25 40 — —

Minimum Setup Time:*

5 100 150 100 150 11 ns

Data Start Bit to Clock t DC 10 50 75 — ...... 1

Propagation Delay Time:DATA AVAILABLE RESEttoData Available tDDA

5

1015075

225125

150.....

225_

ns

Clock to Data Valid tCOV5 225 325 225 325

4

ns10 110 175 — — 4

Clock to Data Available tCDA5 225

,325 225 325

ns10 110 175 —

Clock to Overrun Error tCOE510

210100

,

300150

210—

300

—ns

Clock to Parity Error tCPE510

240120

375175

240—

375—

ns

Clock to Framing Error,

tCFE510

200_ 100

300150

200

_ —

300—

ns_

Typical values are for TA =25°C and nominal voltages.*Maximum limits of minimum characteristics are the values above which all devices function.

'CC

tCm• t"-44CL

R CLOCK

CLOCK 71/2SAMPLE CLOCK 7 LOAD HOLDING REGISTER

2 7 8

CMOS Peripherals 331

CDP1854A, CDP1854AC

.-tDC*

SrD 1

R BUS O-R BUS

START BIT PARITY / STOP BIT

;

I

t1-.1 CDA

DA.

DAq

CE**

tD0t COE -.4.

1

tCPE

FE I

t CFE

cr

K iF A START BIT OCCURS AT A TIME LESS THAN toc BEFORE A HIGH-TO-LOW TRANSITION OF THE CLOCK,E START BIT MAY NOT BE RECOGNIZED UNTIL THE NEXT HIGH-TO-LOW TRANSITION OF THE CLOCK. THE START

BIT MAY BE COMPLETELY ASYNCHRONOUS WITH THE CLOCK

K IF A PENDING DA HAS NOT BEEN CLEARED BY A READ OF THE RECEIVER HOLDING REGISTER BY THE TIME A NEW*ORD IS LOADED INTO THE RECEIVER HOLDING REGISTER, THE OE SIGNAL WILL COME TRUE.

92Cm- 318 77

Fig. 11 - Mode 0 receiver timing diagram.

' 6 " cLocK

5-8 DATA BITS

DATA,mS8

4 . BITS1/2 OR 2

PARITYBI T

STARTBIT 3 DATA

LSB

WCS.28465

Fig. 12 - Serial data word format.