National LVDS Owners Manual 4th Edition 2008

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Transcript of National LVDS Owners Manual 4th Edition 2008

LVDS Owners ManualIncluding High-Speed CML and Signal ConditioningFourth Edition

2008High-Speed Interface Technologies Overview ......... 9-13 Network Topology ................ 15-17 SerDes Architectures ........... 19-29 Termination and Translation .......................31-38 Design and Layout Guidelines ................. 39-45 Jitter Overview .................... 47-58 Interconnect Media and Signal Conditioning ............. 59-75 Semiconductor I/O Models .. 77-82 WEBENCH Online Simulation .............................. 83-88 Solutions for Design Challenges ........................... 89-108

national.com/LVDS

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LVDS Owners ManualIncluding High-Speed CML and Signal Conditioning Fourth Edition 2008

national.com/LVDS

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ContentsIntroduction ..........................................................................7 High-Speed Interface Technologies Overview..............91.1 Differential Signaling Technology....................................... 9 1.2 LVDS Low-Voltage Differential Signaling ..................... 10 1.3 CML Current-Mode Logic ................................................. 11 1.4 Low-Voltage Positive-Emitter-Coupled Logic ................. 12 1.5 Selecting An Optimal Technology ..................................... 12

Design and Layout Guidelines ........................................395.1 PCB Transmission Lines ...................................................... 39 5.2 Transmission Loss ................................................................ 40 5.3 PCB Vias ................................................................................. 41 5.4 Backplane Subsystem ......................................................... 42 5.5 Decoupling ............................................................................. 44

Jitter Overview ..................................................................476.1 Introduction............................................................................ 47 Random Jitter Characteristics...................................... 47 Deterministic Jitter......................................................... 48 Duty Cycle Distortion...................................................... 49 Inter-Symbol Interference ............................................. 50 Periodic Jitter .................................................................. 52 6.2 Additional Jitter Sources .................................................... 52 Effect of Input Capacitance ........................................... 53 FEXT/NEXT ........................................................................ 53 Systems Susceptible to Crosstalk ............................... 54 Bit Error Rate .................................................................... 54 6.3 Pattern Dependencies and Eye Diagrams........................ 55 Eye Masks ........................................................................ 57 Bathtub Curves and Eye Contours ................................ 57

Network Topology .............................................................152.1 Point-to-Point ........................................................................ 15 2.2 Multipoint / Multidrop.......................................................... 16 2.3 SerDes Architectures........................................................... 17 2.4 Mixing Signaling Technologies ......................................... 17 2.5 Selecting an Interface Technology ................................... 17

SerDes Architectures .......................................................193.1 Introduction............................................................................ 19 3.2 Parallel Clock SerDes.......................................................... 19 3.3 Embedded Clock (Start-Stop) Bits SerDes ....................... 20 3.4 8b/10b SerDes ........................................................................ 21 3.5 FPGA-Attach SerDes ............................................................ 22 3.6 Applications........................................................................... 23 Parallel Clock SerDes .................................................... 23 Embedded Clock (Start-Stop) Bits SerDes ................. 24 8b/10b SerDes .................................................................. 26 FPGA-Attach SerDes ...................................................... 27 3.7 Comparison Overview.......................................................... 28 3.8 Summary ................................................................................. 29

Interconnect Media and Signal Conditioning ..............597.1 Physical and Electrical Cable Characteristics ............... 59 7.2 Signal-Conditioning Characteristics ................................ 63 Media Losses in Cables and PCB Traces ................... 63 Pre-Emphasis and De-Emphasis Drivers .................... 64 Equalization ...................................................................... 65 Two Types of Equalizer Circuits ................................... 66 Passive: Power-Saver Equalizers ................................ 66 Active Equalizers ............................................................ 66 Fixed Equalizers .............................................................. 67 Variable Equalizers Allow Control............................... 67 Adaptive Equalizers ........................................................ 67 Crosstalk ........................................................................... 68 Reections ........................................................................ 68

Termination and Translation............................................314.1 Terminations and Impedance Matching........................... 31 4.2 Multidrop and Multipoint .................................................... 31 4.3 AC Coupling ........................................................................... 32 4.4 DC Balance ............................................................................ 33 Selecting a Capacitor..................................................... 34 4.5 Translation ............................................................................. 35 4.6 Failsafes ................................................................................. 37 M-LVDS Failsafes ............................................................ 38

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Contents7.3 Using Pre- and De-Emphasis and Equalizers Together . 70 7.4 Random Noise ....................................................................... 70 7.5 Re-clocking Receivers (Re-clockers)............................... 71 7.6 Bit Error Rate (BER) and Jitter (Random and Deterministic) ............................................... 72 Lossy Media Compensated by Equalization............... 72 Pre-Emphasis Eye Diagrams ......................................... 74 PE/EQ Combination ......................................................... 75 10.2 System Clock Distribution ................................................ 92 ATCA-Synchronization Clock Interface ...................... 92 MicroTCA-Synchronization Clock Interface.............. 93 10.3 Complementing FPGA Performance ............................... 94 Extending SerDes Enables FPGAs ............................... 94 Load Capacitance is Critical......................................... 95 LVDS Translation ............................................................. 96 10.4 Broadcast Video ................................................................. 97 10.5 Extending the Reach of SerDes ....................................... 98 Identifying Cable-Extender-Chipset Benets ............ 99 Typical Transmission Distance Gains ....................... 100 Extending Signal Transmission with Conditioning.100 Power-Saver Equalizers .............................................. 101 10.6 M-LVDS: A High-Speed, Short-Reach Alternative to RS-485............................................................................. 102 10.7 Redundancy ....................................................................... 103 10.8 Testability of High-Speed Differential Networks ....... 104 Functional Testing ......................................................... 106 Loopback ........................................................................ 106 10.9 DVI / HDMI ......................................................................... 107 High Data Rates and Longer Cost-Effective Cables 107 Compensation for Skin Effects and Dielectric Losses .......................................................... 107

Semiconductor I/O Models ..............................................778.1 Input/Output Buffer Information Specication ................ 77 8.2 Behavioral Diagram of IBIS ................................................ 78 8.3 3-State Output Model ........................................................... 78 8.4 Creating IBIS Models ........................................................... 79 8.5 Scattering Parameters (S Parameters) ............................. 80 8.6 SPICE Models ........................................................................ 82

WEBENCH Online Simulation .......................................839.1 Tool Introduction ................................................................... 83 9.2 Designing Interconnects and Selecting Interfaces ....... 83 9.3 Using the WEBENCH Online Tool ...................................... 83 Interface Product Finder ................................................ 83 Create a Design ............................................................... 85 Select Test Pattern, Data Rate, Media, and Signal Conditioning ................................................ 85 Results ............................................................................... 86 Interpreting the Results ................