NAND Flash:Where we are, where are

we going?

Pranav Kalavade

Intel Corporation

Outline

• Introduction

• 3D NAND

• Floating Gate 3D NAND Technology

• CMOS Under Array

• Cell Characteristics

• Summary

NAND Scaling Trend

2D NAND scaling has slowed down

1E-4

1E-3

1E-2

1E-1

1E+0

'00 '05 '10 '15 '20

Cell S

ize [

um

2]

Year

2D NAND Cell Size Scaling

70nm

25nm

20nm

2D NAND Scaling Limiters

• Lithography Limitations

• Small Cell Area Effects: Number Fluctuation

• Proximity Effects: Cell to Cell interference

• High Electric Field Effects

0.0

0.5

1.0

1.5

2.0

5 15 25 35

Vt

dis

trib

uti

on

w

idth

[a

.u.]

Cell feature size [nm]Vt

Ce

lls

Vt distribution width

Outline

• Introduction

• 3D NAND

• Floating Gate 3D NAND Technology

• CMOS Under Array

• Cell Characteristics

• Summary

3D NAND - Scaling Through Stacking

Vertical String vs. Horizontal String

• Vertical string more attractive electrically

• Horizontal string more attractive for cell size

Vertical channel

3D NAND

Horizontal channel

3D NAND

3D NAND Advantage

• Eliminates lithography constraint

• Larger cell size and cell to cell spacing

Less parasitic effects and tighter threshold

voltage distributions

Vt

Cells ~1X nm 2D NAND

3D NAND

3D NAND – Floating Gate vs Charge Trap

• Floating Gate – Good Program/Erase Vt

window and Charge isolation between cells

• Charge Trap – Charge dispersion between

cells & Need for Metal Gate process

Floating Gate 3D NAND Charge Trap 3D NAND

Discrete Charge

Storage Node

Continuous

Charge Storage

Node

Outline

• Introduction

• 3D NAND

• Floating Gate 3D NAND Technology

• CMOS Under Array

• Cell Characteristics

• Summary

3D FG NAND Cell Formation

(b) Cell hole etch

(c) Recess Formation

(d) IPD formation

(e) FG deposition

(f) FG isolation

(g) Tunnel-oxide and

channel formation

(h) WL Step formation for

contacting

(a) Tier deposition

3D FG NAND Technology

CMOS Circuits

Contact/Bitline

Wordlines (32 Active)

SGD

SGS

Metal Layer

Source

Outline

• Introduction

• 3D NAND

• Floating Gate 3D NAND Technology

• CMOS Under Array

• Cell Characteristics

• Summary

CMOS Under Array

• 3D NAND String is formed

fully above the silicon.

• Enables silicon area under

for CMOS circuitry

– 2 Metal Layers below array

for CMOS connections

– 2 Metal layers above the

array for Bitline and

Bussing

Outline

• Introduction

• 3D NAND

• Floating Gate 3D NAND Technology

• CMOS Under Array

• Cell Characteristics

• Summary

Key Cell Characteristics

• Cell Id-Vg Characteristics

• Erase Operation

• Program/Erase Vt

• Program Disturb

• Cell Vt distributions

• Cell to Cell Interference

Cell Id-Vg Characteristics

• Surround gate structure of 3D NAND

provides for good gate control

• 3D NAND String on-current matches that

of 2D NAND

1E-12

1E-10

1E-08

1E-06

0 1 2 3 4 5

Curr

ent

[A]

WL Voltage [V]

Vds = 0.5V

0.0

0.4

0.8

1.2

0 1 2 3 4 5

Curr

ent [

Norm

]

WL Voltage [V]

3D NAND

20nm 2D NAND

Erase Operation

Erase bias applied to the Source

Body biased up by the SGS GIDL

Wo

rdli

nes

N+ Source

SGS1E-14

1E-12

1E-10

1E-08

-6 -4 -2 0GID

L C

urr

en

t [A

]

Vgs [V]Vs

Vg

VWL

Vs =0V

Vbl = -2V

Program/Erase Characteristics

>10V Cell Program/Erase Vt Window is

achieved

-8

-6

-4

-2

0

2

4

6

0 2 4 6 8

Cell

Vt

[V]

Program/Erase Voltage Delta [V]

Program

Erase >10V P/E

Window

Program Disturb

>10V Disturb

Window

Achieved -2.0

-1.5

-1.0

-0.5

0.0

10 20 30

Cell

Vt

[V]

Gate Voltage [V]

Sel Cell

Inh Cell

>10V

Larger physical

cell size of 3D

NAND improves

Vt distributions

90nm70nm

50nm34nm

25nm

20nm

3D NAND

1

4

16

64

# o

f E

lec/1

00m

V D

Vt

Technology Node

0

20

40

60

80

100

120

Natural VtDistribution

Numberfluctuation

Arb

itra

ry U

nit

s 2D 20nm

3D

90nm70nm

50nm

34nm

25nm20nm

3D

1E+2

1E+3

1E+4

# C

ha

nn

el A

rea

Technology Node

Vt Distributions

Cell to Cell Interference

Better shielding from

the control gate in the

3D NAND reduces

interference by ~80%

3D NAND

e e

eee

e

e

e

e

e

2D NAND

e e e e

0.0

0.2

0.4

0.6

0.8

1.0

1 2

Net Interference (A.U.)

2D 20nm 3D

MLC Vt Distribution Width

• Better intrinsic distribution and lower

interference leads to an overall

tighter Vt distribution for 3D NAND

0.0

0.5

1.0

1.5

2.0

5 15 25 35

Vt

dis

trib

uti

on

w

idth

[a

.u.]

Eff Cell feature size [nm]

2D 20nm3D

Vt Distribution [A.U.]

Nu

mb

er

of

Cells

0.5X3D NAND

Outline

• Introduction

• 3D NAND

• Floating Gate 3D NAND Technology

• Cell Characteristics

• CMOS Under Array

• Summary

SLC MLC TLC QLC?MLC: 4 Levels => 2 bit/cellSLC: 2 Levels => 1 bit/cell

Vt

1 0

RD

PVEV0 Vpass_R

Vt

11 1001 00

R1 R2 R3

EV PV1 PV2 PV3

0

Vt

R1

EV PV1Vpass_R

PV2 PV3 PV4 PV5 PV6 PV7

R2 R3 R4 R5 R6 R7

TLC: 8 Levels => 3 bit/cell

Vt

R1

EVVpass_

PV1PV2PV3PV4PV5PV6PV7

R4R5 R6 R7

QLC: 16 Levels => 4 bit/cell

PV1PV2PV3PV4PV5PV6PV7PV7

Outline

• Introduction

• 3D NAND

• Floating Gate 3D NAND Technology

• Cell Characteristics

• CMOS Under Array

• Summary

Summary

• 3D NAND extends NAND scaling with cell

characteristics superior to that of scaled

2D NAND

• More bits / cell accelerates the scaling:

facilitated by superior characteristics of

3D NAND