When the RF test system and the de-vice-under-test (DUT) both havecoaxial connectors, hooking them

together to make a measurement is easy.However, as radio-frequency integrated cir-cuits (RFIC) have shrunk in size, traditionalcoaxial connectors are no longer useful. Withthe multitude of RF component sizes and

shapes found on themarket, no single con-nector type fits themall. A test fixture isneeded to act as anelectrical and mechan-ical interface from theRF test system to theDUT.

RFICs are com-monly marketed not asdie but as packagedcomponents. Although

an essential part of the component, the pack-age is easily overlooked, usually an after-thought to designing the die. A high perfor-mance die in an inferior package results in amediocre performing component.

An RF package can be characterized eitherempty or with a die inside. Many packages

cannot be directly probed, in which case a testfixture provides the solution. Test fixtures areless expensive than wafer probe stations andoffer more flexibility to the RF port location.With a test fixture, the matching and bias cir-cuitry can be located near the DUT. Yet testfixtures add parasitics to the characterizationscheme such as ground loops and RF reflec-tions at the interfaces. Since the calibrationplane is not usually at the package’s pads, ac-curate de-embedding becomes essential. Thisarticle covers RF package characterizationprinciples using test fixtures, and will help thereader to understand the package’s effect onthe die, especially parasitic inductances (self,mutual and ground) and capacitances (bothself and mutual).

THE BASIC TEST FIXTUREAn RF test fixture has three basic compo-

nents — the RF launcher (usually a coaxialconnector), RF interconnecting lines leadingto the DUT (usually microstrip) and a block

RF TEST FIXTURE BASICS

TUTORIAL

SCOTT WARTENBERGRF Micro DevicesGreensboro, NC

This article covers RF package

characterization principles

using test fixtures, and will

help the reader to understand

the package’s effect on the

die…

housing for the test fixture’s body.Figure 1 shows a test fixture de-signed for evaluating leaded pack-ages. Also known as a split block fix-ture, it consists of separate end sec-tions (A-C and C-A) and amid-section (C-C). Each end sectionholds an RF launcher and an inter-connecting RF line. The intercon-necting lines can take any number offorms (microstrip, stripline, CPW,etc.). The width of the mid-section issized to fit the DUT.

Each section of the test fixture canbe individually characterized by its S-parameters and then cascaded for thecomplete in-fixture response. To dothis, the S matrices are converted to ABCD matrices and multiplied ina chain fashion.1 Discontinuities atthe interfaces must be consideredsince they generate reflections. Forinstance, a coaxial center pin, makingpressure contact to the microstripline at B, is prone to wear and bend-ing. After extended use, its contactdegrades, causing larger reflectionsfrom B. Also, any gap between thecoaxial launcher and the fixture blockat B results in a discontinuity.

Mechanically, the most useful testfixtures are designed using a modularapproach. The fixture blocks hold theRF launchers and a replaceable mid-section which holds the DUT. Thelaunchers and the blocks arereusable, while the mid-section iscustomized to fit the DUT. Thelaunchers have alignment pins orbolts that run the length of the block’s

body. Either spring-loaded end sec-tions or tightening the bolt securesthe three sections together.

To calibrate the fixture to the Creference planes, the mid-sectionshould be replaced with calibrationstandards, preferably using short-open-load-thru (SOLT) below 5 GHzand thru-reflect-line (TRL) above.The parasitics in SOLT standards aredifficult to quantify above 5 GHz.The benefit of TRL is that it relies onthe characteristic impedance of theline to overcome reflections at thetransitions. Because TRL uses differ-ent line lengths, the width of themid-section (C-C) must be adjustableor the mid-section replaceable. Overtime, repeated use eventually wearsout the calibration standards and thelaunchers. RF repeatability of thelaunchers will affect the quality of themeasurement, particularly at higherfrequencies.2

QUALITIES OF A GOOD TEST FIXTURE

The qualities of a good test fixtureinclude mechanical durability, good RFperformance, low cost and ease of use.Calibration should be fast and accurate.An ideal fixture would have no loss, aflat frequency response, a linear phaseresponse, no impedance mismatches, awell-known electrical length, total isola-tion between ports and be free of exter-nal parasitics.3 Under such ideal condi-tions, calibration would not be neces-sary. Most test fixtures offer trade-offsbetween these features.

In reality,mounting the DUTinto a test fixtureclouds the DUT’sresponse, requiringde-embedding ofthe fixture’s effects.Users often com-pensate for the testfixture through sim-ple means such ascalibrating to theends of the coaxialtest cables, sub-tracting a few tenthsof a decibel (dB)from the measure-ment, or altogetherignoring the fix-ture’s effects.

Adhering to afew guiding princi-

ples can improve the results. In gen-eral, the RF performance of the testfixture should exceed that of theDUT. For instance, the test fixture’sinsertion loss should be less than theuncertainty found in the DUT’s inser-tion loss (or gain). All along the RFpath, impedance discontinuities atthe fixture transitions should be mini-mized. The bandwidth of the fixtureshould be wider than that of theDUT. Wideband measurements areuseful for studying harmonics, for in-stance. In order to test sensitive de-vices such as filters and low noise am-plifiers, the fixture’s port-to-port iso-lation should be high.

CHARACTERIZING THEFIXTURE’S PARASITIC EFFECTS

To characterize the test fixture,three approaches are available: createa circuit model of the combined fix-ture and DUT; create a circuit modelof the fixture alone; or de-embed thefixture from the measurement toyield the DUT. The first method re-quires the DUT to be inserted duringcharacterization. The measurementsare used to create RF models of thefixture and the DUT, generating bothmodels at the same time.4 Since thereference plane between the fixtureand DUT is undefined, this approachcan give misleading results. Smallparasitics near the DUT-to-fixture in-terface can often be attributed to ei-ther the DUT or the fixture side ofthe reference plane, a source of un-certainty. The solution is to developan electrical model of the fixture only,using it to de-embed the fixture fromthe DUT measurement. Accuracy ofthe final DUT data will depend onhow well the model actually matchesthe fixture. The third method is tocalibrate out the fixture. Mountingcalibration standards in place of theDUT shifts the electrical referenceplane to the DUT contacts, de-em-bedding the fixture’s parasitic effects.

TYPES OF FIXTURES — R&D OR MANUFACTURING

The manufacturing and research& development (R&D) environmentscall for different types of test fixtures.Manufacturing demands highthroughput, quick insertion, align-ment and securing. Rugged, compli-ant contacts are made to withstandthousands of insertions and removals.

TUTORIAL

OUTPUTLAUNCHER

OUTPUTMICROSTRIPDUT

[S]IC [S]IM [S]DUT [S]OM [S]OC

INPUTLAUNCHER

INPUTMICROSTRIP

A B C C B A

Fig. 1 A simple test fixture.

The contact area (or contactor) mustbe kept clean for repeated insertionsand extractions. For automated load-ing and unloading, the manufacturingtest fixture tends to be mechanicallycomplicated, providing fast, repeat-able connections with acceptable RFperformance and long fixture life-times.

Conversely, R&D fixtures are un-sophisticated and somewhat fragilesince only a handful of devices aretested. They can be as simple as aPCB with soldered RF connectors toeither end. In R&D testing, the qual-ity of the measurement and definitionof the reference planes are of utmostimportance. Correlation and repeata-bility between manufacturing andR&D test fixtures is often a problem.

FIXTURING FOR PASSIVE COMPONENTS

Passive devices tend to exhibitsome loss, so the test fixture’s lossmust not degrade the sensitivity ofthe measurement. Unlike active com-ponents, passive components have nogain to overcome fixture losses. Agood example of the fixture’s impacton a passive component measure-ment is measuring a filter. The testfixture’s parasitics can affect the fil-ter’s poles and zeroes, shifting its fre-quency band response. Excessive ca-pacitance or inductance in the fixtureeasily degrades the filter’s bandedges, or skirts. For high reject fil-ters, where only a small amount ofsignal passes through, port-to-portmeasurements can be corrupted byfixture leakage.

To reject out-of-band frequencies,the filter presents a highly reflectiveload to the test fixture port. Ratherthan RF tuning the fixture’s port tomatch the filter’s impedance to 50 Ω,attenuators (or pads) could be placedin the RF path. These should bemounted close to the DUT so that re-flected signals are attenuated as soonas they reflect off the filter. Placingattenuators in-line will decrease thedynamic range of the measurement.

FIXTURING FOR ACTIVE COMPONENTS

Designing the best fixture to testan active component depends on theRF application. For instance, an am-plifier can easily overcome a test fix-ture’s loss by adding a few decibels of

frequency resistance more pre-dictable than with high frequencycoaxial resistors. The S-parameters oflumped elements tend to varysmoothly with frequency. When ashort approaches a wavelength long,it radiates. In-fixture standards cancouple to nearby metal in the fixture.Coupling and radiation are non-sys-tematic errors difficult to de-embed.

Developing in-fixture standardscan be the most difficult part of build-ing a test fixture. They are custom-de-signed and usually require many itera-tions to build precisely. When design-ing calibration standards, theproperties to focus on are attenuation,characteristic impedance and para-sitics (inductances and capacitances).Calibration standards should be stableover temperature and mechanicallyrepeatable. Most importantly, theirresponse should not change each timethey are inserted.

Some general guidelines can easethe design of in-fixture standards.Common substrate materials tochoose from are alumina, sapphire,silicon or GaAs. The material’s dielec-tric properties will impact the behav-ior of the standard (for instance, thedelay of the thru). At frequencies > 2GHz, silicon substrates exhibit higherloss and parasitic capacitance thanthe other materials.

Employing a photolithographic,thin-film fabrication process yieldswell-defined standards. When preci-sion is not critical, a thick-film fabri-cation is less expensive. After fabrica-tion, there must be a means of verify-ing the standards other than the testfixture. When the standards areSOLT, a TRL-calibrated fixture canbe tried to independently character-ize them. A good load will have con-stant low SWR magnitude and a lin-ear, broadband phase response.When creating 50 Ω CPW load stan-dards, two 100 Ω resistors in parallelshould always be chosen over one 50 Ω. This approach cuts the parasiticpad inductance in half.

RF TRANSITIONSRF transitions are key parts of the

test fixture, converting the RF signalfrom one medium (coaxial, mi-crostrip, coplanar waveguide, etc.) toanother. RF transitions perform twotasks. First, an impedance transfor-mation takes place from one charac-

TUTORIALgain to its RF output. However, de-pending on the power level, highpower components can generate a lotof heat. Heat can be dissipated eitherby providing cooling to the fixture orby pulsing the bias so that only a littleheat is generated. Pulsing at a lowduty cycle means the device is biasedonly for a short period of time, allow-ing it to cool. When measuring fornoise figure or small capacitances (onthe order of femtofarads), the DUTshould be shielded from any strayfields which can impinge upon it.Such sensitive DUTs are low noiseamplifiers (LNA), Schottky diodesand a transistor’s junction capaci-tance.

Fixture mismatches to the DUTcontinue to exist even after calibra-tion. The mismatches are mathemati-cally de-embedded from the mea-surement, not physically removed.After calibration, they will continueto interact with the DUT, especiallywith reflective DUTs such as filters,LNAs and power amplifiers (PA).Embedding impedance-matchingnetworks in the fixture can lessen re-flections from highly mismatchedloads. Active devices such as poweramplifiers have a low output port im-pedance. Similarly, some diodes ex-hibit a negative resistance. To ensurestability, the loss of the fixture itselfshould be small but slightly higherthan the DUT.

CALIBRATION STANDARDS —COAXIAL VS. IN-FIXTURE

As discussed earlier, calibratingthe test fixture to the DUT’s pads re-quires in-fixture calibration stan-dards. To appreciate the difficulties, acomparison of how in-fixture stan-dards are physically and electricallydifferent from coaxial standards isuseful.

Coaxial standards are surroundedby ground, serving to shield the cen-ter pin. Conversely, in-fixture stan-dards are usually on a substratemounted in place of the DUT. Sub-strate elements are electrically small,which means they can be approximat-ed as lumped elements, simplifyingtheir characterization. At high fre-quency, arriving at their parasitic val-ues is simpler than with larger coaxialstandards. Substrate resistors tend tobe thin-film and less than a skin-depth thick. This makes their high

teristic impedance Z0 to another. Sec-ond, it transforms the electromagnet-ic fields from one transmission modeto another. Carefully designing forthese two criteria assures a successfultransition.

When a transition is not smooth,reflections and loss appear, caused bysudden changes either in impedanceor in the line’s geometry. Both disturbthe electromagnetic field pattern.When designed carefully, a transitionwill not induce reflections. For exam-ple, transformers are a simple way toadapt from one resistance to another.Using a 3:2 transformer converts a re-sistance from 75 to 50 Ω. Unfortu-nately, impedance transformations in-volve both resistance and reactance,not a simple task due to parasitic in-ductances and capacitances at higherfrequencies. When conceptually de-signing transitions, the changing na-ture of the fields must be kept inmind as they transform from onemedium to another. The input andoutput impedances define the endgoals.

DE-EMBEDDING THE FIXTUREFROM THE MEASUREMENT

A number of schemes are availableto de-embed the fixture’s effects fromthe measurement, namely, de-em-bedding the microstrip lines on thePCB. These lines can be de-embed-ded in one of the following ways:• Linear Phase Compensation:Adding a phase delay can compensatefor the phase due to a length of trans-mission line. This technique assumesthat the phase is linear and that theline is lossless. • Normalization: A short and a thrucan be used to normalize an in-fixturemeasurement, as shown in Figure 2.To find the return loss of the DUT(S11,DUT), the return loss measure-ment (S11M) is normalized by insert-ing a short in place of the DUT. Theshort (whose S11 = –1) gives the re-flection tracking error ERF

Note that a reflection normaliza-tion does not correct for directivity

S ES E

E S

EE

EE

ShortDF

DUT RF

SF DUT

DFRF

SFRF

1111

111

1

1 11

= +( )( )

( )( ) =

+( )( )

( )( ) ≅

,

,–

–

– –– ( )

would be too complicated.5 All com-binations of pins are characterized,two at a time, using symmetry wher-ever possible.

Before beginning any measure-ments, a necessary and sufficient setof experiments should be outlined toevaluate each circuit path in thepackage. For instance, consider adja-cent pins 1 and 2, as shown in Figure4. The external leads are labeled P1and P2, while the internal wire bondpads are P1' and P2'. The first experi-ment is to make two-port S-parame-ter measurements with the internalpads P1' and P2' unconnected oropen. At low frequency, the capaci-tance terms dominate so that the in-ductive circuit elements can be ig-nored (X). The resistors represent RFleakage through the resin dielectricof the package wall. Because no cur-rent flows, the resistors can be ne-glected also. For the next experiment,P1' and P2' are shorted internallywith a bond wire of inductance Lbwto the ground paddle. Because the in-ductances are a larger part of the im-

TUTORIAL(EDF) or source mismatch errors(ESF), but instead assumes they arezero. Similarly, replacing the DUTwith a thru gives the transmission er-ror ETF. Transmission normalizationdoes not correct for factors such asthe load mismatch error ELF.• In-fixture Calibration: Calibrationstandards are mounted one-by-one inplace of the DUT and measured.When quality standards are available,this is the best choice.• Thru Line: The DUT is replacedby a thru line that connects the inputand output lines on the carrier sub-strate. This is commonly used inscalar measurements.• Time Domain Gating: The S-para-meters are transformed from the fre-quency domain to the time domain,then the discontinuity is bounded intime. Transforming back gives the fre-quency response of the discontinuity.

PROCEDURE FORCHARACTERIZING A PACKAGE

Consider a package with eightleads, as shown in Figure 3. Six ofthem are routed through the packagewalls to bond pads inside, while theother two go to a ground paddle inthe package’s center. For the sake ofclarity, the internal routing throughthe package walls is not shown. Thetask is to generate a high frequencyequivalent-circuit model of the pack-age.

An equivalent circuit should be firstsketched, looking at the package’sphysical construction. Based on howthe leads run through the package andits dielectric layers, the circuit mayconsist of resistances, capacitances(both self and mutu-al) and inductances(both self and mutu-al). Rough values forthe elements of theequivalent circuitshould be estimated.

Next, the RF testports are connectedto the package. Thepackage shown hassix RF ports, but avector network ana-lyzer (VNA) hasonly two ports.Even if more testports were avail-able, modeling allthe pins at once

REFLECTION TRANSMISSION

THRUSHORT

S11M

S11M S21MERF

ERF

ETF

ETF

a0

a0

b0

b3S11,DUT

S11,DUT

S11,DUT = S11M

ERF

S21,DUT

S21,DUT

S21,DUT = S21M

ETF

Fig. 2 Normalizing the reflection andtransmission measurements.

PACKAGE LEADS

GROUNDPADDLE

DIEGND

GNDCARRIERBOARDPADS

PIN 1

PIN 2

PIN 3

PIN 6

PIN 5

PIN 4

Fig. 3 A common eight-pin package.

pedance at high frequency, the capac-itors can be neglected. To isolate andidentify the coupling between pins 1and 2, two experiments are using athru and, for a one-port S-parametermeasurement, a grounded thru. Theground paddle is represented as asimple inductance Lg and capacitanceCg. Higher modeling precision mayrequire a more complicated equiva-lent circuit. In all experiments, a cir-cuit simulator helps to fit the mea-sured data to the model’s equivalentcircuit values.

Creating a lumped-element equiva-lent circuit of the package such as theone shown is valid as long as the one-way RF path length through the pack-age is less than a tenth of a wavelength(λ/10). One way to determine the pathlength is by measuring the phase of theport’s return loss. If the phase of the re-turn loss (S11 or S22) is greater than0.4π radians (where 0.4π = 2 (for roundtrip) •2π (for a wavelength)/10), thenthe path length is greater than λ/10 anda more complicated equivalent-circuitmodel is needed.6

MODELING A PACKAGEMOUNTED TO A CARRIER

The design of the carrier (its lay-out, board thickness, dielectric, etc.)

undoubtedly affects the RF behaviorof the package. Before discussinghow to de-embed the carrier’s effect,a few fundamental questions shouldbe asked. Since any package must bemounted to a carrier board to use it,should not the carrier and package bemodeled together? Or should a pack-age model be developed separately,independent of the carrier style?While modeling the package sepa-rately may seem more desirable, itsRF behavior will always depend onthe nature of the carrier. The layoutof the carrier substrate will differfrom one application to another, somodeling the package as though itwere floating in free space is not onlyunrealistic, it can give misleading re-sults when attached to one carrier de-sign or another. Excluding the effectof the carrier and the bonding mater-ial (either a conductive adhesive orsolder) makes the package modelmore universal but makes derivingsuch a model and applying it to a de-sign more difficult.

GROUND INDUCTANCEEstablishing a dependable RF

ground path to the die inside thepackage is crucial. Regular insertionand removal of the DUT into a testfixture can make repeatable groundingperformance difficult. For proper cur-rent conduction, the test circuit (die,package, carrier, test fixture and testsystem) should form a common-modecurrent loop (as shown in Figure 5).With a single ground, the signal cur-rent Isig and ground current Ignd areequal and flow in opposite directions.The magnetic fields (dotted lines) willcancel and the electric fields (solidlines) will terminate properly.

A single ground path is rarely ob-tained. Instead multiple groundpoints occur in the circuit. This givesrise to differential mode currents, asshown in Figure 6. Multiple groundscan cause the ground current Ignd toflow in the same direction as the sig-nal current Isig at some points, leadingto mutual coupling M and radiation.

Multiple ground paths set upground currents traveling in differentdirections. Their effect shows up inthe measurement as high frequencyresonances and generally highercrosstalk. In particular, ground dis-continuity effects will disturb sensi-tive RF devices such as low noise am-

TUTORIAL

P1

P2

P1'

P2'

P1

P2

P1

P2

P1'

P2'

P1

P2

P1'

P2'

P1'

P2'Cg

Lg

Lbw

LbwLbw

Lbw

LOW FREQUENCY OPEN SHORT

GROUNDED THRUTHRU

Fig. 4 Circuit configurations used to model adjacent leads in a package.

SIGNAL TRACE

LOOP

Isig

GROUND PLANE

SIGNAL TRACE

GROUND PLANE

ZSZ

ZL

Ignd

Fig. 5 Common-mode current flow.

SIGNAL TRACE

LOOPM

Isig

GROUND PLANE

SIGNAL TRACE

GROUND PLANE

ZS

ZL

Ignd

Fig. 6 Differential mode current flow.

plifiers and filters. The ground planeimage current runs along the side ofthe conductor plating facing the sub-strate. The plating conforms to thecontours on the surface of the sub-strate. This is why, at millimeter-wavefrequencies, the substrate’s surfaceroughness increasingly becomes afactor in the insertion loss.

GROUND PADDLEInside the package, the die is usu-

ally attached to a ground paddle.Similarly, the carrier often has agrounded area reserved for the pack-age with plated-thru holes or filledvias to ground. When the bondingmaterial penetrates into plated-thruholes, the via’s inductance willchange. On the other hand, gold-plat-ed filled vias have conductive epoxyalready filled in. Yet the epoxy fillerhas a dielectric constant differentfrom the substrate. The frequency ofoperation and resulting skin depthdetermines the depth of penetrationof the RF current into the filler, af-fecting its loss.

One way to measure the groundpaddle’s inductance is by inserting acoaxial SMA connector through thecarrier and package.7 By boring ahole through the carrier and packagelarge enough to accept a SMA centerpin, it can be soldered to the groundpaddle inside, as shown in Figure 7.The connector’s housing is solderedto the ground plane on back of thecarrier. A simple equivalent circuitfor the ground paddle is a parallel LCcircuit to ground. Measuring the one-port S-parameter S11 at low frequen-cies, the ground inductance Lg andcapacitance Cg of the paddle are

L ZS

f Sg ≈

+ ∠( )∠( )0

11

11

1

22

sec

tan( )

π

where

fr = measured resonant frequency ofthe parallel LgCg

Z0 = characteristic impedance(usually 50 Ω)

The fixture’s ground plane shouldclosely couple to the signal path. Toensure ground integrity, map theground path through the fixture as ittravels in parallel with the signal path.The signal and ground paths shouldclosely couple as the RF travels fromthe input launcher through the DUTto the output launcher. The groundpath should be continuous, permit-ting image currents to flow unimped-ed through the carrier, package anddie. Indirect ground paths are whatlead to ground inductance and para-sitic coupling.

CONCLUSIONTest fixtures are often perceived as

a headache, usually built as an after-thought in the design process. To de-liver high performance, the RF prod-ucts must be qualified using a reliabletest fixture.

The size, weight and cost of RFproducts are driving the need forsmaller and more integrated pack-aged components. As the markettrend progresses towards smallerpackage sizes (< 4 mm2) and closerpad spacing (< 0.5 mm), packagecharacterization will become evenmore difficult. At the same time, thedrive towards lower cost makes fastand accurate package characteriza-tion essential to a design’s first-passsuccess. Shorter product design cy-cles mean that the time to design and

C Zf L

gr g

≈ 0 2 2

1

43( )

π

TUTORIALPACKAGE MOLDING

GROUND PADDLE

GROUNDPLANE

BONDWIRE

VIASMA

COAXIALCONNECTOR

Fig. 7 Measuring the RF characteristics of the ground paddle using a coaxial connector.

build test fixtures is getting shorter.These trends will not make the job ofthe test fixture designer any easier.

As the industry moves towardhigher levels of component integra-tion, the package will become morecomplex and require a greater num-ber of tests. Multiple die in the samepackage will mean that interactionbetween die will go beyond the sim-ple mutual inductance and capaci-tance occurring between bond wiresand leads in a package.8

References1. R. Partha, “Use Matrix Models to Make

Analysis Easy for Microstrip Matching Cir-cuits,” RF Design, Vol. 20, No. 9, Septem-ber 1996, pp. 50–62.

2. R. Bauer and P. Penfield, “De-embeddingand Unterminating,” IEEE Transactions onMicrowave Theory and Techniques, Vol.22, No. 3, March 1974, pp. 282–288.

3. Agilent Application Note AN 1287-9, “In-fixture Measurements Using Vector Net-work Analyzers,” 1999.

4. D. Williams, “De-embedding and Unter-minating Microwave Fixtures and Nonlin-ear Least Squares,” IEEE Transactions onMicrowave Theory and Techniques, Vol.38, No. 6, June 1990, pp. 787–791.

5 A. Ferrero, F. Sanpetro and U. Pisani,“Multiport Vector Network Analyzer Cali-bration: A General Formulation,” IEEETransactions on Microwave Theory andTechniques, Vol. 42, No. 12, December1994, pp. 2455–2461.

6. C.T. Tsai and W.Y. Yip, “An ExperimentalTechnique for Full Package InductanceMatrix Characterization,” IEEE Transac-tions on Components, Packaging and Man-ufacturing Technology — Part B, Vol. 19,No. 2, February 1996, pp. 338–343.

7. T. Horng, S. Wu and C. Shih, “ElectricalModeling of RFIC Packages Up to 12GHz,” IEEE Electronic Components andTechnology Conference, 1999, pp. 867–872.

8. R. Gharpurey and R. Meyer, “Modelingand Analysis of Substrate Coupling in Inte-grated Circuits,” IEEE Journal of Solid-State Circuits, Vol. 31, No. 3, March 1996,pp. 344–353.

Scott Wartenberg is astaff engineer at RFMicro Devices inGreensboro, NC. Hehas doneRF/microwave workfor AgilentTechnologies,Westinghouse,Raytheon and the USDepartment of Defense.He earned his BS

degree in electrical engineering from theUniversity of Tennessee, and his MS and PhDdegrees in electrical engineering from the JohnsHopkins University. He is the author of RFMeasurements of Die and Packages (ArtechHouse Inc., Norwood, MA 2002).