Chiplets and Heterogeneous Packaging Are Changing System ...
Multiphysics Simulation for Chiplets…Eco System for 2.5D/3D IC Power, Signal and Thermal Integrity...
Transcript of Multiphysics Simulation for Chiplets…Eco System for 2.5D/3D IC Power, Signal and Thermal Integrity...
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Multiphysics Simulation for Chiplets
Chris OrtizPrinciple Application EngineerANSYS, Semiconductors
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Need for Chip Aware System Simulations
Thermal Fatigue & StressVoltage Drop, Power Loss
Target Impedance
Thermal IntegrityPower IntegritySignal Integrity
EMI/EMCESD
Jitter?
Conducted EMIElectro Static Discharge
Physical Integrity Challenges
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Wafer Scale Engine (WSE)
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• CS-1 being used at Argonne national Laboratory
• 15-20 kW
• 1.2 trillion transistors
Image from cerebras.net
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Advanced Multi-Die PackagingANSYS Solutions certified for latest packaging technologies
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ANSYS and SAMSUNG partners for 3DIC design
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eSilicon Uses ANSYS Multiphysics SimulationsAchieve Silicon to System Success
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HBM2 Stack
Package Substrate
Memory
Interfa
ce
Memory
Inte
rface
I/O Interface
Memory
HBM2 PHY
2.5D interposer & advanced packaging
Power-optimized memories inc’lTCAMs & unique network-
optimized memories
Power-optimized 56G & 112G SerDes
Example of a hyperscale data center ASIC
“With design costs in the tens of millions of dollars and re-spins resulting in schedule delays and missed market opportunities, eSilicon relies on ANSYS’ chip-package-system(CPS) modeling and simulation software.”
Teddy Lee, Architect SI/PI, eSilicon Corporation, San Jose, USA2019 ANSYS ADVANTAGE Find interview on “ANSYS, inc.” youtube page.
eSilicon’s highly configurable FinFET-class IP platform includes application-optimized processor core and a number of high-bandwidth memory(HBM) stacks integrated on a silicon interposer, built into a complex 2.5D package
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Eco System for 2.5D/3D IC Power, Signal and Thermal Integrity
1. Modeling connectivity of complicated 3DIC structure
2. Parasitic modeling of packages (Interposer, FOWLP), board PCB
3. Power, signal and thermal modeling of interconnects of stacked dies
4. Noise source modeling for power, signal and thermal
5. Interface (Bump, Ball and TSV) modeling
Wendem Beyene, “Power Delivery Network Design and Optimization for High-Speed Systems with Si Interposer”, DesignCon 2017
Need for accurate and easy set up for chip, package and board co-simulation
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Parasitic Extraction
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Package Routing
• Irregular package geometries• Special handling for accurate parasitic extraction
Interconnects
• Complex interconnect geometries• Need to consider interaction between package and die metal layers
planes • Larger planar supply routing• Larger dimensions• Need for field solver and/or hybrid solutions
Slotted ground/power
Signal channel
• Finer ( < 1um) and longer line (> mm)• Slotted ground network• Special handling for accurate parasitic extraction
FOWLP
Interposer
pkg/pcb
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Multi Die System PDN Coverage Current Model Generation in ANSYS CMA
1 MHz 10 MHz0 MHz 100 MHz 1 GHz 10 GHz100KHz
Current Noise vs. CPM Types
Time extension up to msVarious di/dt for low/mid.
frequencyConventional CPM
CPM of multiple Dies from RedHawk/Totem
Time extension up to msVarious di/dt for low/mid.
frequencyConventional CPM
Full PDN Coverage Current Model from ANSYS CMA
Merge Traditional CPM and modulated Current
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IC
PCBPackages
loop
Converged
Power Map
System
Thermal BC
2-WaysLink
CPS – Thermal IntegrityPower-Thermal Analysis
Chip-Package-System information feed small to large
Chip-Package-System information feed large to small
IC
IC
Constant
Power
Uncertain
Power
Interposer
Converged
Power Map
System
Thermal BC
2-WaysLink
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CDX work
• Provide chiplet and p-chiplet integrators with relevant information required for power and thermal modeling.
• Information will allow for analysis at early and late stages of design
• Precision of results will be controlled by data utilized. Early analysis being less precise that final.
• Enable means for dealing with missing or un-available data for given (p)chiplet
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Input Data for Power and Thermal Analysis
• Zeff format used to store chiplet information‐ Thermal resistance‐ Power information‐ Large number of entries will be used to make estimates for parts with missing data‐ Precision of results affected by variation in input data
• Interposer/pcb layout and placement information‐ Material properties both electric and thermal‐ Block information can be used for thermal‐ Layout information required for power integrity
• Thermal boundary conditions‐ Fan placement‐ HTC (Heat Transfer Coefficient) boundaries
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Validation
• The proposed specifications for performing thermal and power analysis will be validated on the PoC and results with basic input data vs a full signoff analysis with detailed chip thermal models will be compared along with precision of results
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Thank You