ABSTRACT In this paper, a multi-level wordline driver scheme is presented to improve SRAM read and write stability while lowering power consumption during hold operation. The proposed circuit applies a shaped wordline voltage pulse during read mode and a boosted wordline pulse during write mode. During read, the applied shaped pulse is tuned at nominal voltage for short period of time, whereas for the remaining access time, the wordline voltage is reduced to a lower level. This pulse results in improved read noise margin without any degradation in access time which is explained by examining the dynamic and nonlinear behavior of the SRAM cell. Furthermore, during hold mode, the wordline voltage starts from a negative value and reaches zero voltage, resulting in a lower leakage current compared to conventional SRAM. Our simulations using TSMC 65nm process show that the proposed wordline driver results in 2X improvement in static read noise margin while the write margin is improved by 3X. In addition, the total leakage of the proposed SRAM is reduced by 10% while the total power is improved by 12% in the worst case scenario of a single SRAM cell. The total area penalty is 10% for a 128Kb standard SRAM array.

I.INTRODUCTION Aggressive transistor scaling leads to increased process

variations, such as fluctuations in width, length and oxide thickness of the transistors [1, 2], as well as fluctuations in the number and position of dopants in the channel region (RDF) [3]. Such variability effects results in various parametric failures in the SRAM array such as read, write, hold and access failures [3]. To mitigate such failures and ensure stable SRAM function various techniques have been proposed that include device sizing, supply and threshold voltage selection, SRAM column height, sense-amplifier optimization as well as redundant columns and error correction techniques. However, a lot of these techniques come usually at a cost of power and area overhead making challenging the satisfaction of present day strict power and high density memory requirements. Apart from variations, power is also considered as another major challenge in nanometer regime and various techniques have been proposed to tackle it. Among these, supply voltage scaling is considered as one of the most effective methods for dynamic and leakage power reduction [4]. However, scaled voltages and process variations degrade the static noise margin in SRAM arrays significantly, especially during read. To improve read static noise margin (SNM), even under lower supply voltage, different SRAM bit-cell topologies have been proposed (i.e. 8T, and 10T) [5, 6] or techniques based on dynamic wordline voltage adjustment. Such techniques include level-programmable wordline driver (LPWD) [7], a replica access transistor (RAT) [8], negative write biasing [9,10], capacitive coupling [11], and level-programmable wordline driver for single supply (LPWD-SS) [12], which can effectively improve read/write failures. However, such techniques come usually at the cost of high area overhead due to the required resistances and the extra circuitry that is needed to create negative voltages as well as

due to the extra power rings needed to supply a negative voltage during write mode. The technique proposed in [11] improves write margin without read margin degradation, while the proposed technique presented in this paper improves both read and write margins. Adaptive wordline under-drive technique proposed in [13] is another technique to reduce the Vcc,min of SRAM. This technique tracks the changes in SRAM operation at different corners due to transistors’ variations.

In this paper, we propose a design technique for the improvement of memory SNM by applying different voltage levels at the wordline depending on the mode of operation. Specifically, the proposed scheme boosts the wordline voltage to VDD+α where α is a design parameter that depends on transistors’ size and boosting capacitance of the wordline driver circuit. In addition, for a short period of time from the beginning of read operation the proposed scheme applies a fixed voltage equal to VDD while for the rest of the read operation a low voltage equal to around VDD/2 is applied in order to improve the noise margin without degrading access time significantly. Finally, during standby mode a negative wordline voltage is applied which leads to reduced overall leakage current. By adopting such a multi-level scheme of wordline voltages the proposed scheme limits the SRAM failures while reducing the bitline leakage. A worthwhile advantage of the proposed scheme is the merging of read-assist and write-assist circuit designs into one single design and overall shows negligible area overhead compared to other existing techniques such as the RAT [8] and LPWD-SS [12] schemes due to lower required capacitance and no usage of any resistance.

The rest of paper is organized as follows. In section II, we consider an ideal wordline pulse similar to the one generated by the proposed wordline driver and we describe its advantages. Section III, presents the proposed multi-level wordline driver technique (MLWD) and describes the details of circuit that generates the desired pulse. Simulation results of the proposed scheme and the comparison with a conventional wordline driver (CWD) are presented in section IV. Finally, conclusions are drawn in section V.

Multi-Level Wordline Driver for Low Power SRAMs in Nano-Scale CMOS Technology

Farshad Moradi1, 5, Georgios Panagopoulos2, Georgios Karakonstantis3, Dag Wisland1, Hamid Mahmoodi4, Jens Kargaard Madsen5, and Kaushik Roy2

1Nanoelectronics Group, University of Oslo, Oslo, Norway, 2Nanoelectronic Research Lab, Purdue University, USA, 3Swiss Federal Institute of Technology (EPFL), Switzerland, 4NeCRL Group, San Francisco State University, USA,

5Aarhus School of Engineering, Aarhus University, Denmark {famo, jkm}@iha.dk, {kaushik, gpanagop}@purdue.edu, georgios.karakonstantis@epfl.ch,dagwis@ifi.uio.no,mahmoodi@sfsu.edu

Fig. 1: The effects of wordline shaping on SRAM cell stability for read ((a), (b)) and write ((c), (d)).

(a)[V]

(b)

[V]

(c)

[V]

(d)

[V]

978-1-4577-1954-7/11/$26.00 ©2011 IEEE 326

II. MOTIVATION EXAMPLE

As we have already mention, process variations lead to fluctuations in transistor parameters such as threshold voltage, width and length variations that can ultimately lead to memory failures. In general, parametric failures [3] can occur during (a) read: flipping the stored data, (b) write: the data is not stored correctly within the required time and c) hold: flipping of cell data with the application of a lower supply voltage. Figs 1a, b show examples of read and write failures assuming constant wordline (CWL) voltage equal to supply voltage. One method to reduce the effect of variability in these cases is the upsizing of the SRAM cell that helps to make the cell more stable. However, since the area of the SRAM cell is crucial for the density of the memory array, it is important to consider other techniques to improve the stability. A promising technique is to change the shape of the applied wordline voltage. Such technique is preferable since the stability of the cell can be improved without altering the topology or size of each bit-cell. In order to explain the effectiveness of the wordline voltage let us some examples. To begin with let us consider a scenario in which the shape of the applied wordline voltage is not fixed but looks like the one depicted in Fig. 1c. Figs. 1c, d shows the SRAM function during read and write after applying the shaped voltage shown in Fig. 1c. Interestingly, we observe that the application of such a shaped wordline voltage helps the cell to maintain the stored data during read as shown in Fig. 1b. Next let us assume a memory with conventional worldline (Fig. 1b) and a cell that cannot write data correctly due to weakened access transistors influenced by parametric variations. Interestingly, by applying the shaped wordline voltage (boosted to a higher level) depicted in Fig. 1d to the same cell (assumed that fails under a conventional fixed wordline voltage) strengthens the access transistor and allow data to be stored correctly.

The above examples show that appropriate wordline shapes can significantly improve the cell stability and this increase memory yield which is necessary in nanoscale technologies. Motivated by the above examples in this paper we proposed a scheme that generates the appropriate wordline shapes depending on mode of operation and we examined its characteristics and its effects on 128Kb memory array. The details of the proposed circuit are discussed in the next section.

III. PROPOSED WORDLINE DRIVER

In this section we describe the proposed wordline driver in detail and explain how it achieves to improve the read and write SNM, while maintaining a read access time similar to standard SRAM-cell,

and reducing power consumption as opposed to conventional wordline drivers.

The schematic of the proposed wordline driver is shown in Fig. 2. The Multi-Level Wordline Driver circuit (MLWD) consists of three parts: (1) the delay element that determines the duration of a read operation and the time during which WL has a negative voltage level, (2) the pulse generator circuitry that produces a special shaped pulse and (3) the boosting capacitance that changes the voltage level of the MLWD output depending on the operational mode. In order to describe how the MLWD scheme works let us consider its operation at three different modes: (a) hold or standby mode (b) read mode and (c) write mode. a) During hold, the WL is connected to a negative voltage for a

short period of time (~6τinv, where τinv is the delay of a single inverter) and thereafter WL voltage becomes zero. Note that the main reason behind the application of a negative WL voltage level is the reduction of the leakage current. Of course the actual improvement in leakage power consumption depends on various factors such as the transistor size, the boosting capacitance, and the delay of the inverter-chain circuitry as we will show in section IV.

b) During write mode, the MLWD circuit, generates a VDD+α voltage with α>0. Higher WL voltage level (wordline boosting technique) improves the writeability because the gate voltage of the access transistor is higher and hence it becomes stronger (as we also show in one of the examples in section II). Note that α is a design parameter and it is determined by the boosting capacitance while the rise time of WL is tuned by the size of the transmission-gate in the MLWD circuit. Note that, larger transmission-gate transistors (TGT) lead to lower rise time of the MLWD output during write or read modes. Hence, there is no need for dual supply voltages or negative ground (Vss). However boosted wordline suffers from dummy read. However the proposed technique suffers from half-select read during write that can be mitigated by lowering the level of boosted voltage during write.

c) During read mode, for a short period of time from the beginning of the access of the cell (≅6×τinv seconds (70ps-100ps), the MLWD output voltage is raised to VDD±δ where δ is a very small value (≅few mV), that depends on the transistor dimensions of the MLWD circuit, the boosting capacitance, and the load capacitance. For the remaining WL pulse period, the MLWD output is set at a fixed voltage under VDD/2. By applying such a voltage, the read noise margin improves significantly while the read access time is marginally affected. The negligible degradation on read access time is attributed to the primary value of wordline voltage that is VDD±δ, where δ is a value equal to few mV. Thus the degradation in access current is negligible. However, for larger load capacitance the primary level of wordline voltage is lower than VDD leading to reduced access time. Consequently, the drop of the WL pulse width during read, does not affect the read access time significantly.

Next, we explain the operation of the proposed MLWD circuit at different modes during read, write, and hold modes.

During write, when WLin is “1”, for a duration equal to 3×τinv (delay of three inverters), node A remains at “1”, while node B is at ‘0’. In this case, P1, P2 and N1 turn on charging the boosting capacitance to VDD. After this time (~3×τinv), node A becomes zero while node B remains at zero turning off transistor N1. After an elapsed time equal to 6×τinv from the beginning of operation, node B becomes one. Therefore, there is no path between node MLWD and WLin. At this point, capacitance Cboost discharges to ‘0’ after a time constant equal to RN2×Cboost.

Fig.2: MLWD circuit topology.

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For duration equal to 6×τinv from the begincircuit operates similar to write operation. Howetransistors N3 and NR turn on and try to pull downto ground. At this time, TG1 (i.e. N1 and P1) is ofand P2) is still ON (N2 turns on, while the drain anare connected to the same voltage). In this case, the final Cboost voltage in the read cycone time constant that is defined by the on-resistaN3 and NR transistors (Rstack) together with RN1tha

2( || ).1

2

1 . stack N boost

tR R Cstack

boostN

RV K e KR

−

= − + + +

where, Rstack and RN2 are the equivalent resistanceNR and N2 devices, respectively. As it can be seefinal value of Vboost is a value greater than zero bBy upsizing the stacked NMOS transistors, Vboost aIn this case, the size of the boosting capacitandischarging time of Cboost to its final value. During hold mode, when WLin becomes zero, for3×τinv, TG1 is OFF while N2 turns on. In this casperiod, the voltage at node MLWD goes towardsequal to -1V with a time constant of τ=RN2×Cbnegative voltage is determined by the boosting capRN2. After an extra elapsed time equal to 3τinv (to6×τinv from the beginning of standby mode), the Cto zero with a time constant determined by RP2||RNleakage power of the whole row, but its influence iis not so significant. On the other hand, the lower Wread reduces the total leakage power significantly in next sections. MLWD scheme results in 10%reduction for the whole SRAM array. Note that inthe applied negative voltage throughout the w

Fig.4: Simulation results for MLWD and CWD (C

Fig.3: MLWL outputs during read mode.

nning of read, the ever, after 6×τinv, n the MLWD node ff and TG2 (i.e. N2 nd the source of N2

cle is reached after ance of the stacked at is:

2 .2 (1)N boost

tR CK e

−

es for stacked N3-en from Eq. 1, the because Rstack>RN2. approaches to zero. nce determines the

r a delay equals to se, during the 3τinv s a negative value boost. Note that the pacitance Cboost and otal delay of 6τinv Cboost is charged up N1. This affects the in the total leakage WL voltage during as it is also shown % leakage current n order to maintain whole cycle, two

transmission gates can be used to discoinput signals.

IV. SIMULATION To show the efficacy of the pro

performed HSPICE simulations on a memory array using the proposed MLWwell as a conventional wordline in TSM Before going into the details of tmention that for comparison reasons wein [15] referred to as conventional worimplemented using a NAND gate that and the row decoder’s output. In additiwordline driver (CWD) design requirrows in an SRAM array. As we mentthe proposed MLWD circuit generates one for each operation mode. The outpuboosted wordline voltage to a VDD+α vavoltage becomes negative reducing thein read mode the wordline voltage raiseparagraphs we consider the different opcell, and later on we discuss about pbehavior of the proposed MLWD in pre A. Read mode Voltage waveforms showing the operatthe proposed MLWD are illustrated inshaped wordline voltage during read enthrough sense amplifiers. In Fig.4, we conventional wordline driver (CWD) anbitline discharging time is faster in casthat, for small loads, due to the boostedBL is discharged faster than the convebetter read access time. For instance, f=1GHz, at TT (Typical NMOS, Typicat Temp=27OC improves by 20% cosupply voltages, due to the delay of M

Cboost=10fF)

`Fig.5: Lowering the WL voltage effect time.

Fig.6: Current saving of MLWD durin

onnect TG1 and TG2 from the

RESULTS oposed MLWD technique, we

6T SRAM cell and 128KB WD wordline driver scheme as MC 65nm process technology.

he results we would like to e used the technique described rdline driver (CWD). CWD is takes inputs read/write signal

ion, note that the conventional res large buffers to drive the tioned in the previous section, three different voltage shapes ut of MLWD during write is a alue. During hold the wordline

e overall leakage current while ed to VDD+δ. In the following perational modes of the SRAM power savings as well as the esence of process variations.

tion of a 6T-SRAM cell using n Fig. 3. As it can be seen the nables SRAM to read the data plot the results for BLs with

nd MLWD. As it is shown, the e of MLWD than CWD. Note

d WL provided by MLWD, the entional case and hence shows read access time at VDD=1V, al PMOS) process corner, and

ompared to CWD. For lower MLWD design that is attributed

on SNM and Read access

ng Read

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to the transmission-gate transistors drivability, degrades by few percent compared to CWD. Thlowered level of wordline voltage during the read.load capacitance of the wordline driver (incrcolumns), the drivability of MLWD reduces resultwordline output during read. Lowering the WL volto make the access transistors “weaker” and thuSNM. However, this technique degrades the acweaker access transistors. Fig.5 explains how readtime are affected by lowering the WL voltage. Ilowering the WL voltage to ~0.6V, read access 40% while the read SNM improves by 2X. By apptechnique, read access time does not get degradSNM improves by more than two times. Table 1 shread SNM using MLWD and CWD topologies. Intedesign improves read SNM by at least 2.14X comscheme. All in all, MLWD design, degrades the acload capacitance while improves SNM significantlyboosted level of MLWD output depends on thewordline capacitance that is driven. In case that the sense amplifier senses a voltage dbetween the bitlines, the WL voltage is lowereaccess current for the remaining read cycle (≅90%TWL is the WL period). Fig.6 shows the accesthrough the pass-transistors of the SRAM cell durinand CWD. It is evident that our MLWD design p50% current savings during read compared to CWresult, MLWD reduces the power consumed byduring read. This is attributed to decreased currentaccess transistor (IPT). B. Write Mode Fig.7 shows the MLWD operation during write ait can be seen, during write, the wordline voltVDD+ , where is the boosted value that was diIII.

Fig.7: The output of the MLWD circuit during

Fig.8: Write delay for MLWD compared to CWD an

read access time his is attributed to . By increasing the reased number of ts in lower level of ltage level is a way

us to improve read ccess time due to d SNM and access It is apparent that time degrades by

plying the MLWD ded while the read hows the results for erestingly, MLWD

mpared to the CWD ccess time for large y. Furthermore, the e amount of total

difference (ΔVBL) ed to suppress the % of TWL, where ss current flowing ng read for MLWD provides more than

WD technique. As a y the SRAM cell t flows through the

and hold mode. As tage is boosted to iscussed in section

Writeability of MLWD improves duFig. 8, we compare the write delay techniques. Since, the MLWD design lower supply voltages, write delay istechnique. At lower supply voltages, thLPWD [7] or LPWD-SS [12]) results iMLWD technique. Fig.9 shows the wavduring write under different supply vwrite speed degrades which takes placeMLWD circuitry. By upsizing the (transmission-gate transistors), this prlower supply voltages. However, we hasupply voltages, the MLWD exhibits lothe negative BL methods (LPWD andesign also includes read-assist circuitrdesign to improve read margin. Instewordline signal to ground (during reavoltage to a level less than VDD thathrough access transistors. The results of write margin for the necompared to CWD and MLWD schemeThese simulation results show that the write margin compared to the MLWMLWD achieves 2.75X improvement the conventional design. Furthermore, delay at higher supply voltages compautilizing the MLWD design, Vmin is reat VDD=1V (CBL=400fF, CWL=50fF) whis reduced to 31mV. All in all, Vmin compared to CWD. C. Power consumption

In Fig.11, we have plotted IPT duMLWD and CWD schemes. To cperformed HSPICE transient analysimodes. The results show that MLWD dof SRAM cell by 12% compared to CW

Fig.9: Level of MLWD, at different opera

Fig.10: Write Margin comparison

g write.

nd LPWD ue to boosted WL voltage. In

for different wordline driver shows less rise in voltage at

s less affected by using this he negative BL technique (e.g. n a smaller delay compared to veforms of the MLWD output

voltages. We observe that the e due to the delay added by the

transistors in the MLWD roblem can be mitigated for ave to mention that for higher ower write delay compared to

nd LPWD-SS). The proposed ry compared to the LPWD-SS ead of shutting off the input ad), we lowered the wordline t helps to lower the leakage

gative bitline design (LPWD) es are depicted in Fig. 10. LPWD design provides better

WD technique. However, the in write margin compared to our design shows better write

ared to the LPWD design. By duced from 166mV to 96 mV hile the final Vmin for MLWD is improved by at least 43%

uring read and write modes for alculate power savings, we s for read, write, and hold design reduces the total power

WD design.

ation voltage

329

As we mentioned, read current is reduced bcompared to using CWD technique. However,wordline voltage during write, the MLWD schincrease in the IPT current compared to CWD. Cimprovement (12%) in total power saving is obsethat the number of read accesses is three times largof write accesses based on test-benchmarks [15]. the total savings will improve more than 1applications, where read is more prevalent. In thneglect the static power consumption of wordlinleakage of the cells due to the gate leakage.

D. Process Variations: In case of process variations (higher Vth value forby applying the CWD design, SRAM fails to restorage nodes during the specified pulse width. proposed MLWD design, if the specified pulse is nread the data, the SRAM still have the chance of re

Fig.11: Current savings during write and read operatio

Fig.13: The effect of process variations on the valu

Fig.12: Process variations effect on WL voltage durin

by more than 50% , due to boosted heme shows 37% Consequently, less erved. It is known er than the number This suggests that 2% for common

his comparison we ne drive and gate

r access transistors) ead the data from However, for the

not wide enough to eading the data at a

slower rate when wordline voltage is adesign is less prone to process variationstudy the proposed scheme under varCarlo simulations for both read and wsummarized in Figs. 12 and 13, respecwe observe that the effect of process under the lowest WL voltage. As it caand 17.4mV, respectively. Furthermoreα during write is 0.11V and equal to tour circuit demonstrates robust behavprocess variations and mismatches due in presence of process variations. E. Dynamic Noise Margin

Recently, increasing attention has analysis and dynamic noise margin (Dincorporation for SRAM cell analysisgrasp and explain the improvements ththe proposed technique. The premise is are not captured during the DC static paying attention to dynamic noise mashaped pulse during read cycle. Loweriread makes our design more stable (dycounterparts. Hence, in our design, a loperiod of time improves the read stabili

Initially we performed transient Hthe voltage waveforms (VL, VR and WLare shown in Fig.14 (a). DNM is impothat are statically unstable. Statically uread mode butterflies cross in one pFig.15. For instance, for that cell, if a t0) after some finite time it will cross treach the unique read mode EP. When will converge to (0, VDD) EP. It dynamically unstable because the storeand after read operation. However if thevoltage is short enough then the trajectoto cross the separatrix and reach the otdata. Note that the cell is dynamicallyread correctly. The above mentioned scF. Implementation-Area: We have implemented the layout of a tFig. 17 that is larger than standard layoof the MLWD and CWD designs are s

ons.

ue of α for the

Fig.14: Simulation results for CWD an

ng the read.

at VDD/2 level. As a result, our ns and more robust. In order to iations we performed Monte-

write modes and the results are ctively. In case of read mode, variations is more prominent

an be seen, μ and σ are 0.53V e, we observe that the mean of the designed value. Therefore vior in presence of transistor

to small variations of α value

been paid to dynamic stability DNM) [16], [17]. The DNM s is necessary in our case to hat are achieved by employing

to capture transient states that analysis. The main reason for argin here is that we used a ing the WL pulse width during ynamically) compared to other wer voltage (VF (WL)) after a ty.

HSPICE simulations to obtain L) with respect to time as they ortant when we deal with cells unstable cell is one where the point. That case is shown in rajectory starts from EP (VDD, the separatrix and then it will the access transistor closes, it is obvious that this cell is

ed data is not the same before e time that the WL is at a high ory may not have enough time ther EP, thereby, retaining the

y stable in this case since it is enarios are depicted in Fig.16.

thin-SRAM cell as depicted in out of SRAM cell. The layout shown in Fig.18.Note that the

nd MLWD design

330

capacitor Cboost is implemented using a MOSCshows different capacitance values at different bCboost=17fF, 10fF and 2fF for capacitance voltageand -1V respectively. Even though the area overhewordline driver is 46% the total area overheadcircuitry compared to CWD is less than 2.5% forarray that is shown in Fig.19. However, compared of SRAM array, proposed design has up to 10% are

V. CONCLUSIONS

In this paper, we proposed a multi-level(MLWD) that improves write/read noise margileakage power and limiting the read access time proposed MLWD scheme, improves the read noise2X compared to the conventional wordline drivpower is reduced by at least 12% compared toSRAM due to a lowered drive current through the read mode and lower leakage in standby moproposed MLWD scheme can be applied to anysuggested to accompany SRAM cells with different

IV.REFERENCES

[1] Chang E, et al., “Using a Statistical Metrology FraSystematic and Random Sources of Die- and Wafer-lVariation in CMP Processes,” IEDM Tech. Digest, pp. 49[2] Panagopoulos G. and Roy K., "A Physics-Based 3-D RDF Induced Threshold Voltage Variations," TED, Vol403, 2010.

Fig.17: Thin-cell 6T-SRAM cell layout.

Fig.15: Simulations results for comparison of the C

Fig.16: Simulation results for MLWD at different levVF(WL).

CAP device which iases, for instance

e equal to 1V, 0V, ead for a single bit d due to MLWD r a 128Kb memory to standard layout

ea overhead.

l wordline driver in while lowering degradation. The

e margin by at least ver (CWD). Total o the conventional pass-transistors in de. Although the

y SRAM cell, it is tial bitlines.

amework to Identify level ILD Thickness 99-502, 1995. Analytical Model for . 58, No. 2, pp. 392-

[3] Mukhopadhyay S. et al., “Modeling of design of SRAM array for yield enhancemTCAD, vol. 24, no. 12, pp. 1859–1880, 2005[4] Gonzalez, et. al., "Supply and threshold vCMOS,"IEEE JSSC vol.32, no.8, pp.1210-12[5] Verma N. et al., "A 65nm 8T Sub-Vt SRRedundancy," IEEE ISSCC , pp.328-606, 20[6] Verma, N.; Chandrakasan, A.P.; , "A SRAM Employing Sense-Amplifier RedundJournal of , vol.43, no.1, pp.141-149, Jan. 20 [7] Hirabayashi O., "A process-variation-towith 0.179µm2 Cell in 40nm CMOS usindriver, "IEEE ISSCC,2009.pp.458-459,459a,[8] Nii, K et al., "A 45-nm single-port anrobust read/write stabilizing circuitry unCircuits Symposium, pp.212-213, 2008 [9] Yabuuchi, M. et al., "A 45nm Low-Swith Improved Immunity Against Process anISSCC 2000, pp.326-606, 11-15 Feb. 2007 [10] Yabuuchi et al., "A 45nm 0.6V crosbiased read/write assist, "VLSI Circuits Symp[11] Mukhopadhyay S. et al., "SRAM WTransient Negative Bit-Line Voltage, "IEEE[12] Hirabayashi O. et al., "A process-varSRAM with 0.179µm2 cell in 40nm CMwordline driver, " ISSCC 2009, pp. 458-459,[13] Kolar, P., et al., "A 32 nm High-k MDynamic Stability Enhancement for LowCircuits, IEEE Journal of , vol.46, no.1, pp.7[14] Schuster S. E. et al., “A 15-ns CMOS 6Circuits, vol. 21, pp. 704–711, Oct. 1986. [15] McNairy et al., "Itanium 2 processor mivol.23, no.2, pp. 44- 55, March-April 2003. [16] Sharifkhani, M. et al., "SRAM Cell StIEEE JSSC, vol.44, no.2, pp.609-619, 2009. [17] Khalil, D. E. et al., "Accurate EstimatiIEEE TVLSI vol.16, no.12, pp.1639-1647, 20

Fig. 18: Layout of (a) MLWD (b) CW

Fig.19: Layout of 128KB SRAM array CWD layouts

CWD and MLWD.

vels of

f failure probability and statistical ment in nanoscaled CMOS,”IEEE 5. voltage scaling for low power 216, Aug 1997. RAM Employing Sense-Amplifier 007.

256 kb 65 nm 8T Subthreshold dancy," Solid-State Circuits, IEEE 008. olerant dual-power-supply SRAM ng level-programmable wordline , 8-12 Feb. 2009. nd dual-port SRAM family with

nder DVFS environment, "VLSI

tandby-Power Embedded SRAM nd Temperature Variations, "IEEE

s-point 8T SRAM with negative posium, 2009, pp.158-159 Write-Ability Improvement with

E TVLSI, pp.24-32, 2011 riation-tolerant dual-power-supply MOS using level-programmable , 459a.

Metal Gate SRAM With Adaptive w-Voltage Operation," Solid-State 76-84, Jan. 201 64K RAM,” IEEE J. Solid-State

icroarchitecture," in Micro, IEEE ,

tability: A Dynamic Perspective,"

ion of SRAM Dynamic Stability," 008.

WD designs.

including MLWD and

331