Multi-Gbit/s CMOS Transimpedance Amplifier with Integrated Photodetector...
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Multi-Gbit/s CMOS Transimpedance Amplifier with Integrated Photodetector for Optical Interconnects A Ph. D. Thesis Presented to The Academic Faculty by Indal Song In Partial Fulfillment of the Requirement for the Degree of Doctor of Philosophy in Electrical and Computer Engineering Georgia Institute of Technology November, 2004
Transcript of Multi-Gbit/s CMOS Transimpedance Amplifier with Integrated Photodetector...
Multi-Gbit/s CMOS Transimpedance Amplifier with Integrated Photodetector for Optical Interconnects
A Ph. D. Thesis Presented to The Academic Faculty
by
Indal Song
In Partial Fulfillment of the Requirement for the Degree of
Doctor of Philosophy in Electrical and Computer Engineering
Georgia Institute of Technology
November, 2004
Multi-Gbit/s CMOS Transimpedance Amplifier with Integrated Photodetector for Optical Interconnects
Approved by: Dr. Martin A. Brooke School of Electrical and Computer Engineering
Dr. Stephen P. DeWeerth School of Electrical and Computer Engineering
Dr. David E. Schimmel School of Electrical and Computer Engineering
Dr. David S. Citrin School of Electrical and Computer Engineering
Dr. Paul A. Kohl School of Chemical and Biomolecular Engineering
Novermber 19, 2004
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ACKNOWLEDGEMENTS
This dissertation could not have been written without Dr. Martin A. Brooke who
not only served as my research advisor but also encouraged and challenged me
throughout my graduate program.
During the course of my stay at Georgia Institute of Technology, he and the other
distinguished faculty members, Dr. Nan M. Jokerst, Dr. Stephen P. DeWeerth, Dr. David
E. Schimmel, Dr. David Citrin, and Dr. Paul A. Kohl patiently guided me through the
dissertation process, never accepting less than my best efforts. I would like to express my
appreciation to them.
I’m also grateful that I had opportunities to work with my colleagues/friends,
Seokhun Hyun, Daeik Kim, Ananthasayanam Chellappa, Jaemin Shin, Jaehong Kim,
Cheolung Cha, and Sungyong Jung for their help and valuable inputs towards this work. I
thank them all.
Finally, I would like to take this opportunity to thank my wife, Sunwook, and my
daughter, Irene, for their continuous support and all the joy that they bring into my life.
November 19, 2004
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TABLE OF CONTENTS
ACKNOWLEDGEMENTS............................................................................................... iii
LIST OF TABLES............................................................................................................. vi
LIST OF FIGURES .......................................................................................................... vii
SUMMARY....................................................................................................................... ix
CHAPTER I INTRODUCTION .................................................................................1
1.1 Generic Fiber Optic Communication System..............................................3
1.2 Objectives ....................................................................................................5
CHAPTER II BACKGROUND AND DESIGN CONSIDERATION ........................7
2.1 Background..................................................................................................7
2.1.1 Photodetectors..................................................................................8
2.1.2 Characteristics of Preamplifier ......................................................10
2.1.3 Sensitivity and Bit-error-rate .........................................................11
2.1.4 Eye Diagram ..................................................................................15
2.2 Noise Consideration...................................................................................19
2.2.1 Device Intrinsic Noise....................................................................20
2.2.2 Noise Requirements .......................................................................21
2.2.3 Noise and Bandwidth Trade-off.....................................................25
CHAPTER III DESIGN OF OPTICAL PREAMPLIFIER CIRCUIT ........................28
3.1 Introduction................................................................................................28
3.2 Transimpedance Stage ...............................................................................30
3.2.1 Principal Preamplifier Topologies .................................................30
3.2.1.1 High Impedance Open-loop Amplifier ..............................31
3.2.1.2 Low Impedance Open-loop Amplifier...............................33
3.2.1.3 Transimpedance Feedback Amplifier ................................35
3.2.2 Differential Topology ....................................................................39
3.2.3 Co-Design of Frontend ..................................................................42
3.2.3.1 Quantum Efficiency and Bandwidth..................................43
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3.2.3.2 Optimized Sensitivity.........................................................45
3.2.4 Transimpedance Amplifier Design ................................................49
3.3 Post-amplifier and Output Buffer ..............................................................52
3.3.1 Cascaded Amplifier .......................................................................53
3.3.2 Bandwidth Enhancement ...............................................................55
3.3.2.1 Cherry-Hooper Amplifier ..................................................56
3.3.2.2 Capacitive Peaking.............................................................58
3.3.2.3 Source Degeneration..........................................................60
3.3.2.4 Inductive Peaking...............................................................62
3.3.3 Post-amplifier Design ....................................................................65
3.3.4 Output Buffer Design.....................................................................68
CHAPTER IV SIMULATIONS, LAYOUT, AND MEASUREMENTS....................70
4.1 Simulations ......................................................................................................70
4.1.1 HPADS Simulation........................................................................70
4.1.2 HSPICE Transient Simulation .......................................................73
4.1.3 AC and Noise Simulation ..............................................................80
4.1.4 Packaging Effect Simulation..........................................................85
4.2 Layout 88
4.3 Measurements ..................................................................................................91
4.3.1 Measurement Setup........................................................................91
4.3.2 Measurement Results .....................................................................94
CHAPTER V CONCLUSIONS................................................................................100
APPENDIX I ...................................................................................................................104
REFERENCES ................................................................................................................156
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LIST OF TABLES
1.1 SONET/SDH standard bit rates ...............................................................................2
2.1 Relationships between BER, Q, and SNR .............................................................24
2.2 Cumulative power spectrum of NRZ signal ..........................................................27
3.1 Required cell bandwidth for n-cascaded amplifier ................................................54
3.2 Required cell gain for n-cascaded amplifier ..........................................................54
5.1 Performance comparison of CMOS preamplifiers ..............................................101
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LIST OF FIGURES
1.1 Diagram of generic optical communication system interface..................................3
2.1 Equivalent circuit model of photodetector...............................................................8
2.2 Power unit conversion graph .................................................................................11
2.3 Example of BER vs Sensitivity curve....................................................................13
2.4 Example of eye-diagram........................................................................................15
2.5 Example of pattern dependent jitter.......................................................................17
2.6 Example of pulse width distortion .........................................................................18
2.7 Probability of error of binary-coded signal............................................................22
2.8 Normalized power spectral density of NRZ signal................................................25
3.1 Block diagram of optical frontend .........................................................................29
3.2 Integrating amplifier ..............................................................................................31
3.3 Common-gate preamplifier....................................................................................33
3.4 Two-stage feedback amplifier................................................................................36
3.5 Single-stage feedback amplifier.............................................................................37
3.6 Small signal models of single-ended and differential amplifier including power supply inductances......................................................................40
3.7 Simplified schematic of optical frontend with noise sources ................................46
3.8 Plot of normalized RMS noise vs normalized input capacitance ..........................48
3.9 Transimpedance feedback amplifier using OP-Amp.............................................49
3.10 Transimpedance stage............................................................................................51
3.11 Cherry-Hooper amplifier .......................................................................................57
3.12 Capacitive peaking.................................................................................................59
3.13 Source degeneration...............................................................................................60
3.14 Shunt peaking.........................................................................................................62
3.15 Series peaking ........................................................................................................64
3.16 Post amplifying stage.............................................................................................65
3.17 Output buffer..........................................................................................................69
4.1 Transimpedance gain curve using slow transistor corner model ...........................71
4.2 Transimpedance gain curve using typical transistor corner model........................72
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4.3 Transimpedance gain curve using fast transistor corner model.............................72
4.4 Simulated eye-diagram using slow corner model operating at 5Gbit/s .................74
4.5 Simulated eye-diagram using typical corner model operating at 5Gbit/s..............75
4.6 Simulated eye-diagram using fast corner model operating at 5Gbit/s...................76
4.7 Simulated eye-diagram using slow corner model operating at 10Gbit/s ...............77
4.8 Simulated eye-diagram using typical corner model operating at 10Gbit/s............78
4.9 Simulated eye-diagram using fast corner model operating at 10Gbit/s.................79
4.10 CMRR curves of circuit using slow, typical, and fast corner model .....................80
4.11 Noise simulation result using slow transistor corner model ..................................82
4.12 Noise simulation result using typical transistor corner model...............................83
4.13 Noise simulation result using fast transistor corner model....................................84
4.14 Model of package line impedance .........................................................................85
4.15 Transient response without power supply decoupling capacitors..........................86
4.16 Transient response with power supply decoupling capacitors...............................87
4.17 Layout of preamplifier circuit ................................................................................89
4.18 Photograph of preamplifier circuit with integrated I-MSM photodetector............92
4.19 Test board of integrated optical frontend circuit....................................................92
4.20 Measurement setup diagram ..................................................................................93
4.21 Eye-diagram with 57uApp input photocurrent operating at 5Gbit/s .....................94
4.22 Eye-diagram with 113uApp input photocurrent operating at 5Gbit/s ...................95
4.23 Eye-diagram with 57uApp input photocurrent operating at 10Gbit/s ...................95
4.24 Eye-diagram with 113uApp input photocurrent operating at 10Gbit/s .................96
4.25 Eye-diagram with 57uApp input photocurrent operating at 5Gbit/s .....................97
4.26 Eye-diagram with 113uApp input photocurrent operating at 5Gbit/s ...................97
4.27 Eye-diagram with 57uApp input photocurrent operating at 10Gbit/s ...................98
4.28 Eye-diagram with 113uApp input photocurrent operating at 10Gbit/s .................98
4.29 Measured BER vs Input photocurrent....................................................................99
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SUMMARY
Trends toward increased integration and miniaturization of optical system
components have created pressure to consolidate widely disparate analog and digital
functions onto fewer and fewer chips with a goal of eventually built into a single mixed-
signal chip. Yet, because of those performance requirements, the frontend circuit has
traditionally used III-V compound semiconductor technologies, but the low-level of
integration with other digital ICs limits the sustainability of such end products for short-
distance applications. On the other hand, their CMOS counter parts, despite having such
advantages as low power consumption, high yield that lowers the cost of fabrication, and
a higher degree of integration, have not performed well enough to survive in such a noisy
environment without sacrificing other important attributes.
In this research, a high-speed CMOS preamplifier was designed and fabricated
through TSMC 0.18µm mixed-signal non-epi CMOS technology, and a 20µm diameter
InGaAs thin-film Inverted-MSM photodetector with a responsivity of 0.15A/W at a
wavelength of 1550µm was post-integrated onto the circuit. The circuit has a overall
transimpedance gain of 60dBΩ, and bit-error-rate data and eye-diagram measurement
results taken as high as 10Gbit/s are reported in this dissertation.
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CHAPTER I
INTRODUCTION
The advent of cheaper and more powerful personal computers has not only
expanded the user base but also created a demand for greater transmission capacity
among the telecom networks. In state-of-the-art technology, fiber optic devices and
systems are widely deployed to satisfy this need for more data throughput economically.
Fiber optic communication is an economic solution because its physical nature lets
network providers expand capacity either by increasing the transmission bit rate or by
introducing alternative transmission techniques. Neither alternative requires further
upgrades or additional cable installations [60-63].
In modern fiber optic transmission systems, the synchronous optical network
(SONET) and synchronous digital hierarchy (SDH) standard define a technology for
carrying many signals of different capacities through a synchronous, flexible, optical
hierarchy by means of a byte-interleaved multiplexing scheme [64-65]. The basic
transmission bit rate is OC-1 at 51.8Mbit/s, and higher bit rates offered by SONET/SDH
are summarized in Table 1.1. Furthermore, new techniques such as wavelength division
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multiplexing (WDM) have increased transmission capacity by sending numerous data
streams over one fiber by using a different wavelength for each one of them.
Table 1.1 SONET/SDH standard bit rates
SONET SDH Bit Rate
OC-1 - 51.84 Mbit/s
OC-3 STM-1 155.52 Mbit/s
OC-12 STM-4 622.08 Mbit/s
OC-48 STM-16 2.4883 Gbit/s
OC-192 STM-64 9.9533 Gbit/s
OC-768 STM-196 39.8131 Gbit/s
The transmission of optical data via fiber cables involves electrical-to-optical
conversion at the transmission end and optical-to-electrical at the receiving end. These
conversion processes are handled by optoelectronic transceiver units that contain
electronic devices and semiconductor optical components.
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1.1 Generic Fiber Optic Communication System
Figure 1.1 depicts a typical interface of an optical communication system [1-3]. It
consists of both digital (MUX and DEMUX) and analog building blocks such as a
transimpedance amplifier (TIA), a limiting amplifier (LA), laser driver, clock and data
recovery (CDR), and other sub components.
Figure 1.1 Diagram of generic optical communication system interface
In the transmitter, a number of channels are multiplexed into a high-speed data
stream. This data stream is retimed and applied to a laser driver, and the optical output is
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delivered to the fiber. The phase-locked loop (PLL) generates clocks for both the
multiplexer and the retiming circuit. Also, because the power of the laser output varies
with temperature and aging, a monitor PD and a power control circuit continuously adjust
the output level of the driver.
In the receiver, the PD converts the received light to a signal current, and the
signal swing is amplified to logic levels. Subsequently, the CDR performs timing and
amplitude-level decisions on the incoming signal, which leads to a time- and amplitude-
regenerated data stream. The result is then demultiplexed, thereby reproducing the
original channels.
The lightwave traveling through the fiber usually undergoes considerable
attenuation before reaching the PD. This attenuation requires a subsequent stage to detect
and amplify the signal at an acceptable bit-error-rate (BER). Hence the TIA, the first
stage of amplification, should provide both high overload tolerance and high input. To
provide the high input sensitivity necessary to receive optical signals weakened by
transmitter aging and/or long transmission distance, the TIA noise must be reduced to a
minimum. On the other hand, a high overload tolerance is required to avoid bit errors
caused by distortion in the presence of strong optical signals. Furthermore, to ensure
stable operation and the required bandwidth, gain can be optimized only within a narrow
range. This limitation sometimes causes the output voltage that results from low-power
optical signals to be insufficient for further processing. Therefore, the LA often follows
to amplify small TIA voltages.
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1.2 Objectives
Trends toward increased integration and miniaturization of optical system
components have created pressure to consolidate widely disparate analog and digital
functions onto fewer and fewer chips with a goal of eventually built into a single mixed-
signal chip. Yet, although the intrinsic speed of CMOS devices has dramatically been
improved via aggressive scaling, the consolidation of multiple functions onto a single
chip for use in fiber optic communication systems has been impeded by mixed-signal
issues like noise and cross-talk.
In most optical communication systems, the frontend of the receiver consists of a
PD and a preamplifier. Because of those performance requirements, the frontend circuit
has traditionally used III-V compound semiconductor technologies, but the low-level of
integration with other digital ICs limits the sustainability of such end products for short-
distance applications. On the other hand, their CMOS counter parts, despite having such
advantages as low power consumption, high yield that lowers the cost of fabrication, and
a higher degree of integration, have not performed well enough to survive in such a noisy
environment without sacrificing other important attributes. This performance
shortcoming is mainly due to the nature of silicon CMOS devices that have limited gain,
limited bandwidth, low substrate resistance, and large parasitic capacitances as well. The
low-voltage headroom in submicron CMOS technologies also is an obstacle to the
implementation of broadband amplifiers [25, 66-68].
The optical frontend can be realized with monolithic optoelectronic integrated
circuits (OEIC) that have all the components in a single chip, or with discrete
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components put together on a printed circuit board (PCB). In these multi-chip products,
the PDs and circuits are individually optimized, fabricated and packaged in separate
processes and connected by external wires. However, these interconnections may cause
unwanted parasitic feedbacks that degrade overall system performance. Two major
factors in such degradation are inadequate electromagnetic interference (EMI) properties
and poor bandwidth because of finite line impedance effects. Moreover, the larger
footprint required by the separate chip package that results in the higher fabrication cost
cannot be ignored.
The primary object of this research is to develop a high-speed CMOS optical
receiver frontend with a heterogeneously integrated PD that can satisfy performance,
compatibility, and cost issues. The theoretical backgrounds of the components and the
characteristics of the optical frontend were reviewed as part of the research. Furthermore,
various aspects that affect the performance of the amplifier as well as circuit techniques
to overcome the limitations of CMOS technology were investigated. Details of designing
a CMOS preamplifier - including circuit topologies, layout, and integration aspects - are
discussed, and measurement results taken as high as 10Gbit/s are reported in this
dissertation.
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CHAPTER II
BACKGROUND AND DESIGN COSIDERATION
2.1 Background
An optical receiver frontend consists of two major parts, a semiconductor PD
followed by an electronic signal amplifier. Light traveling through the fiber undergoes
considerable attenuation before reaching the PD, thus requiring a highly sensitive
receiver to detect the signal at an acceptable BER. Hence the performance of the receiver
is often characterized by the input sensitivity, bandwidth, and detection method employed
in the receiver [4]. This sensitivity can be expressed in terms of mean optical input power
or root-mean-square (RMS) input-referred noise. Bandwidth is usually determined by the
total capacitance contributed by the PD, the preamplifier, and other parasitic elements
present at the optical frontend.
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2.1.1 Photodetectors
The fundamental mechanism behind the optical-to-electrical signal conversion is
optical absorption. This involves basic concepts such as responsivity, quantum efficiency,
and bandwidth. In the operation of the PD, it is reverse-biased, absorbing the incident
radiation and in turn generating electron-hole pairs that drift to the metal contacts to
generate a current in the external circuit [5]. An equivalent circuit model of the PD is
often represented by a current source with a shunt capacitance CPD, as shown in Figure
2.1.
Preamplifier Preamplifier
Figure 2.1 Equivalent circuit model of PD
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Commonly adopted types are p-i-n, avalanche, and metal-semiconductor-metal
(MSM) PDs, with the types defined based on the photo-detection process each one uses
and on their physical structures.
First, the p-i-n PD consists of a highly resistive middle layer interposed between p
and n sections to create a wide depletion region in which a large electric field exists.
Most of the incident power is absorbed inside the i-region and drifted away; thus, the drift
component of the photocurrent dominates over the slow diffusion component that can
distort the temporal response of the PD.
Second, the avalanche PD uses an impact ionization mechanism in which an
additional multiplication layer is introduced to generate secondary electron-hole pairs that
result in an internal current gain. An avalanche PD is often used when the amount of
optical power that can be spared for the receiver is limited; however, the avalanche
process has major drawbacks in its high noise contribution and in the trade-off between
gain and bandwidth [6-7].
The MSM PD has been gaining attention for application as an integrated
photoreceiver. Its light-absorbing layer is sandwiched between inter-digitated metal
electrodes forming Schottky barriers. The main advantage lies in its planar structure,
which results in relatively low capacitance per unit area and ease of integration [8]. For
example, a typical 20µm diameter MSM PD with 1µm electrode width and spacing
exhibits less than 20fF of capacitance.
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2.1.2 Characteristics of Preamplifier
The small photocurrent generated by the PD must be converted, with a minimum
amount of added noise, to a usable signal for further processing. A larger signal swing
may be obtained by widening a light reception window to increase responsivity, but this
larger signal swing then comes at a cost of an increased response time. Hence, a
preamplifier is used as the first stage of amplification and has great impact on
determining the overall data rate and sensitivity that can be achieved in an optical
communication system. Typically, the preamplifier is required to be able to accommodate
wideband data extending from dc to high frequencies to avoid inter-symbol interference
(ISI). At the same time, it is also desirable to maintain a reasonable signal gain, in-band
noise, ripple, and phase distortion to improve the sensitivity [9]. As performance
indicators, BERs are used to determine the bandwidth and the sensitivity, and eye-
diagrams can be visual aids to estimate or trouble-shoot sources of noise and other
limiting factors.
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2.1.3 Sensitivity and BER
A receiver is said to be more sensitive if it achieves the same performance with
less optical power incident on it. The launched optical power is an important parameter,
because it indicates how much light is arriving at the surface of the photodetector. It is
often expressed in units of dBm with 1mW as the reference level, and the general
definition is
Power(dBm) =10 ⋅ log10( IncidentPower1mW
) (2.1)
and an example of a power unit conversion graph is shown in Figure 2.2.
0
0.2
0.4
0.6
0.8
1
1.2
0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20
dBm
Figure 2.2 Power unit conversion graph
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In digital systems, the signal uses digital discrete modulation of optical field. The
receiver recovers a sequence of binary digits (bits) from the incoming optical signal field,
thus, the technique used to specify a digital receiver’s sensitivity is different from that
used for an analog receiver. The primary measure of the performance of such systems is
to quantify the probability that the receiver will make an incorrect decision. Therefore,
the BER is defined as the ratio of number of incorrect identifications to total number of
bits received by the decision circuit of the receiver. For example, a BER of 1x10-9
corresponds to on average of one error per thousand million bits.
Measuring BER and simultaneously varying the amount of optical power received
yields a bath-tub shaped plot similar to Figure 2.3. At low levels of the received optical
power range, the error rate will be relatively high. As the received optical signal power
increases, the probability of making a bit-error decreases. In a correctly designed link, a
point will be reached that satisfies the user’s quality-of-service requirements for BER. At
higher received optical signal power levels, the BER will usually continue to decrease
and the system will become error-free. However, it is possible for a BER “floor” to be
observed in some systems. These are usually caused by subtle receiver degradations that
are independent of the amount of received optical signal power. Some forms of
interference, clock jitter, data pattern dependence, and setup and hold-time violations in
digital circuit designs can cause the occurrence of BER floors.
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Figure 2.3 Example of BER vs Sensitivity curve
Ultimately, if the received power continues to increase, the receiver will
eventually overload and the error rate will rise. The difference between the point at which
there is just enough received optical signal power to meet the desired BER and the point
at which receiver overload causes the BER to rise to unacceptable levels is the receiver
dynamic range. In other words, the minimum allowable optical power at the receiver
input is determined by the receiver sensitivity. The receiver has to operate not only at the
minimum detectable power but also at optical power levels that are sometimes
significantly larger. The receiver dynamic range is the difference (in dB) between the
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minimum detectable power levels, the equivalent of receiver sensitivity, and the
maximum detectable power level. Maximum allowable input-received power levels can
be determined when the amplifier output starts to be affected by nonlinear dynamic
effects, which is a function of either the bias resistor or of the feedback resistor. As the
bias resistor decreases, the maximum allowable received optical power increases. Thus,
dynamic range is increased. However, a reduction in the resistor value results in an
increase in the amplifier noise level. Therefore, a trade-off is required between high
receiver sensitivity and wide dynamic range.
The amount of optical signal power that produces a receiver BER of 10-12 is a
widely used measure of receiver performance for 10-Gigabit optical links and is
frequently referred to as receiver sensitivity. Although the BER can be defined as the
number of errors made per second, such a definition makes the BER dependent on bit-
rate.
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2.1.4 Eye Diagram
Another way to characterize a receiver performance is to qualitatively measure the
properties of a recovered waveform of binary-coded data. By overlaying the transition (1-
0 & 0-1) of all different possible combinations of bit patterns at their respective decision
times, a waveform called an eye-diagram that is shaped similar to a human eye is
obtained, as shown in Figure 2.4. Depending on standards, pseudo-random bit stream
(PRBS) patterns are typically used, although eye diagrams of other non-random data
patterns also can be examined.
Figure 2.4 Example of eye-diagram
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An eye-diagram – the display that results from the overlap of a series of data
waveforms – is the most common method of characterizing the quality of a signal. It is
obtained when an oscilloscope is triggered synchronously with the data stream. A
synchronous clock signal, the data itself, or the clock recovered from the output data is
usually used to trigger the scope. In one captured screen, all possible transitions of the
signal are displayed. Consequently, the characteristics of the opening of the eye permit
noise, jitter, rise and fall times, and amplitude to be observed and measured. Closure of
the eye in the eye-diagram can result from various sources. Mismatched transmission line
impedances will add ripples that will increase overshoot and close the eye both
horizontally and vertically. Insufficient bandwidth of circuits or excessive losses of
cables and PCBs can result in vertical eye closure.
Eye-diagrams quantify the amount of amplitude noise and time variation (or jitter)
that will close the eye-diagram vertically and horizontally, respectively [78-79]. Jitter
involves three significant sources. First, random jitter (RJ) is caused by random noise,
which results in random midpoint crossings that are present during edge transitions.
Second, pattern-dependent jitter (PDJ), shown in Figure 2.5, results from variations in the
number of consecutive bits representing the same logic level in data streams. The PDJ
usually appears in the eye diagram when the receiver bandwidth doesn’t meet the
system’s required low-frequency and/or high-frequency cut-off. If the location of the
lower cutoff frequency does not pass the low frequencies associated with long
consecutive bit streams, a signal droop can be observed in the waveform, a condition that
is often called baseline wander. At the end of the droop period, the signal is again shifted
with respect to the decision threshold. On the other hand, when the bandwidth of the
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receiver is not high enough, the receiver cannot allow for complete transitions during
single-bit patterns, thereby resulting in high frequency PDJ.
Figure 2.5 Example of pattern dependent jitter (PDJ)
Finally, Figure 2.6 shows pulse-width distortion (PWD) that happens when the
midpoint crossing of a low-to-high and a high-to-low transition does not occur at the
same level because of DC offsets and nonsymmetrical rising and falling times.
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Figure 2.6 Example of pulse width distortion (PWD)
It is desirable that the eye diagram waveform doesn’t enter the masked area
shown in Figure 2.4. The size and shape of this area varies, depending on the data rate.
The ideal decision sampling point occurs at the time of the maximum vertical opening,
which can be determined from the eye diagram; this point corresponds to the time when
the signal-to-noise ratio (SNR) is at its maximum. Therefore, an eye diagram, combined
with histograms of jitter and noise, can function as the key tool to estimate system
reliability
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2.2 Noise Consideration
In direct-detection optical systems, the receiver is composed of a PD, amplifier
circuit, and a CDR circuit. Generally, a semiconductor PD receives binary coded optical
pulses representing “1” and “0” bits and converts them into electrical currents while the
detection circuit that identifies bits as either “1” or “0” depends on signal amplitude.
Hence the accuracy of the decision circuit depends heavily on the SNR of the electrical
signal detected by the PD and the subsequent amplifier.
As mentioned in the previous section, sensitivity, which is defined as the
minimum average received optical power for which the optical receiver can achieve a
certain BER, is the major parameter that characterizes receiver performance. It is related
to the SNR, which in turn depends on various noise sources that corrupt the desired
signal. The photo-detection process itself introduces some noise even in a perfect
noiseless receiver, which is often called a quantum-noise-limited receiver, In fact, such
an ideal receiver does not exist because as many other noise sources degrades the SNR
considerably beyond the shot-noise limit. In addition to noises introduced by receivers,
the optical signal launched by the transmitter may have inherent intensity and phase
fluctuations and chromatic dispersion of the optical fibers may contribute additional
noise. Therefore, receiver sensitivity is determined by the cumulative effect of all
possible noise mechanisms as well as by the bit rate of the data because some noise
sources are related to signal bandwidth.
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2.2.1 Device Intrinsic Noise
The noise intrinsic to devices in all electronic circuits fall into three major
categories: shot noise, thermal noise and flicker noise [72-73].
First, shot noise is generated when a current flows across a potential barrier and is
caused by the random fluctuation of the current above and below its average value. This
occurs in vacuum tubes and in semiconductor devices. In semiconductors, it is due to the
random diffusion of holes and electrons through a p-n junction and to the random
generation and recombination of hole-electron pairs. Shot noise is generally modeled
with the device as a parallel noise current source, and the Norton equivalent noise current
source is given by
Ish = 2qI∆f (2.2)
Second, thermal noise is generated when thermal energy causes free electrons to
move randomly in a resistive material, and the equivalent noise current source is given by
It =4kT∆f
R (2.3)
for resistors, and
It = 4kTγgm∆f (2.4)
for MOSFETs, respectively, where k is Boltzmann’s constant, T is the absolute
temperature, R is the resistance, and gm is the transconductance.
The last noise source, flicker noise, is caused by the imperfect contact between
two conducting materials when the conductivity is fluctuating in the presence of DC
current, or, in the case of MOSFET, the drain bias current. This noise source is also
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modeled as a noise current source in parallel with the device and given by
n
mf
f ffIK
I∆
= (2.5)
where 1< m <3.
2.2.2 Noise Requirements
To derive a relationship between SNR in an analog system and BER in binary
optical communication system, two separate SNRs associated with the high and low
levels of the signal need to be combined into a single quantity. The error probability of
the two-level digital signal can be expressed in terms of probabilities of “1”, P(1), and
“0”, P(0). Also, the conditional probabilities of error are P(1|0) and P(0|1). Hence the
definition of the probability of error, P, as Gaussian noise that will cause the signal plus
noise at the decision instant to cross the threshold level to the opposite side from the
signal alone is
P = P 10( )⋅ P 0( )+ P 01( )⋅ P 1( ) (2.6)
as illustrated in Figure 2.7.
22
Figure 2.7 Probability of error of binary-coded signal
Assuming the conditional probabilities are equal, and if ones and zeros are
equally probable, the probabilities P(1) and P(0) are both 0.5, and the above equation
becomes
P =12
[P 1 | 0( )+ P 0 |1( )]
= P 1 | 0( )
= p(x)dx∫ (2.7)
by symmetry. The definite integral will have a lower limit equal to half the peak-to-peak
value, Vpp/2, and an upper limit of infinity. Because the distribution is Gaussian, the
right-hand side of the equation can be expressed as
23
P(1 | 0) =1
σ 2πexp(− x 2
2σ 2 )dxVpp / 2
∞∫
= 12
erfc(Vpp
2σ 2) (2.8)
where erfc stands the complementary error function, defined as
erfc(x) =2π
exp(−y 2)dyx
∞∫ (2.9)
Hence the probability of error is given by
P =12
erfc( Q2
) (2.10)
where
Q =Vpp
2σ=
V1 −V0
σ (2.11)
The probability of error in the binary coded digital system is commonly called the
BER. The parameter Q [10] represents SNRs of the high and low levels of the digital
signal, and is the ratio of the peak-to-peak signal to the RMS value of associated noises.
The maximum input noise level to acquire a certain level of BER can be derived
mathematically by the above equation, and their relation in terms of Q is
Q2 =Isignal
2
Inoise2
(2.12)
where Q is a power SNR, Isignal is the current signal converted by a PD, and Inoise2 is the
total input-referred noise power. Therefore, the Inoise requirement can be obtained because
the Isignal is a known value and can be obtained from the optical input power incident to
the PD, and the sensitivity requirement of the receiver amplifier for a certain BER can be
estimated from the following relationship given by
24
BER ≈1
Q 2π⋅ exp −
Q2
2
(2.13)
Table 2.1 Relationships between BER, Q, and SNR
BER Q SNR
1.00E-06 4.75 13.53
1.00E-07 5.20 14.32
1.00E-08 5.61 14.98
1.00E-09 5.99 15.55
1.00E-10 6.36 16.07
1.00E-11 6.71 16.53
1.00E-12 7.03 16.94
1.00E-13 7.35 17.33
25
2.2.3 Noise and Bandwidth Trade-off
Of the many encoding methods used to transmit a binary digital signal, non-
return-to-zero (NRZ) is one of the most common in fiber optic communication systems.
Since each binary digits representing logic levels “1” and “0” is assigned an equal
amount of time, it can be said that the probability in which either “1” or “0” will appear
in the data stream is also equal. With these assumptions, the power spectral density of
NRZ coded data can be calculated [80]. Integration over the frequency of the power
spectrum results in a curve having a form of (sin xx
)2 and is not band limited as illustrated
in Figure 2.8.
QuickTime?and aTIFF (LZW) decompressor
are needed to see this picture.
Figure 2.8 Normalized power spectral density of NRZ signal
26
However, in reality, a system cannot have infinite bandwidth and is bound to have
a certain cutoff frequency. It is also notable that cumulative noise power increases
proportionally with the increase in the system bandwidth, which leads to a trade-off
between bandwidth and noise.
Table 2.2 tabulates a cumulative power spectrum of a NRZ signal. The majority
of the signal power (92%) of the NRZ-coded data is constrained within the frequency of
0.7 times the bit-rate Rb, thus the cutoff frequency,
f−3dB = 0.7 × Rb (2.14)
is considered a logical compromise between bandwidth and noise [11]. In fact, for
example, increasing the bandwidth by 14% to 0.8Rb will also lead to an increased noise
power of 14% while signal power is only increased by 2%. If the Q was 7 for a system
with f-3dB=0.7Rb, which corresponds to a BER of 10-12, and assuming the noise is
Gaussian, then the Q for the system with f-3dB=0.8Rb is given by
Q f−3dB = 0.8Rb=
1.021.14
•Qf−3dB = 0.7Rb
= 6.26 (2.15)
that corresponds to a BER of 10-10, which indicates the 14% increase in
bandwidth only leads to a lower BER by a factor of 100.
27
Table 2.2 Cumulative power spectrum of NRZ signal
f/Rb Cumulative power of NRZ signal
0.5 81.4%
0.6 86.9%
0.7 92.0%
0.8 94.3%
0.9 95.0%
1.0 95.1%
1.2 95.5%
1.4 97.1%
1.6 98.9%
28
CHAPTER III
DESIGN OF OPTICAL PREAMPLIFIER CIRCUIT
3.1 Introduction
As demand for the use of optics in computing increases, the integration of
optoelectronic devices, interface circuitry, and other digital VLSI circuits is gaining more
attention as a mean of implementing systems that can perform highly complex processing
tasks. In most optical-to-electrical interface circuits, the frontend of the receiver consists
of a PD and a preamplifier, and this frontend traditionally has been provided by III-V
compound semiconductor technologies. However, the low-level of integration with other
digital ICs limits the sustainability of end products for short-distance applications. On the
other hand, their CMOS counter-parts have not shown enough performance to survive in
such a noisy environment without sacrificing other important attributes. Their
shortcomings are mainly because of the nature of silicon CMOS devices, which can be
integrated seamlessly with other digital circuitry but nevertheless have limited gain,
limited bandwidth, and large parasitic capacitances.
29
In this research, various aspects that affect the performance of the optical frontend
are investigated, and a wideband differential CMOS preamplifier has been designed.
Issues that arise from the submicron CMOS technologies, such as low substrate
resistance, high junction capacitance, low transconductance, and low supply voltage, are
considered and carefully addressed in the design phase.
Figure 3.1 depicts a block diagram of the designed preamplifier, which is
composed of a transimpedance stage with a single-loop resistive feedback, a post-
amplifier, and a 50Ω driving buffer. The goal of the research for this dissertation was a
high-speed hybrid optical frontend for short-reach optical links, which limits the target
distance allowes lowering of requirements for preamplifier gain and noise because a lot
more optical power is available at the input. The circuit was realized using TSMC
0.18µm CMOS technology, and an optimized inverted MSM (I-MSM) PD has been post-
integrated on the chip to measure the overall optical frontend performance.
+ -
+-
+ -
+-
+ -
+-
TIA Post-Amplifier Buffer
PD
Figure 3.1 Block Diagram of Optical Frontend
30
3.2 Transimpedance Stage
In designing an optical receiver frontend, two major factors must be considered.
These are the bandwidth of an amplifier and the input sensitivity. The bandwidth of the
whole optical receiver is usually determined at the first stage, and it can be estimated by
its RC time constant contributed by PD stray capacitance and electrical amplifier input
resistance and parasitic capacitance. The noise that affects the sensitivity is primarily
related to the preamplifier input impedance. Hence it is crucial to choose the appropriate
circuit topology that gives an optimal trade-off between bandwidth and input signal
sensitivity for given system requirements.
3.2.1 Principal Preamplifier Topologies
Three widely used configurations for optical frontend circuits are the high input-
impedance open-loop, the low input-impedance open-loop, and the transimpedance
feedback loop. The architectures of all three are based on the value of impedance seen at
the input and the existence of a feedback loop within the circuit. Each of them exhibits
different characteristics, and their pros and cons allow circuit designers to choose one that
is best suited for a specific application.
31
3.2.1.1 High Impedance Open-loop Preamplifier
A large signal swing can be obtained by using a large load resistor RIN, and a high
input-impedance preamplifier, as illustrated in Figure 3.2, is one of the candidates for use
in an optical receiver front-end. It is also referred to as an integrating preamplifier
because, when the RIN is large, the input admittance is dominated by the shunt
capacitance in parallel, and the signal tends to be integrated by this capacitance.
CT RINIIN
RD
M
VOUT
Figure 3.2 Integrating preamplifier
Neglecting channel-length modulation and body effects for simplicity, the
transimpedance gain of the circuit is equal to
32
ZT = gmRDRIN
1+ sRINCT
(3.1)
where CT is the total input capacitance including a PD capacitance CPD, a parasitic
capacitance CPARA, and an amplifier input capacitance CG, i.e.
GPARAPDT CCCC ++= (3.2)
As expected, the main drawback is its low achievable bandwidth given by
TINdB CR
13 =−ω (3.3)
while the large RIN may help to reduce the input-referred noise current
In,IN2 =
In,M2 + In,RD
2
gm2 RIN
2
+=
DmmIN RggRKT
22
14 γ (3.4)
For a high-impedance frontend, an equalizer usually follows to restore the output
pulse shape, which is distorted by the limited bandwidth of the preamplifier, by way of
attenuating low frequency components of the signal [12].
33
3.2.1.2 Low Impedance Open-Loop Preamplifier
To alleviate the limited bandwidth caused by the large RC time constant at the
input, the amplifier shown in Figure 3.3 employs the common-gate topology that has low
input resistance.
RD
CTIIN
M1
M2VG2
VG1
VOUT
Figure 3.3 Common-gate preamplifier
Since the current gain of the common-gate amplifier is unity for, the transfer
function is given by
ZT =RD
1+ s CT
RIN
(3.5)
34
where
211
11
dsdsm
DdsIN ggg
RgR++
+= (3.6)
Usually, ( gds1 + gds2 ) is small compared to gm1, and
1
1
mIN g
R ≈ (3.7)
However, the gds term becomes larger in submicron CMOS devices and increases the RIN.
The input-referred noise current can be obtained by computing the output noise
and dividing it by the mid-frequency transimpedance gain RD. By neglecting the flicker
noise effect because the amplifier bandwidth of interest is much greater than the typical
flicker noise corner frequencies, the output noise is
Vn,OUT2 = In,M 2
2 + In,RD
2( )RD2 (3.8)
yielding the input-referred noise current of
In,IN2 = In,M 2
2 + In,RD
2( )
+=
Dm R
gKT 14 2γ (3.9)
As shown in the above equation, the noise currents of M2 and RD, however, are
directly referred to the input with a unity factor, which makes the common-gate
architecture unsuitable for low-noise applications. Hence this topology is often used in
conjunction with a resistive feedback [13-14] that is discussed in the following sections.
However, the tight trade-off between noise and bandwidth still leaves very little
flexibility in design, especially when the limited voltage headroom of submicron CMOS
technologies is considered.
35
3.2.1.3 Transimpedance Feedback Preamplifier
The shunt feedback amplifier, which is basically a current-to-voltage converter
with a negative resistive feedback, is the most commonly employed circuit topology for
preamplifiers in optical fiber applications. This architecture is typically chosen because it
provides a large bandwidth by synthesizing a small input-impedance while maintaining a
large resistor value in the feedback path to improve noise behavior [15-16].
The first implementation depicted in Figure 3.4 employs a source follower in the
core to alleviate the loading effect of RD [17-19]. Assuming the source follower has a
unity voltage gain, the transimpedance gain and the bandwidth are given by
ZT = −gmRDRF
1+ gmRD
1
1+ s RFCT
1+ gmRD
(3.10)
and
TF
DmdB CR
Rg+=−
13ω (3.11)
To obtain the input-referred current noise of the above circuit, the noise that arises
from the core amplifier needs to be calculated first. If the input noise of the core amplifier
is expressed as
21
2,,2
,,m
coreINncoreINn g
VV =
= 1gm1
2 In,M 12 + In,RD
2( )RD2 +
In,M 22
gm 22
(3.12)
then the input-referred current noise is given by
36
In,IN2 =
1RF
2 Vn,RF
2 + Vn,IN ,core2( )
222
21
221
21
4444
DFmmDFmFmF RRggKT
RRgKT
RgKT
RKT γγ
+++= (3.13)
RD
CTIIN
M1
VOUT
RF
I BIAS
M2
Figure 3.4 Two-stage feedback preamplifier
The main drawback, however, is the large voltage headroom consumption
because the voltage across RD is limited to VDD-VGS2-VGS1 (no voltage drop occurs in RF
because no DC current flows through it). In addition, CMOS source followers suffer from
poor drive capability compared with those using other device technologies [20-21].
37
Figure 3.5 shows another popular configuration that eliminates the source
follower so as to circumvent the limitations mentioned above, and the frequency response
is given by
dB
Dm
DFmT sRg
RRgZ
3
1
11
)1(
−
++−
−=
ω
(3.14)
where
TDF
DmdB CRR
Rg)(
13 +
+=−ω (3.15)
RD
CTIIN
M
VOUT
RF
Figure 3.5 Single stage feedback preamplifier
38
Again, using the same method applied to the above topology, the input-referred
current noise can be written as
In,in2 =
Vn,IN2
RF2
2
2,,
2,
F
coreINnRn
RVV
F+
=
2
2
2,
2,2
,
F
m
RnMnRn
Rg
IIV D
F
++
=
DFmFmF RRg
KTRg
KTRKT
222
444++=
γ (3.16)
By comparing Equations (3.10), (3.11), (3.14), and (3.15), it can be observed that
both have approximately the same transimpedance gain, but the bandwidth is slightly
lower in the second configuration. However, a wide transistor, which only comes at the
cost of large capacitance, is necessary for the source follower when short-channel devices
are used. Hence, by getting rid of it, the single-stage feedback configuration is expected
to have improved noise performance at high frequencies [22, 71].
39
3.2.2 Differential Topology
Single-ended architectures, despite the advantages of high-gain, high-bandwidth,
and low-power consumption, are not suitable because they are very susceptible to supply
noise and plagued by stability problems stemming from parasitic feedback paths. A large
substrate cross-talk noise, when integrated with other digital circuitry, also may
significantly deteriorate the performance of a receiver, especially when using a low-level
input signal under low-supply voltage in the submicron CMOS [57, 69].
The primary methods used to alleviate the large supply noise present in a mixed
digital and analog circuit environment are to keep the sensitive analog parts away from
the noisy digital parts, or to block the noise transmission from the digital circuitry. Thus,
in addition to careful layouts including separate power supply lines, shields, and epitaxial
layers underneath the transistors, differential circuit architectures are inevitable in
designing optical receiver systems that are susceptible to substrate noise.
Differential receiver designs attempt to remove noise from their inputs by using
parallel signal paths. The identical paths with a 180-degree phase difference in
differential circuits are to pick up the same noises that will be subtracted during
amplification processes, and the basic idea can be explained using simple common source
amplifiers as depicted in Figure 3.6.
40
Figure 3.6 Small signal models of single-ended (top) and differential amplifier (bottom) including power supply inductances
Assuming the differential amplifier has a good common mode rejection property,
its voltage gain is given by
Av,S = gmR (3.17)
41
and will remain constant over the frequency of interest. However, the effective
transconductance and the output impedance of the single-ended amplifier are
Gm =gm
1+ sLgm
(3.18)
and
Z = R + sL (3.19)
respectively, resulting in a gain of
Av,D = GmZ =gm
1+ sLgm
• (R + sL) (3.20)
because it doesn’t have the complementary pair to share the same virtual ground. Hence
when a binary coded bit stream that contains all frequency components is received at the
input, its output will be distorted because the amplifier gain is not uniform for all
frequencies.
42
3.2.3 Co-Design of Frontend
Various solutions to the high-speed optical PHY circuits have been demonstrated
in GaAs- and InP-based technologies to deliver the required performance, but the low-
level of integration with other digital ICs typically limits the sustainability of the end
product for short-reach applications. In addition, to replace copper solutions, an optical
solution must be able to show comparable low power consumption and low
manufacturing cost. Meanwhile, over the past 30 years, aggressive scaling has improved
the intrinsic speed of CMOS devices by more than three orders of magnitude, and the
current generation CMOS exhibits not only cost effectiveness but also sufficient
performance for high-speed applications [37-39].
Although silicon monolithic receivers [40-42] are best suited for low-cost
applications, the low absorption coefficient of the silicon usually leads to a low quantum
efficiency-bandwidth product. Several approaches to circumvent this trade-off have been
reported [43-48]; however, compatibility issues still exist with the standard CMOS
process, and lightwave systems operating in the 1.3~1.6µm wavelength range necessitate
InP-based PDs.
43
3.2.3.1 Quantum Efficiency and Bandwidth
The benefits of the hybrid integration of optical devices and CMOS circuits stem
from the possible co-optimization of individual components that make up the optical
frontend. This potential co-optimization would give which gives more flexibility in
design. The first advantage would be a higher achievable quantum efficiency-bandwidth
product. As described in the previous section, a PD is used as the input device in any
direct-detection optical receiver system, and the switching speed of the PD can be
characterized as a trade-off between two factors. First, the finite transit time of electrons
and holes through the depletion region limit the rate at which the current can vary in
response to light. The second factor limiting speed arises from the parasitic capacitance
of the PD, which greatly affects the design of preamplifier circuits [5-6, 10].
ω −3dB =1
(RC )2 +(τ transit )2 (3.21)
As the above equation indicates, the same switching speed may comes from various PDs
having different physical structures (or properties) – There can be a range of PDs that
have the same bandwidth but have different combinations of RC time constants and
transit times. In the case of MSM PDs, devices optimized for small capacitance by
widening the space between electrodes may deliver the limited bandwidth because of the
slow drift transport and collection of carriers that result in a tail in the frequency
response. Reducing the absorption layer improves the transit time by minimizing low
electric field regions, but this faster transit time comes at the cost of low responsivity [52-
54].
44
However, the overall bandwidth of the front-end is mainly determined by the total
input capacitances, and only a small portion of these input capacitances comes from the
PD. Assuming the gate capacitance CG of the preamplifier is greater than or equal to CP (
= CPARA + CPD ), it can be seen from the Equation (3.2) that a little increase in CPD does
not significantly degrade frontend speed. For example, if the PD is made to have 50%
more capacitance but 50% better responsivity as well, the quantum efficiency-bandwidth
product will be increased by at least 20%. Therefore, it can be assumed that an optimal
point exists, and that allowing a slightly larger capacitance margin at the preamplifier
input can lead to a higher optical-to-electrical conversion gain for a given bandwidth.
45
3.2.3.2 Optimized Sensitivity
Another advantage could be improvement in sensitivity. The PD displays
relatively low noise, making the subsequent preamplifier the major noise contributor.
Therefore, it has been suggested that the greatest sensitivity can be obtained when the
capacitance of a preamplifier input transistor is equal to that of the sum of a PD and other
parasitics [12], i.e.,
CG = CPD + CPARA = CP (3.22)
Therefore, the optimal point can also be explained in terms of the lowered input-referred
current noise, which is expressed as
In,IN2 =
Vn,RF
2 + Vn,A2 (1+ ω 2RF
2CT2)
RF2
++=
m
TF
mFF gCRf
gRKT
RKT 2222
2
)2(144 πγ (3.23)
if the dominant noise contribution of the amplifier is from the input transistor as depicted
in Figure 3.7.
For a given bandwidth fC, a large gm typically leads to a large CG requiring a small
RF, while the opposite situation allows a large RF. Hence CG = CP is considered as the
cross point because low noise is achieved by the large gm and RF [10, 21, 23, 55].
46
2, FRnV
2,AnV
Figure 3.7 Simplified schematic of optical frontend with noise sources.
However, the major drawbacks of CMOS technologies is low transconductance
and the lack of semi-insulated substrates, which are available in III-V semiconductor
devices, resulting in somewhat higher parasitic capacitances [22, 25]. In other words, to
obtain a reasonable gain, the CG in CMOS, which is proportional to gm, usually becomes
inevitably larger compared to CP. Hence the unmatched capacitances at the input will
lead to lower sensitivity, and this issue is further emphasized by the low supply voltage
used in submicron CMOS technologies. By reanalyzing the different aspects of the
previous study [56], however, the noise problem can be alleviated by using a capacitance-
optimized PD for the preamplifier circuit.
47
By integrating the Equation (3.23) over the noise bandwidth that is almost equal
to that of the preamplifier when multiple poles present in practice [21], the total
integrated input-referred current noise is given by
In,IN ,TOTAL2 = (4KT)(2π ) fCCT
A+
fCγCT2
fTCG A2 +f 2γCT
2
fTCG
0
fC∫ df
++=
GT
TC
GT
TTC Cf
CfACf
CA
CfKT3
)2)(4(2
2
22 γγπ (3.24)
where
)(2 PGF
C CCRAf
+=
π (3.25)
=
G
mT C
gfπ21 (3.26)
Normalizing CG with CP and rearranging Equation (3.24) yields
+
+
+= 1)1(
3)4(2
,,N
N
TT
C
F
CTOTALINn C
CAff
AfRfKTI γγ (3.27)
From the equation, for a fixed bandwidth fC and an amplifier gain A, the value of
feedback resistor RF is inversely proportional to the total input capacitance, i.e.,
RF ∝1
(CN +1)CP
(3.28)
and Equation (3.27) can be written as the function of CN and CP.
++
+Γ∝ )1()1( 2
2,, N
N
NPTOTALINn C
CCCI (3.29)
Figure 3.8 plots the normalized RMS input-referred current noise based on the
above equations. Keeping in mind that horizontal lines indicate the same amount of
noise, it can be observed that compensation for this noise behavior can be achieved by
48
optimizing the capacitance of the PD as long as this increased capacitance does not
severely affect bandwidth.
Figure 3.8 Plot of normalized RMS noise vs. normalized input capacitance
49
3.2.4 Transimpedance Amplifier Design
As mentioned in the previous section, a common-gate configuration is typically
chosen when low input-impedance is important because it can tolerate a wide range of
PD capacitance. However shunt feedback architecture, which has better noise behavior, is
much more attractive in such a case that PD models are readily available. The basic form
of a transimpedance feedback configuration can be realized with a conventional OP-Amp
with a negative feedback resistor as shown in Figure 3.9.
Figure 3.9 Transimpedance feedback amplifier using OP-Amp
In operation, the currents generated by the PD forms the OP-Amp input resulting
in the negative output voltage. However, although it can achieve large enough
transimpedance gain of
50
ZT ≈ −Rf (3.30)
because of the large voltage gain of the OP-Amp, the operating speed has usually been
limited by the OP-Amp because of the long propagation delay within the feedback loop.
The design employs a single-stage common source amplifier with an active
feedback. The advantage of active feedback implementation is that the resistance value
can be controlled by applying variable external voltage to the transistor gate. Because its
value is dependent upon the applied gate voltage, it lends itself to a possible solution that
would exist with an optimal resistance value that balances the best sensitivity with the
highest bandwidth. This configuration may carry the risk of instability because its phase
difference is 180° out of feedback loop delay; minimizing this risk requires careful
selection of the right size of transistor in the design phase.
In general, bandwidth can be extended in two ways: Decreasing the feedback
resistor value at a cost of the noise, or by increasing the intrinsic gain of the core
amplifier. Hence a large transconductance is preferable not only to maximize the gain but
also to lower the noise while maintaining a reasonable bandwidth [22]. A diode-
connected NMOS is usually considered for a load because it makes the amplifier less
sensitive to the process variation because the gain is determined by the width ratio of the
input and load transistors. However, in submicron CMOS processes, the large voltage
drop across the NMOS load becomes problematic. Gate-source capacitance, which is
three to four times larger than gate-drain capacitance in the saturation mode, appears at
the output node and may also significantly influence both noise behavior and bandwidth
[27].
51
As shown in Figure 3.10, the transimpedance stage employs PMOS loads
operating in the triode region. Because the PMOS load allows the output signal to swing
up to VDD because the VGD of the input transistor is almost zero, and transconductance
could be maximized with the least compromise of the feedback resistor value. Also, the
differential scheme as well as a symmetric circuit layout plays an important role in
enhancing the overall noise performance by providing a better common mode rejection
ratio.
Figure 3.10 Transimpedance Stage
52
3.3 Post-Amplifier and Output Buffer
A large-value feedback resistor may be preferred for good sensitivity, but the
integration of the signal because of the input capacitance will follow because in practice
the open-loop gain cannot be increased indefinitely. Cascading amplifiers within the
feedback loop may also lead to additional phase-shift, which likely causes ringing or
instability problems [23]. Hence the voltage swing produced by preamplifiers at the
minimum light intensity is usually less than adequate to be further processed in the
following stages. These issues are more prominent in CMOS technologies in which the
supply voltage and transconductance are typically limited [24-25].
The noise contribution from the later stage is negligible compared with that from
the first transimpedance stage, and differential voltage-mode amplifiers are good
candidates for post amplification. The fact that, unlike the first stage, the post amplifier
and the output buffer can receive balanced input signals is another advantage because
ideal tail current sources used in differential pairs do not exist in practice. Hence the
primary reason for post amplification and buffering is to boost the output signal swing of
the TIA to an acceptable level so that it can be detected by an LA without adding a
considerable amount of noise.
53
3.3.1 Cascaded Amplifier
A cascade of n identical gain cells is one of the widely used methods to build a
high-speed amplifier especially when one cannot achieve an enough gain from a single-
stage amplifier. The overall gain of the n-staged amplifier is given by
Atotal = Acelln (3.31)
where the overall bandwidth is
BWtotal = BWcelln 21/ n −1 (3.32)
For example, if the total bandwidth of the amplifier is required to have 10GHz, then the
bandwidth of each cell must exceed 20GHz for n = 3, and 26GHz for n = 5.
Table 3.1 and 3.2 illustrates the required cell bandwidth and gain for a cascade of
n. The gain-bandwidth requirement of each cell varies with the target bandwidth and the
gain of the cascaded amplifier, and it can be observed that n = 4 is the optimum value for
the above tabulated case. However, another critical issue that cannot be ignored is the
relationship between n and the overall input-referred noise. In other words, it is also
desirable to have as few stages as possible because the noise accumulates rapidly as the
gain per stage lowers.
54
Table 3.1 Required cell bandwidth for n-cascaded amplifier
Cell Bandwidth (GHz) needed for Total Bandwidth of # of Stage
8.0 9.0 10.0
1 8.0 9.0 10.0
2 12.4 14.0 15.5
3 15.7 17.7 19.6
4 18.4 20.7 23.0
5 20.7 23.3 25.9
6 22.9 25.7 28.6
Table 3.2 Required cell gain for n-cascaded amplifier
Cell Gain needed for Total Gain of # of Stage
8.0 9.0 10.0
1 8.0 9.0 10.0
2 2.8 3.0 3.2
3 2.0 2.1 2.2
4 1.7 1.7 1.8
5 1.5 1.6 1.6
6 1.4 1.4 1.5
55
3.3.2 Bandwidth Enhancement
A post differential amplifier with a voltage gain of 10 and a cutoff frequency
exceeding 10GHz was required to avoid the ISI resulting from a limited bandwidth. In
addition, the trade-off between low noise and wide bandwidth still exists, and the number
of cascaded stages needs to be kept to a minimum. However, it was impossible to realize
such an amplifier with ordinary cascaded differential pairs, and techniques to improve the
bandwidth without compromising other important factors were necessary.
One of the most effective methods to enhance bandwidth is to increase the gain
near the cutoff frequency of the amplifier. This gain can be realized by transforming the
frequency response of the amplifier from the first order transfer function to the second
order form. In general, the transformed amplifier will exhibit complex-conjugate poles
exhibits, and the bandwidth will be extended by 30~40% without sacrificing low
frequency gain.
56
3.3.2.1 Cherry-Hooper Amplifier
In order to achieve more gain for a given bandwidth, it is possible to interpose
source followers between the cascade amplifiers to isolate the output node from the input
capacitance of the latter stage [28]. However, the source follower usually consumes
substantial voltage headroom, limiting the transconductance of the input transistor in the
subsequent stage [20-21]. The follower may also severely attenuate the signal if channel
length-modulation and body effects are significant.
The Cherry-Hooper amplifier [29-30] depicted in Figure 3.11 incorporates local
feedback in the drain network to improve speed. The transistor M1 acts as a
transconductance stage and the transistor M2 together with the feedback resistor RF acts
as a transimpedance stage, producing a combined voltage gain of
Fmm
mFm
IN
OUT RgggRg
VV
12
11 ≈−= (3.33)
if RF>>1/gm2.
The overall frequency response of the amplifier is given by
22121
221
)()1(
mF
Fmm
IN
OUT
gCCsCCRsRgg
VV
+++−
= (3.34)
and if for simplicity two poles are assumed to be equal,
212
221
4)(
CCgCCR
mF
+= (3.35)
thereby
ω1 = ω2 =2gm2
C1 + C2
(3.36)
57
C1
M2
VOUT
RF
M1
C2
VIN
I BIAS
Figure 3.11 Cherry-Hooper amplifer
The above equation shows that pole frequencies are determined by gm2 and by the
average value of capacitances at nodes 1 and 2, where average values are expected to be
much higher than those without feedback, e.g., 1/(RC). In general, by yielding only high
frequency poles, this topology is able to provide wide bandwidth without sacrificing
much gain.
58
3.3.2.2 Capacitive Peaking
This technique uses a gain peaking effect of the frequency response by carefully
controlling the capacitance CL loaded at the output node of a preamplifier, thereby
increasing the bandwidth [31-32].
By reanalyzing the feedback preamplifier circuit with the total output capacitance
CL attached, as shown in Figure 3.12, Equation (3.14) can be rewritten in a second-order
transfer function form as follows:
ZT =ZT 0ω0
2
s2 +ω0
Qs + ω0
2 (3.37)
21
21
ωωωω
+=Q (3.38)
210 ωωω = (3.39)
and
ω1 =1
RINCT
(3.40)
LOUT CR
12 =ω (3.41)
In general, the value of Q ranges from 1/2 to 5/6, which corresponds to the 0-10%
overshoot, for many practical applications for broadening the bandwidth [27]. The
maximally flat gain curve (Butterworth response) is obtained at Q=0.707.
59
CT
M
VOUT
RF
CL
RD
IIN
VOUT
Figure 3.12 Capacitive peaking
The bandwidth of the preamplifier can be estimated by setting the magnitude of
Equation (3.37) to 0.707 times its low frequency gain ZT0. That is,
ZT 0ω02
−ω−3dB2 + j 2ω0ω−3dB + ω0
2 =12
ZT 0 (3.42)
thereby
ω−3dB = ω0 (3.43)
which is always greater than the original first-order topology. Thus, once the amount of
the required gain peaking (Q) is determined, the capacitance CL could be easily estimated
by Equation (3.38), (3.39), and (3.40).
60
3.3.2.3 Source Degeneration
Another way to broaden the frequency response is to degenerate the input
transistors, as shown in Figure 3.13, so that their effective transconductance Gm increases
at the high frequency to compensate for the reduced gain beyond the cutoff frequency
[21-22, 30].
CGS
M
VOUT
CL
RD
VIN
CSRS
RG
Figure 3.13 Source degeneration
The capacitor CS is to bypass the degeneration resistor RS at high frequencies,
providing the peaking behavior that extends the bandwidth. The RG represents the output
61
resistance of the preceding stage. Neglecting the body effect, the equivalent transfer
function is given by
LD
Dm
IN
OUT
CsRR
GV
V+
=1
=gm (1+ sRSCS )
s2RGCGSRSCS + s(RGCGS + RSCS + RSCGS ) + (1+ gmRS )
RD
1+ sRDCL
(3.44)
If the zero at 1/(RS/CS) cancels out the output pole 1/(RDCL) at the drain, then
VOUT
VIN
=gmRD
s2RGCGSRSCS + s(RGCGS + RSCS + RSCGS ) + (1+ gmRS ) (3.45)
Assuming the low frequency pole ω 1 is much close to the origin, it can be also shown
that
ω1 ≈1+ gmRS
RGCGS + RSCS + RSCGS
≈1+ gmRS
RSCS
(3.46)
if RLCGS >> RS(CS+CGS). Hence the input pole frequency is increased by a factor of
(1+gmRS) implying that the load impedance seen by the preceding stage is reduced. This
has an advantage over a direct trade-off of a gain-bandwidth product without
degeneration.
62
3.3.2.4 Inductive Peaking
The idea of inductive peaking is to use the capacitive load, which usually limits
bandwidth, to resonate with an inductor, thus increasing speed without additional power
dissipation or loss of gain [9]. At the output node, shunt-peaking [27, 33-35] can be
realized by placing the inductor in series with the load resistor of an amplifier as shown
in Figure 3.14.
M
VOUT
C
R
VIN
L
Figure 3.14 Shunt-peaking
The transfer function for the shunt-peaking circuit is given by
VOUT
VIN
= −gmsL + R
s2LC + sRC +1
63
Qs
Qs
Qs
Rgm 020
02
0
ωω
ω
ω
++
+−= (3.47)
where
Q =1R
LC
(3.48)
LC1
0 =ω (3.49)
Equation (3.47) can be interpreted as a combination of a low-pass function and a
band-pass function. The zero is primarily responsible for the bandwidth enhancement in
this case, and the circuit experiences more overshoot than other second-order
configurations mentioned in the previous sections. For the value of Q=0.64, it has the
maximally flat response, and the bandwidth is improved by 72%.
A bond-wire is also sometimes deliberately interposed at the input of the
preamplifier, as depicted in Figure 3.15, to achieve the so-called series peaking [36]. The
frequency response of the overall system is given by
ZT =ZT 0ω0
2
s2 +ω0
Qs + ω0
2 (3.50)
where
PD
WIRE
F CL
RAQ )1( +
= (3.51)
WIREPD LC
10 =ω (3.52)
At Q=0.707, the bandwidth is extended by 41% with an overshoot of 4.3%.
64
Figure 3.15 Series-peaking
The use of bond-wires as shunt-peaking inductors, however, is constrained by the
bonding pad capacitances, a limited range of realizable inductances, and large variations
between them. Hence on-chip spiral inductors, despite their consumption of large
amounts of space on the chip, are more suitable for differential circuit architectures.
65
3.3.3 Post-Amplifier Design
The goal of a designed post-amplifier composed of cascaded differential
amplifiers is to boost a signal swing that could not be obtained sufficiently in the
transimpedance stage. A two-stage cascaded amplifier has been chosen to minimize the
noise, and the transistor level detail is shown in Figure 3.16. The biasing at the input of
one stage is provided by the previous stage because AC coupling between stages cannot
be used because of the wide-band nature of the application.
Figure 3.16 Post amplifying stage
66
The difficulties lie in the fact that these gain cells also function as a pre-driver of
the following 50Ω buffer that has wide transistors. Hence large transconductance with a
small load (gain-bandwidth trade-off) was needed because the opposite combination may
increase the time constant at the output node. Either a large tail current or a wide input
transistor can be used to ensure sufficient transconductance. In general, however, as the
tail current increases, the voltage across the load increases, and the minimum voltage at
the common source node of the 50Ω buffer fails, eventually driving the current source
into the triode region. These issues become increasingly more difficult as the supply
voltage scales down.
The trade-off between the gain, speed and voltage headroom has been be
alleviated by shunt-peaking because, unlike other configurations such as Gilbert gain
cells, the inductor in series with the load resistor does not result in any additional voltage
drop or increased power consumption.
On-chip spiral inductors were employed. Although an active inductor [21, 33-34,
58], which is configured with a transistor operating in the saturation mode and a resistor
connected at the gate, occupies only a small area, the major drawback is the need of an
additional power supply line. The higher voltage ( > VDD ) is required to maximize the
transconductance, which is directly related to the quality factor, without introducing
substantial parasitic capacitances while avoiding additional voltage headroom
consumption.
A simultaneous optimization of on-chip inductors and other active components
was run in the simulator to obtain an improvement in bandwidth and voltage gain while
minimizing overshoot. The power supply lines are separated from the previous stage so
67
that amplified output signals are not fed back throuogh them into the sensitive input
stage.
68
3.3.4 Output Buffer Design
To drive external loads associated with equipment such as the oscilloscope and
the BER tester including pad capacitances, the post-amplifier is followed by a differential
output buffer. However, because of the wide input transistor of the output stage, the
overall amplifier may experience a speed bottleneck. So, this stage is to drive the big
output stage that in turn drives the pad, which has large capacitance.
The gain of the designed buffer is almost unity, and it employs a slightly modified
Cherry-Hooper architecture as shown in Figure 3.17. PMOS loads at the
transconductance stage are added to alleviate the voltage headroom problem by providing
part of the bias current to input differential pairs. The inherently low output-impedance
also helps delivering signals to external 50Ω loads efficiently.
69
Figure 3.17 Output buffer
70
CHAPTER IV
SIMULATIONS, LAYOUT, AND MEASUREMENTS
4.1 Simulations
4.1.1 HPADS Simulation
The HPADS simulation on the designed amplifier has been performed using
TSMC 0.18µm mixed-signal CMOS models provided by Agilent Technology. The
primary reason for these simulations were to optimize transistor sizes while varying other
parameters such as PD input capacitances, circuit biases, and transistor corner models.
One drawback of the models provided was that they do not include parameters for the
simulator to calculate device junction capacitances according to the width of transistors.
Hence the worst-case scenario was assumed, and fixed formula to calculate those values
was used even if stacked transistors share their drain or source regions with each other to
reduce parasitic capacitances.
71
S-parameters of the preamplifier were obtained in the HPADS simulation, then
they were converted to Z-parameters because a transimpedance gain can be expressed in
terms of Z-parameters.
L
T
ZZ
ZZ22
21
1+= (4.1)
Figures 4.1 to 4.3 show S21 and transimpedance gain curves over frequencies with
various input capacitances, i.e. 20fF (solid), 100fF (dash), and 200fF (dot) for three
transistor corner models. Top traces show S21 curves, and bottom traces are
transimpedance gains obtained using Equation (4.1).
Figure 4.1 Transimpedance gain curve using slow transistor corner model
72
Figure 4.2 Transimpedance gain curve using typical transistor corner model
Figure 4.3 Transimpedance gain curve using typical transistor corner model
73
4.1.2 HSPICE Transient Simulation
The HSPICE simulation has been run using TSMC 0.18µm mixed-signal CMOS
models provided by MOSIS service. SPICE netlists were extracted from the circuit layout
and include line capacitances. Figures 4.4 to 4.9 are transient responses of the
preamplifier at speeds of 5 and 10Gbit/s, while different combinations of PD
capacitances (20fF and 200fF), input currents (10µApp and 50µApp), and transistor
corner models were used. In each chart, traces from top to bottom represent a simulated
output eye-diagram assuming 20fF PD capacitance with 10µApp input, 20fF with
50µApp, 200fF with 10µApp, and 200fF with 50µApp, respectively.
As shown in the simulation results, the total input capacitance is the primary
factor that determines the overall bandwidth, and the input signal magnitude affects the
vertical size of the eye-diagram – the bigger input current and the smaller capacitance
results in outputs with faster rising and falling time constants.
74
Figure 4.4 Simulated eye-diagram using slow corner model operating at 5Gbit/s
75
Figure 4.5 Simulated eye-diagram using typical corner model operating at 5Gbit/s
76
Figure 4.6 Simulated eye-diagram using fast corner model operating at 5Gbit/s
77
Figure 4.7 Simulated eye-diagram using slow corner model operating at 10Gbit/s
78
Figure 4.8 Simulated eye-diagram using typical corner model operating at 10Gbit/s
79
Figure 4.9 Simulated eye-diagram using fast corner model operating at 10Gbit/s
80
4.13 AC & Noise Analysis
HSPICE AC sweep simulations were also run to plot common-mode rejection
ratio curves and input-referred noise currents. First, Figure 4.10 represents CMRR curves
of the preamplifier circuit using slow, typical, and fast transistor corner models,
respectively. The middle curve shows the best CMRR because the circuit was optimized
with the typical transistor process model.
Figure 4.10 CMRR curves of circuit using slow, typical, and fast corner model
81
Figures 4.11 to 4.13 illustrate noise simulation results of the preamplifier circuit
for each process corner models. In each noise chart, the top two traces represent an output
noise and the RMS input-referred noise assuming 20fF PD capacitance, while the two
traces at the bottom are the results using 200fF capacitance. The following equation has
been used to calculate the input referred noise
In,IN ,rms =output _ noise( )2∫
Low _ frequency _Gain (4.2)
Based on the noise simulation results, the RMS input-referred current noise of
In,IN ,rms =1.7µA has been obtained. In addition, assuming PD responsivity ρ = 0.25 A/W,
the extinction ratio re >> 10 dB, and the target BER = 10-12 (Q=7), a theoretical
sensitivity can also be calculated and is given by
Sensitivity =10log In,IN ,rms(Q)ρ
re +1re −1
1000
dBm ≈ −13.2dBm (4.3)
82
Figure 4.11 Noise simulation result using slow transistor corner model
83
Figure 4.12 Noise simulation result using typical transistor corner model
84
Figure 4.13 Noise simulation result using fast transistor corner model
85
4.1.4 Packaging Effect Simulation
Packaging inductance can play a major role in degrading the quality of the
amplifier output signal, thus successful optical frontend design demands careful attention
to the sources and effects of parasitic inductance due to bond wires, die pads, etc.
A simple yet effective way to suppress the finite line impedance effect is to place
decoupling capacitors between the power supply lines and the ground. In general, the
more decoupling capacitors the better the power is regulated by providing the circuit
enough charge until the switching noise settles down. However, because of the area
constraint in the physical layout in practice, the optimum size and placement of those
capacitors must be calculated. Hence a line impedance model including package bond
wires, PCB lines, and other biasing wires needs to be taken into consideration in the
design phase. The packaging parasitic and decoupling network models used in the
simulation are depicted in Figure 4.14.
Figure 4.14 Model of package line impedance
86
Because of the relatively large effective series inductance (ESL) and the effective
series resistance (ESR) associated with surface mount capacitors, they are placed on the
board to decouple the low frequencies. Since lower frequencies are not as affected by
inductance, the parts do not have to be optimized for low inductance, and they were
placed far from the chips. The higher frequencies are decoupled with on-chip capacitors
that have lower ESL and ESR.
Figure 4.15 illustrates the effect of line impedance when no decoupling capacitors
are placed internally or externally, and the effect can be observed in the transient
response and in the eye-diagram of the simulated output.
Figure 4.15 Transient response without power supply decoupling capacitors
87
On the other hand, the second simulation shown in Figure 4.16 indicates that the
decoupling capacitors can effectively regulate power supply lines by providing necessary
charges during switching and greatly improve the output signal quality.
Figure 4.16 Transient response with power supply decoupling capacitors
88
4.2 Layout
In the layout of the circuit, the power supply rails have been partitioned into two
halves to reduce unwanted parasitic feedback paths. The first half serves the first stage of
the amplifier that deals with very small signals, and the second half serves the later stages
including post amplifiers and the output buffer. This partitioning helps prevent the larger
output signal from propagating through power supply lines to the sensitive input parts
through power supply lines. Such propagation may eventually causes oscillation. In
addition, the floor plan keeps the input pads as far away from the other pads as possible
to prevent unwanted coupling between them. Input pads that will receive small input
currents generated by a PD were located in the far right, and output pads for the exiting
signals were placed in the far left.
As shown in the Figure 4.17, the area is dominated, as is typical in high frequency
ICs, by passive components such as spiral inductors and capacitors. Great importance
was accorded to the layout of each single stage as well, such as symmetric drawing of the
circuit because of its differential nature, thereby reducing common-mode noise and
systematic offset [59]. The unused input is also brought out to create partial symmetry at
the input to pick up the same noise that may occur.
89
Figure 4.17 Layout of preamplifier circuit
The PD integration site was placed as close to the input as possible to reduce
inductance, and five pads vertically arranged in both the input and the output serves as
coplanar ground-signal-ground-signal-ground (GSGSG) differential probe pads for
90
electrical signals in and out. Metal lines that interconnect transistors within and between
the amplifier stages are stacked to minimize parasitic line capacitance to the substrate.
Models of the package and of all bond-wires were incorporated in the design
phase, and large metal-insulator-metal (MIM) capacitors that provide a capacitance of
1fF/1µm2 were used for on-chip supply decoupling. These capacitors are of primary
importance to ensure a good AC ground at VDD because even the differential topology
introduces into the supply some transient currents that result from the finite capacitance
seen at the common-source node to ground. To help minimize ground bouncing, multiple
parallel pins assigned to ground are used, and the same was done for VDD pads.
91
4.3 Measurements
4.3.1 Measurement Setup
The circuit was fabricated using TSMC 0.18µm CMOS non-epi process. This n-
well CMOS process offers 1 poly and 6 metal layers as well as thick top metal for
inductors, an additional high resistive poly, and MIM capacitors. The chip photograph in
Figure 4.18 shows the active area (1500µm 1000µm) of the preamplifier circuit. A
MSM PD was post-integrated close to the input of the circuit to prevent parasitic
inductance and integrated upside down to improve the responsivity that may be degraded
by the reflection of metal contacts [70]. The I-MSM PD has 20µm diameter with 1µm
electrode width and spacing, and the estimated responsivity is 0.15A/W.
After integration, the chip was mounted and bonded right onto to the test board as
pictured in Figure 4.19. Based on the simulation results, surface mount chip capacitors
were also placed on the backside of the PCB for effective power supply line decoupling.
In operation, circuit biases were provided through those metal traces on the PCB while
output signals were transmitted through the GSGSG coplanar probe.
92
Figure 4.18 Photograph of preamplifier circuit with integrated I-MSM PD
Figure 4.19 Test board of integrated optical frontend circuit
93
Figure 4.20 illustrates the measurement setup with an optical input source.
Electrical signals generated by a BER tester (BERT) were fed into a modulator driver,
and its amplified output served as input to an electrical-to-optical modulator. Then,
continuous-wave (CW) lights from a distributed feedback (DFB) laser paired with a
thermo-electric cooler (TEC) were externally modulated by the Mach-Zehnder (MZ)
modulator, and the modulated lightwave was transmitted through a single-mode fiber and
coupled into the integrated PD.
Figure 4.20 Measurement setup diagram
94
4.3.2 Measurement Results
During measurements, circuit outputs were captured by an oscilloscope to see
eye-diagrams and also compared to the original electrical signals by the BERT. Output
eye-diagrams measured with a 27-1 pseudorandom bit stream signal at different input
powers and data speeds are shown in Figures 4.21 to 4.24.
Figure 4.21 Eye-diagram with 57µApp input photocurrent operating at 5Gbit/s
95
Figure 4.22 Eye-diagram with 113µApp input photocurrent operating at 5Gbit/s
Figure 4.23 Eye-diagram with 57µApp input photocurrent operating at 10Gbit/s
96
Figure 4.24 Eye-diagram with 113µApp input photocurrent operating at 10Gbit/s
For BER measurements, a commercial LA was attached because, when the optical
power was low, output swings from the frontend circuit were below the input sensitivity
of the BERT. An optical attenuator was used to reduce the input power while maintaining
stable operation of the optical source. It can be observed that the area of the opened eye,
the input power, and the operating speed clearly affect the BER. Figures 4.25 to 4.28
show output eye-diagrams with the LA, and Figure 4.29 plots the measured BER curve as
a function of equivalent input photocurrents.
97
Figure 4.25 Eye-diagram from LA with 57µApp input photocurrent at 5Gbit/s
Figure 4.26 Eye-diagram from LA with 113µApp input photocurrent at 5Gbit/s
98
Figure 4.27 Eye-diagram from LA with 57µApp input photocurrent at 10Gbit/s
Figure 4.28 Eye-diagram from LA with 113µApp input photocurrent at 10Gbit/s
99
Figure 4.29 Measured BER vs Input photocurrent
100
CHAPTER V
CONCLUSIONS
A high-speed CMOS preamplifier was designed and fabricated through TSMC
0.18µm mixed-signal non-epi CMOS technology, and a 20µm diameter InGaAs thin-film
I-MSM PD with a responsivity of 0.15A/W at a wavelength of 1550µm was post-
integrated onto the circuit.
The circuit uses a feedback architecture to meet the bandwidth-noise trade-off,
and high-speed circuit techniques were employed to overcome the limitations of CMOS
devices. Each stage including the first transimpedance stage has differential signal paths
for better noise immunity, and a balanced topology was also addressed in the layout.
Through recursive extractions of circuit netlists form the layout and simulations,
the circuit was optimized so that it can tolerate a wide range of fabrication process
variations. The finite line impedance effect resulting from the chip package was also
considered in the design phase, and an appropriate power supply decoupling network was
built into the chip and into the external test board.
101
For measurements, the chip was mounted onto a PCB, and output signals were
captured using a differential coplanar microwave probe. With optical inputs generated
from an externally modulated laser source, the test results indicate that the integrated
circuit can operate up to 10Gbit/s. Table 5.1 compares this work with other published
papers about CMOS preamplifiers.
Table 5.1 Performance comparison of CMOS preamplifiers
Author Publised
Year Speed
(Gbit/s) Tech. (um)
Input Source Sensitivity BER
Apsel [81] 2001 1 0.5 Optical - -
Haralabidis [83] 2000 1 0.8 Electrical - -
Ingels [84] 1999 1 0.7 Electrical 10µA -
Lee [26] 2002 1 0.25 Optical - -
Nakahara [88] 2001 1 0.5 Optical -28dBm 1.0E-09
Schow [40] 1999 1 0.6 Optical -9.3dBm 1.0E-09
Woodward [42] 1998 1 0.35 Optical -6.3dBm 1.0E-09
Zimmermann [41] 2001 1 1 Optical -15.4dBm 1.0E-09
Kim [35] 2003 1.25 0.25 Optical -17dBm 1.0E-12
Schrodinger [89] 2002 1.25 0.35 Optical -22.5dBm 1.0E-12
Yoon [28] 1997 1.25 0.8 Optical 30µA 1.0E-09
Schneider [90] 2004 1.25 0.12 Optical -28.2dBm 1.0E-10
Kuo [32] 2001 2 0.35 Electrical - -
Li [85] 2000 2 0.5 Optical -17.7dBm 1.0E-09
102
Chiang [82] 2003 2.1 0.35 Electrical - -
Mohan [27] 2000 2.1 0.5 Electrical - -
Chen [34] 2002 2.5 0.35 Electrical 16uA -
Madhaven [86] 2000 2.5 0.5 Electrical - -
Mitran [87] 2002 2.5 0.25 Electrical - -
Park [14] 2003 2.5 0.6 Electrical - -
Tanabe [22] 1998 2.5 0.15 Electrical 31µA -
Wang [18] 2001 2.5 0.35 Electrical - -
Beaudoin [49] 2002 5 0.18 Electrical - -
Tao [91] 2003 5 0.18 Optical - -
Csutak [44] 2002 8 0.13 Optical 2dBm 1.0E-9
Peterson [50] 2002 10 0.18 Optical - -
This Work 2004 10 0.18 Optical 28µA 1.0E-9
@ 5Gbit/s
Measured s-parameter data of photodetectors with various sizes and structures
were plugged into the simulator, and the circuit was co-optimized accordingly. After
fabrication, the heterogeneously integrated optical frontend achieved 28µA and 113µA
input sensitivity for the BER of 10-9 and 10-12 at 5Gbit/s, respectively. Under the same
measurement conditions, the circuit exhibited the overall transimpedance gain of more
than 60dBΩ while eye-diagrams were measured up to 10Gbit/s under the same
measurement conditions. There have been only a handful of papers published regarding
CMOS transimpedance amplifiers operating above 5Gbit/s, and to the best of the author’s
103
knowledge, this work is the first to report the integrated CMOS frontend with measured
input sensitivities and BERs in this realm.
104
APPENDIX I
SPICE NETLIST OF PREAMPLIFIER CIRCUIT
* extracted/netlist/TIA_TSMC.C.raw * Netlist output for hspiceS. * File name: LD_TIA_TSMC_extracted.S.
105
* Subcircuit for cell: TIA_TSMC. * Generated for: hspiceS. X43 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X45 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X47 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X49 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X51 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X53 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X55 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X57 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X59 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X61 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X63 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X65 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X67 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X69 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X71 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X73 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X75 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X77 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X79 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X81 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X83 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X85 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X87 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X89 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X91 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X93 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X95 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X97 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X99 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X101 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X103 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X105 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X107 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X109 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X111 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X113 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X115 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X117 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X119 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X121 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X123 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X125 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X127 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X129 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X131 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X133 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X135 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X137 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X139 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X141 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X143 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X145 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X147 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0
106
X149 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X151 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X153 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X155 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X157 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X159 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X161 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X163 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X165 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X167 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X169 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X171 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X173 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X175 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X177 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X179 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X181 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X183 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X185 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X187 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X189 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X191 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X193 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X195 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X197 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X199 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X201 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X203 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X205 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X207 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X209 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X211 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X213 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X215 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X217 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X219 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X221 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X223 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X225 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X227 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X229 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X231 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X233 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X235 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X237 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X239 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X241 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X243 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X245 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X247 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X249 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X251 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X253 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X255 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X257 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X259 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0
107
X261 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X263 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X265 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X267 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X269 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X271 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X273 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X275 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X277 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X279 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X281 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X283 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X285 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X287 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X289 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X291 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X293 6 5 MIMCAP LT=29.9999992421363E-6 M=1.0 X295 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X297 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X299 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X301 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X303 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X305 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X307 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X309 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X311 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X313 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X315 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X317 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X319 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X321 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X323 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X325 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X327 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X329 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X331 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X333 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X335 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X337 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X339 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X341 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X343 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X345 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X347 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X349 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X351 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X353 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X355 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X357 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X359 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X361 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X363 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X365 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X367 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X369 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X371 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0
108
X373 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X375 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X377 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X379 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X381 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X383 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X385 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X387 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X389 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X391 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X393 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X395 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X397 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X399 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X401 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X403 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X405 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X407 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X409 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X411 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X413 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X415 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X417 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X419 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X421 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X423 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X425 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X427 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X429 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X431 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X433 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X435 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X437 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X439 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X441 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X443 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X445 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X447 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X449 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X451 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X453 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X455 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X457 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X459 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X461 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X463 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X465 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X467 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X469 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X471 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X473 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X475 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X477 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X479 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X481 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X483 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0
109
X485 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X487 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X489 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X491 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X493 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X495 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X497 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X499 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X501 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X503 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X505 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X507 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X509 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X511 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X513 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X515 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X517 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X519 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X521 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X523 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X525 41 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X527 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X529 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X531 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X533 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X535 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X537 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X539 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X541 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X543 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X545 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X547 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X549 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X551 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X553 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X555 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X557 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X559 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X561 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X563 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X565 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X567 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X569 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X571 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X573 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X575 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X577 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X579 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X581 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X583 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X585 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X587 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X589 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X591 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X593 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X595 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0
110
X597 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X599 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X601 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X603 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X605 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X607 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X609 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X611 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X613 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X615 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X617 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X619 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 X621 20 28 MIMCAP LT=29.9999992421363E-6 M=1.0 D623 5 8 NDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D625 5 8 NDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D627 5 8 NDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D629 5 8 NDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D631 5 8 NDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D633 5 8 NDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D635 5 8 NDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D637 5 8 NDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D639 5 8 NDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D641 5 8 NDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D643 5 8 NDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D645 5 8 NDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D647 5 8 NDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D649 5 8 NDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D651 5 8 NDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D653 5 8 NDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D655 5 8 NDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D657 5 8 NDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D659 5 8 NDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D661 5 8 NDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D663 5 8 NDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D665 5 8 NDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6
111
+M=1.0 D667 5 8 NDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D669 5 8 NDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D671 5 8 NDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D673 5 8 NDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D675 5 8 NDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D677 5 8 NDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D679 5 8 NDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D681 5 8 NDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D683 5 8 NDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D685 5 8 NDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D687 5 8 NDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D689 5 8 NDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D691 5 8 NDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D693 5 8 NDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D695 5 8 NDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D697 5 8 NDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D699 5 8 NDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D701 5 8 NDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D703 5 8 NDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D705 5 8 NDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D707 7 28 PDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 +L=10E-6 M=1.0 D709 7 28 PDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 +L=10E-6 M=1.0 D711 7 20 PDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 +L=10E-6 M=1.0 D713 7 20 PDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 +L=10E-6 M=1.0 D715 7 35 PDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 +L=10E-6 M=1.0 D717 7 35 PDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 +L=10E-6 M=1.0 D719 7 29 PDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 +L=10E-6 M=1.0 D721 7 29 PDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6
112
+L=10E-6 M=1.0 D723 7 28 PDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 +L=10E-6 M=1.0 D725 7 27 PDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 +L=10E-6 M=1.0 D727 7 28 PDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 +L=10E-6 M=1.0 D729 7 27 PDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 +L=10E-6 M=1.0 D731 7 20 PDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 +L=10E-6 M=1.0 D733 7 19 PDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 +L=10E-6 M=1.0 D735 7 20 PDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 +L=10E-6 M=1.0 D737 7 19 PDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 +L=10E-6 M=1.0 D739 7 8 PDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D741 7 15 PDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 +L=10E-6 M=1.0 D743 7 8 PDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D745 7 15 PDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 +L=10E-6 M=1.0 D747 7 6 PDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D749 7 6 PDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D751 7 9 PDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D753 7 5 PDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D755 7 9 PDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D757 7 5 PDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D759 7 5 PDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D761 7 1 PDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D763 7 5 PDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D765 7 1 PDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D767 7 6 PDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D769 7 2 PDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D771 7 6 PDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D773 7 2 PDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D775 7 6 PDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D777 7 3 PDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6
113
+M=1.0 D779 7 6 PDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D781 7 3 PDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D783 7 4 PDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D785 7 4 PDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D787 7 5 PDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 D789 7 5 PDIO AREA=400.000005340573E-12 PJ=79.99999797903E-6 W=10E-6 L=10E-6 +M=1.0 X791 6 30 SPIRAL_TURN NR=2.5 RAD=59.9999984842725E-6 X793 6 22 SPIRAL_TURN NR=2.5 RAD=59.9999984842725E-6 X795 6 32 SPIRAL_TURN NR=2.5 RAD=59.9999984842725E-6 X797 6 24 SPIRAL_TURN NR=2.5 RAD=59.9999984842725E-6 C2213 39 40 1.94617169873169E-15 C2215 38 40 684.963992467267E-18 C2217 38 39 180.291823090915E-18 C2219 37 40 204.187138693661E-18 C2221 37 39 214.551844117848E-18 C2223 36 39 266.844653961344E-18 C2225 36 38 3.28099016800253E-15 C2227 36 37 3.07263022737334E-15 C2229 35 38 3.00053057114482E-15 C2231 35 37 2.99977014731642E-15 C2233 34 40 1.88512899883839E-15 C2235 34 39 1.82479526552193E-15 C2237 34 38 9.47120477884237E-15 C2239 34 36 20.7351734252733E-15 C2241 34 35 2.97102989589961E-15 C2243 33 40 1.84086919800374E-15 C2245 33 39 1.91397152948358E-15 C2247 33 37 9.37397810199178E-15 C2249 33 36 20.7356375993284E-15 C2251 33 35 2.9706076499754E-15 C2253 32 34 128.385802901849E-18 C2255 31 34 3.17670664791013E-15 C2257 31 33 3.17664756736206E-15 C2259 31 32 10.6963891333896E-18 C2261 30 33 109.091080577666E-18 C2263 30 31 10.5523463830614E-18 C2265 29 37 128.884030328402E-18 C2267 29 35 11.1020803214199E-15 C2269 28 41 141.617783038644E-15 C2271 28 40 6.34100172204415E-15 C2273 28 39 6.30378860005595E-15 C2275 28 38 25.8368223733998E-15 C2277 28 37 26.1158045330393E-15 C2279 28 36 31.5766123914606E-15 C2281 28 35 3.72907398523185E-15 C2283 28 34 1.13553851007798E-15 C2285 28 33 1.05811641644627E-15 C2287 28 29 5.8311226161479E-15 C2289 27 37 599.26569872661E-18
114
C2291 27 36 44.4344815276786E-18 C2293 27 35 87.8689811041195E-18 C2295 27 33 31.3483750492489E-18 C2297 27 29 12.4469204610062E-15 C2299 27 28 6.46397057719474E-15 C2301 26 34 1.92136083315719E-15 C2303 26 32 12.5476250551382E-15 C2305 26 31 15.8192533914912E-15 C2307 25 33 1.92136019788248E-15 C2309 25 31 15.8194702319257E-15 C2311 25 30 12.5640219189311E-15 C2313 23 26 3.17665688472448E-15 C2315 23 25 3.17646249066309E-15 C2317 21 33 29.5658636949237E-18 C2319 21 30 5.74583317462297E-15 C2321 21 26 3.69735175432422E-15 C2323 21 25 1.95896973128999E-15 C2325 21 24 6.67078214159635E-15 C2327 20 40 16.7363579863401E-15 C2329 20 39 16.7994619409105E-15 C2331 20 38 1.54540356545247E-15 C2333 20 37 1.53897638532782E-15 C2335 20 36 88.6466499939275E-18 C2337 20 35 9.39861236119678E-15 C2339 20 34 22.0681932200806E-15 C2341 20 33 22.0445897999725E-15 C2343 20 29 1.934500008235E-15 C2345 20 28 340.003822622489E-15 C2347 20 27 1.93442504581916E-15 C2349 19 40 1.74516368644731E-15 C2351 19 39 1.74306833869404E-15 C2353 19 38 60.948401303471E-18 C2355 19 37 62.0993999647814E-18 C2357 19 36 2.70596109945174E-15 C2359 19 34 623.312540582686E-18 C2361 19 33 764.127479959418E-18 C2363 19 28 14.4390708021807E-15 C2365 19 27 13.1674422613245E-15 C2367 19 20 4.60765382757368E-15 C2369 18 34 29.5658636949237E-18 C2371 18 32 5.79003262436012E-15 C2373 18 26 1.95599135168921E-15 C2375 18 25 3.66320446808861E-15 C2377 18 22 6.66503332898334E-15 C2379 18 21 5.04657910106081E-15 C2381 17 26 1.90680181910154E-15 C2383 17 24 10.7248101526469E-15 C2385 17 23 15.8192449211617E-15 C2387 17 21 7.67992660704328E-15 C2389 16 25 1.90396383521177E-15 C2391 16 23 15.8196565791741E-15 C2393 16 22 10.7217964094206E-15 C2395 16 18 8.32780940290389E-15 C2397 15 19 414.158718323681E-18 C2399 14 21 11.1897194323405E-15 C2401 14 17 180.291823090915E-18
115
C2403 14 16 214.655857116793E-18 C2405 13 17 3.15351043889134E-15 C2407 13 16 3.15178609156897E-15 C2409 13 14 266.844653961344E-18 C2411 12 21 42.5022207039793E-18 C2413 12 18 11.2730141112747E-15 C2415 12 17 207.28606167075E-18 C2417 12 16 172.956848639938E-18 C2419 12 14 1.94617169873169E-15 C2421 11 17 6.01242154817821E-15 C2423 11 14 3.36592999667848E-15 C2425 11 13 20.7351734252733E-15 C2427 11 12 1.88504874246663E-15 C2429 10 16 6.01157790336274E-15 C2431 10 14 1.92084604888349E-15 C2433 10 13 20.7356494577897E-15 C2435 10 12 3.37466862383707E-15 C2437 8 35 21.0926552103325E-15 C2439 8 29 21.0926552103325E-15 C2441 8 28 42.185310420665E-15 C2443 8 27 21.0926552103325E-15 C2445 8 20 42.4297370241883E-15 C2447 8 19 21.0926552103325E-15 C2449 8 15 21.0926552103325E-15 C2451 8 9 21.0926552103325E-15 C2453 7 35 20.6043186933838E-15 C2455 7 29 20.6043186933838E-15 C2457 7 28 41.2086373867675E-15 C2459 7 27 20.6043186933838E-15 C2461 7 20 41.2086373867675E-15 C2463 7 19 20.6043186933838E-15 C2465 7 15 20.6043186933838E-15 C2467 7 9 20.8487436028412E-15 C2469 7 8 564.155981045561E-15 C2471 6 26 267.90492745307E-18 C2473 6 25 228.441503621814E-18 C2475 6 21 267.90492745307E-18 C2477 6 18 267.90492745307E-18 C2479 6 17 1.52597993530163E-15 C2481 6 16 1.52726795477705E-15 C2483 6 15 414.158718323681E-18 C2485 6 14 16.8376936200178E-15 C2487 6 13 20.3285409255582E-18 C2489 6 12 16.7471678208129E-15 C2491 6 11 21.633587391108E-15 C2493 6 10 21.6195334204472E-15 C2495 6 8 63.2779690191293E-15 C2497 6 7 61.8129543860854E-15 C2499 5 41 1.04788736281919E-12 C2501 5 40 2.88495377252492E-15 C2503 5 39 2.83349037999035E-15 C2505 5 38 33.7713865661456E-15 C2507 5 37 33.4990925786576E-15 C2509 5 36 5.15187291970105E-15 C2511 5 35 426.499764324961E-15 C2513 5 34 16.5353621501543E-15
116
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117
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121
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122
M975 32 18 26 32 PCH L=180.000000682412E-9 W=2.49999993684469E-6 +AD=674.999986460811E-15 AS=674.999986460811E-15 PD=3.03999991047021E-6 +PS=3.03999991047021E-6 M=+1.00000000E+00 M977 30 21 25 30 PCH L=180.000000682412E-9 W=2.49999993684469E-6 +AD=674.999986460811E-15 AS=674.999986460811E-15 PD=3.03999991047021E-6 +PS=3.03999991047021E-6 M=+1.00000000E+00 M979 26 18 32 32 PCH L=180.000000682412E-9 W=2.49999993684469E-6 +AD=674.999986460811E-15 AS=674.999986460811E-15 PD=3.03999991047021E-6 +PS=3.03999991047021E-6 M=+1.00000000E+00 M981 25 21 30 30 PCH L=180.000000682412E-9 W=2.49999993684469E-6 +AD=674.999986460811E-15 AS=674.999986460811E-15 PD=3.03999991047021E-6 +PS=3.03999991047021E-6 M=+1.00000000E+00 M983 32 18 26 32 PCH L=180.000000682412E-9 W=2.49999993684469E-6 +AD=674.999986460811E-15 AS=674.999986460811E-15 PD=3.03999991047021E-6 +PS=3.03999991047021E-6 M=+1.00000000E+00 M985 30 21 25 30 PCH L=180.000000682412E-9 W=2.49999993684469E-6 +AD=674.999986460811E-15 AS=674.999986460811E-15 PD=3.03999991047021E-6 +PS=3.03999991047021E-6 M=+1.00000000E+00 M987 26 18 32 32 PCH L=180.000000682412E-9 W=2.49999993684469E-6 +AD=674.999986460811E-15 AS=674.999986460811E-15 PD=3.03999991047021E-6 +PS=3.03999991047021E-6 M=+1.00000000E+00 M989 25 21 30 30 PCH L=180.000000682412E-9 W=2.49999993684469E-6 +AD=674.999986460811E-15 AS=674.999986460811E-15 PD=3.03999991047021E-6 +PS=3.03999991047021E-6 M=+1.00000000E+00 M991 30 21 25 30 PCH L=180.000000682412E-9 W=2.49999993684469E-6 +AD=674.999986460811E-15 AS=674.999986460811E-15 PD=3.03999991047021E-6 +PS=3.03999991047021E-6 M=+1.00000000E+00 M993 32 18 26 32 PCH L=180.000000682412E-9 W=2.49999993684469E-6 +AD=674.999986460811E-15 AS=674.999986460811E-15 PD=3.03999991047021E-6 +PS=3.03999991047021E-6 M=+1.00000000E+00 M995 26 18 32 32 PCH L=180.000000682412E-9 W=2.49999993684469E-6 +AD=674.999986460811E-15 AS=674.999986460811E-15 PD=3.03999991047021E-6 +PS=3.03999991047021E-6 M=+1.00000000E+00 M997 25 21 30 30 PCH L=180.000000682412E-9 W=2.49999993684469E-6 +AD=674.999986460811E-15 AS=674.999986460811E-15 PD=3.03999991047021E-6 +PS=3.03999991047021E-6 M=+1.00000000E+00 M999 32 18 26 32 PCH L=180.000000682412E-9 W=2.49999993684469E-6 +AD=674.999986460811E-15 AS=674.999986460811E-15 PD=3.03999991047021E-6 +PS=3.03999991047021E-6 M=+1.00000000E+00 M1001 30 21 25 30 PCH L=180.000000682412E-9 W=2.49999993684469E-6 +AD=674.999986460811E-15 AS=674.999986460811E-15 PD=3.03999991047021E-6 +PS=3.03999991047021E-6 M=+1.00000000E+00 M1003 26 18 32 32 PCH L=180.000000682412E-9 W=2.49999993684469E-6 +AD=674.999986460811E-15 AS=674.999986460811E-15 PD=3.03999991047021E-6 +PS=3.03999991047021E-6 M=+1.00000000E+00 M1005 25 21 30 30 PCH L=180.000000682412E-9 W=2.49999993684469E-6 +AD=674.999986460811E-15 AS=674.999986460811E-15 PD=3.03999991047021E-6 +PS=3.03999991047021E-6 M=+1.00000000E+00 M1007 32 18 26 32 PCH L=180.000000682412E-9 W=2.49999993684469E-6 +AD=674.999986460811E-15 AS=674.999986460811E-15 PD=3.03999991047021E-6 +PS=3.03999991047021E-6 M=+1.00000000E+00 M1009 30 21 25 30 PCH L=180.000000682412E-9 W=2.49999993684469E-6 +AD=674.999986460811E-15 AS=674.999986460811E-15 PD=3.03999991047021E-6 +PS=3.03999991047021E-6 M=+1.00000000E+00 M1011 26 18 32 32 PCH L=180.000000682412E-9 W=2.49999993684469E-6 +AD=674.999986460811E-15 AS=674.999986460811E-15 PD=3.03999991047021E-6
123
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124
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125
M1087 20 40 34 20 PCH L=180.000000682412E-9 W=3.00000010611257E-6 +AD=810.000016279039E-15 AS=810.000016279039E-15 PD=3.54000007973809E-6 +PS=3.54000007973809E-6 M=+1.00000000E+00 M1089 20 39 33 20 PCH L=180.000000682412E-9 W=3.00000010611257E-6 +AD=810.000016279039E-15 AS=810.000016279039E-15 PD=3.54000007973809E-6 +PS=3.54000007973809E-6 M=+1.00000000E+00 M1091 34 40 20 20 PCH L=180.000000682412E-9 W=3.00000010611257E-6 +AD=810.000016279039E-15 AS=810.000016279039E-15 PD=3.54000007973809E-6 +PS=3.54000007973809E-6 M=+1.00000000E+00 M1093 33 39 20 20 PCH L=180.000000682412E-9 W=3.00000010611257E-6 +AD=810.000016279039E-15 AS=810.000016279039E-15 PD=3.54000007973809E-6 +PS=3.54000007973809E-6 M=+1.00000000E+00 M1095 20 40 34 20 PCH L=180.000000682412E-9 W=3.00000010611257E-6 +AD=810.000016279039E-15 AS=810.000016279039E-15 PD=3.54000007973809E-6 +PS=3.54000007973809E-6 M=+1.00000000E+00 M1097 20 39 33 20 PCH L=180.000000682412E-9 W=3.00000010611257E-6 +AD=810.000016279039E-15 AS=810.000016279039E-15 PD=3.54000007973809E-6 +PS=3.54000007973809E-6 M=+1.00000000E+00 M1099 34 40 20 20 PCH L=180.000000682412E-9 W=3.00000010611257E-6 +AD=810.000016279039E-15 AS=810.000016279039E-15 PD=3.54000007973809E-6 +PS=3.54000007973809E-6 M=+1.00000000E+00 M1101 33 39 20 20 PCH L=180.000000682412E-9 W=3.00000010611257E-6 +AD=810.000016279039E-15 AS=810.000016279039E-15 PD=3.54000007973809E-6 +PS=3.54000007973809E-6 M=+1.00000000E+00 M1103 20 40 34 20 PCH L=180.000000682412E-9 W=3.00000010611257E-6 +AD=810.000016279039E-15 AS=810.000016279039E-15 PD=3.54000007973809E-6 +PS=3.54000007973809E-6 M=+1.00000000E+00 M1105 20 39 33 20 PCH L=180.000000682412E-9 W=3.00000010611257E-6 +AD=810.000016279039E-15 AS=810.000016279039E-15 PD=3.54000007973809E-6 +PS=3.54000007973809E-6 M=+1.00000000E+00 M1107 33 39 20 20 PCH L=180.000000682412E-9 W=3.00000010611257E-6 +AD=810.000016279039E-15 AS=810.000016279039E-15 PD=3.54000007973809E-6 +PS=3.54000007973809E-6 M=+1.00000000E+00 M1109 34 40 20 20 PCH L=180.000000682412E-9 W=3.00000010611257E-6 +AD=810.000016279039E-15 AS=810.000016279039E-15 PD=3.54000007973809E-6 +PS=3.54000007973809E-6 M=+1.00000000E+00 M1111 20 40 34 20 PCH L=180.000000682412E-9 W=3.00000010611257E-6 +AD=810.000016279039E-15 AS=810.000016279039E-15 PD=3.54000007973809E-6 +PS=3.54000007973809E-6 M=+1.00000000E+00 M1113 20 39 33 20 PCH L=180.000000682412E-9 W=3.00000010611257E-6 +AD=810.000016279039E-15 AS=810.000016279039E-15 PD=3.54000007973809E-6 +PS=3.54000007973809E-6 M=+1.00000000E+00 M1115 34 40 20 20 PCH L=180.000000682412E-9 W=3.00000010611257E-6 +AD=810.000016279039E-15 AS=1.44000002894051E-12 PD=3.54000007973809E-6 +PS=6.96000006428221E-6 M=+1.00000000E+00 M1117 33 39 20 20 PCH L=180.000000682412E-9 W=3.00000010611257E-6 +AD=810.000016279039E-15 AS=1.44000002894051E-12 PD=3.54000007973809E-6 +PS=6.96000006428221E-6 M=+1.00000000E+00 M1119 6 12 11 6 PCH L=180.000000682412E-9 W=3.00000010611257E-6 +AD=1.44000002894051E-12 AS=810.000016279039E-15 PD=6.96000006428221E-6 +PS=3.54000007973809E-6 M=+1.00000000E+00 M1121 6 14 10 6 PCH L=180.000000682412E-9 W=3.00000010611257E-6 +AD=1.44000002894051E-12 AS=810.000016279039E-15 PD=6.96000006428221E-6 +PS=3.54000007973809E-6 M=+1.00000000E+00 M1123 11 12 6 6 PCH L=180.000000682412E-9 W=3.00000010611257E-6 +AD=810.000016279039E-15 AS=810.000016279039E-15 PD=3.54000007973809E-6
126
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127
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128
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129
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130
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131
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132
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133
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134
M1423 31 1 5 5 NCH L=180.000000682412E-9 W=3.74999990526703E-6 +AD=1.01249997969122E-12 AS=1.01249997969122E-12 PD=4.29000010626623E-6 +PS=4.29000010626623E-6 M=+1.00000000E+00 M1425 25 33 31 5 NCH L=180.000000682412E-9 W=3.74999990526703E-6 +AD=1.01249997969122E-12 AS=1.01249997969122E-12 PD=4.29000010626623E-6 +PS=4.29000010626623E-6 M=+1.00000000E+00 M1427 31 34 26 5 NCH L=180.000000682412E-9 W=3.74999990526703E-6 +AD=1.01249997969122E-12 AS=1.01249997969122E-12 PD=4.29000010626623E-6 +PS=4.29000010626623E-6 M=+1.00000000E+00 M1429 5 1 31 5 NCH L=180.000000682412E-9 W=3.74999990526703E-6 +AD=1.01249997969122E-12 AS=1.01249997969122E-12 PD=4.29000010626623E-6 +PS=4.29000010626623E-6 M=+1.00000000E+00 M1431 31 33 25 5 NCH L=180.000000682412E-9 W=3.74999990526703E-6 +AD=1.01249997969122E-12 AS=1.01249997969122E-12 PD=4.29000010626623E-6 +PS=4.29000010626623E-6 M=+1.00000000E+00 M1433 25 33 31 5 NCH L=180.000000682412E-9 W=3.74999990526703E-6 +AD=1.01249997969122E-12 AS=1.80000003617564E-12 PD=4.29000010626623E-6 +PS=8.45999966259114E-6 M=+1.00000000E+00 M1435 26 34 31 5 NCH L=180.000000682412E-9 W=3.74999990526703E-6 +AD=1.01249997969122E-12 AS=1.80000003617564E-12 PD=4.29000010626623E-6 +PS=8.45999966259114E-6 M=+1.00000000E+00 M1437 31 1 5 5 NCH L=180.000000682412E-9 W=3.74999990526703E-6 +AD=1.01249997969122E-12 AS=1.80000003617564E-12 PD=4.29000010626623E-6 +PS=8.45999966259114E-6 M=+1.00000000E+00 M1439 23 26 17 5 NCH L=180.000000682412E-9 W=3.74999990526703E-6 +AD=1.80000003617564E-12 AS=1.01249997969122E-12 PD=8.45999966259114E-6 +PS=4.29000010626623E-6 M=+1.00000000E+00 M1441 5 1 23 5 NCH L=180.000000682412E-9 W=3.74999990526703E-6 +AD=1.80000003617564E-12 AS=1.01249997969122E-12 PD=8.45999966259114E-6 +PS=4.29000010626623E-6 M=+1.00000000E+00 M1443 23 25 16 5 NCH L=180.000000682412E-9 W=3.74999990526703E-6 +AD=1.80000003617564E-12 AS=1.01249997969122E-12 PD=8.45999966259114E-6 +PS=4.29000010626623E-6 M=+1.00000000E+00 M1445 17 26 23 5 NCH L=180.000000682412E-9 W=3.74999990526703E-6 +AD=1.01249997969122E-12 AS=1.01249997969122E-12 PD=4.29000010626623E-6 +PS=4.29000010626623E-6 M=+1.00000000E+00 M1447 23 1 5 5 NCH L=180.000000682412E-9 W=3.74999990526703E-6 +AD=1.01249997969122E-12 AS=1.01249997969122E-12 PD=4.29000010626623E-6 +PS=4.29000010626623E-6 M=+1.00000000E+00 M1449 16 25 23 5 NCH L=180.000000682412E-9 W=3.74999990526703E-6 +AD=1.01249997969122E-12 AS=1.01249997969122E-12 PD=4.29000010626623E-6 +PS=4.29000010626623E-6 M=+1.00000000E+00 M1451 23 26 17 5 NCH L=180.000000682412E-9 W=3.74999990526703E-6 +AD=1.01249997969122E-12 AS=1.01249997969122E-12 PD=4.29000010626623E-6 +PS=4.29000010626623E-6 M=+1.00000000E+00 M1453 5 1 23 5 NCH L=180.000000682412E-9 W=3.74999990526703E-6 +AD=1.01249997969122E-12 AS=1.01249997969122E-12 PD=4.29000010626623E-6 +PS=4.29000010626623E-6 M=+1.00000000E+00 M1455 23 25 16 5 NCH L=180.000000682412E-9 W=3.74999990526703E-6 +AD=1.01249997969122E-12 AS=1.01249997969122E-12 PD=4.29000010626623E-6 +PS=4.29000010626623E-6 M=+1.00000000E+00 M1457 23 1 5 5 NCH L=180.000000682412E-9 W=3.74999990526703E-6 +AD=1.01249997969122E-12 AS=1.01249997969122E-12 PD=4.29000010626623E-6 +PS=4.29000010626623E-6 M=+1.00000000E+00 M1459 16 25 23 5 NCH L=180.000000682412E-9 W=3.74999990526703E-6 +AD=1.01249997969122E-12 AS=1.01249997969122E-12 PD=4.29000010626623E-6
135
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136
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137
M1535 23 26 17 5 NCH L=180.000000682412E-9 W=3.74999990526703E-6 +AD=1.01249997969122E-12 AS=1.01249997969122E-12 PD=4.29000010626623E-6 +PS=4.29000010626623E-6 M=+1.00000000E+00 M1537 5 1 23 5 NCH L=180.000000682412E-9 W=3.74999990526703E-6 +AD=1.01249997969122E-12 AS=1.01249997969122E-12 PD=4.29000010626623E-6 +PS=4.29000010626623E-6 M=+1.00000000E+00 M1539 23 25 16 5 NCH L=180.000000682412E-9 W=3.74999990526703E-6 +AD=1.01249997969122E-12 AS=1.01249997969122E-12 PD=4.29000010626623E-6 +PS=4.29000010626623E-6 M=+1.00000000E+00 M1541 17 26 23 5 NCH L=180.000000682412E-9 W=3.74999990526703E-6 +AD=1.01249997969122E-12 AS=1.01249997969122E-12 PD=4.29000010626623E-6 +PS=4.29000010626623E-6 M=+1.00000000E+00 M1543 23 1 5 5 NCH L=180.000000682412E-9 W=3.74999990526703E-6 +AD=1.01249997969122E-12 AS=1.01249997969122E-12 PD=4.29000010626623E-6 +PS=4.29000010626623E-6 M=+1.00000000E+00 M1545 16 25 23 5 NCH L=180.000000682412E-9 W=3.74999990526703E-6 +AD=1.01249997969122E-12 AS=1.01249997969122E-12 PD=4.29000010626623E-6 +PS=4.29000010626623E-6 M=+1.00000000E+00 M1547 23 26 17 5 NCH L=180.000000682412E-9 W=3.74999990526703E-6 +AD=1.01249997969122E-12 AS=1.01249997969122E-12 PD=4.29000010626623E-6 +PS=4.29000010626623E-6 M=+1.00000000E+00 M1549 5 1 23 5 NCH L=180.000000682412E-9 W=3.74999990526703E-6 +AD=1.01249997969122E-12 AS=1.01249997969122E-12 PD=4.29000010626623E-6 +PS=4.29000010626623E-6 M=+1.00000000E+00 M1551 23 25 16 5 NCH L=180.000000682412E-9 W=3.74999990526703E-6 +AD=1.01249997969122E-12 AS=1.01249997969122E-12 PD=4.29000010626623E-6 +PS=4.29000010626623E-6 M=+1.00000000E+00 M1553 17 26 23 5 NCH L=180.000000682412E-9 W=3.74999990526703E-6 +AD=1.01249997969122E-12 AS=1.80000003617564E-12 PD=4.29000010626623E-6 +PS=8.45999966259114E-6 M=+1.00000000E+00 M1555 23 1 5 5 NCH L=180.000000682412E-9 W=3.74999990526703E-6 +AD=1.01249997969122E-12 AS=1.80000003617564E-12 PD=4.29000010626623E-6 +PS=8.45999966259114E-6 M=+1.00000000E+00 M1557 16 25 23 5 NCH L=180.000000682412E-9 W=3.74999990526703E-6 +AD=1.01249997969122E-12 AS=1.80000003617564E-12 PD=4.29000010626623E-6 +PS=8.45999966259114E-6 M=+1.00000000E+00 M1559 20 33 40 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=959.999983153603E-15 AS=540.000010852693E-15 PD=4.95999984195805E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1561 20 34 39 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=959.999983153603E-15 AS=540.000010852693E-15 PD=4.95999984195805E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1563 39 34 20 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1565 40 33 20 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1567 20 34 39 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1569 20 33 40 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1571 40 33 20 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6
138
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139
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140
M1647 21 14 14 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1649 14 11 6 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1651 12 10 6 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1653 18 12 12 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1655 14 14 21 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1657 6 11 14 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1659 6 10 12 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1661 12 12 18 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1663 21 14 14 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1665 14 11 6 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1667 12 10 6 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1669 18 12 12 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1671 6 10 12 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1673 12 12 18 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1675 14 14 21 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1677 6 11 14 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1679 12 10 6 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1681 18 12 12 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1683 21 14 14 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6
141
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142
+AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1723 14 14 21 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1725 6 11 14 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1727 12 10 6 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1729 18 12 12 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1731 21 14 14 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1733 14 11 6 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1735 14 14 21 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1737 6 11 14 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1739 6 10 12 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1741 12 12 18 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1743 21 14 14 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1745 14 11 6 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1747 12 10 6 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1749 18 12 12 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1751 14 14 21 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1753 6 11 14 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1755 6 10 12 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1757 12 12 18 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00
143
M1759 12 10 6 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1761 18 12 12 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1763 21 14 14 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1765 14 11 6 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1767 6 10 12 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1769 12 12 18 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1771 14 14 21 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1773 6 11 14 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1775 18 12 12 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1777 21 14 14 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1779 14 11 6 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1781 12 10 6 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1783 14 14 21 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1785 6 11 14 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1787 6 10 12 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1789 12 12 18 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=540.000010852693E-15 PD=2.53999996857601E-6 +PS=2.53999996857601E-6 M=+1.00000000E+00 M1791 21 14 14 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=959.999983153603E-15 PD=2.53999996857601E-6 +PS=4.95999984195805E-6 M=+1.00000000E+00 M1793 14 11 6 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=959.999983153603E-15 PD=2.53999996857601E-6 +PS=4.95999984195805E-6 M=+1.00000000E+00 M1795 12 10 6 5 NCH L=180.000000682412E-9 W=1.99999999495049E-6 +AD=540.000010852693E-15 AS=959.999983153603E-15 PD=2.53999996857601E-6
144
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145
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146
M1871 28 19 39 5 NCH L=180.000000682412E-9 W=999.999997475243E-9 +AD=270.000005426346E-15 AS=270.000005426346E-15 PD=1.53999997110077E-6 +PS=1.53999997110077E-6 M=+1.00000000E+00 M1873 28 19 40 5 NCH L=180.000000682412E-9 W=999.999997475243E-9 +AD=270.000005426346E-15 AS=270.000005426346E-15 PD=1.53999997110077E-6 +PS=1.53999997110077E-6 M=+1.00000000E+00 M1875 40 19 28 5 NCH L=180.000000682412E-9 W=999.999997475243E-9 +AD=270.000005426346E-15 AS=479.999991576802E-15 PD=1.53999997110077E-6 +PS=2.96000007438124E-6 M=+1.00000000E+00 M1877 39 19 28 5 NCH L=180.000000682412E-9 W=999.999997475243E-9 +AD=270.000005426346E-15 AS=479.999991576802E-15 PD=1.53999997110077E-6 +PS=2.96000007438124E-6 M=+1.00000000E+00 M1879 5 2 18 5 NCH L=180.000000682412E-9 W=999.999997475243E-9 +AD=479.999991576802E-15 AS=270.000005426346E-15 PD=2.96000007438124E-6 +PS=1.53999997110077E-6 M=+1.00000000E+00 M1881 5 2 21 5 NCH L=180.000000682412E-9 W=999.999997475243E-9 +AD=479.999991576802E-15 AS=270.000005426346E-15 PD=2.96000007438124E-6 +PS=1.53999997110077E-6 M=+1.00000000E+00 M1883 18 2 5 5 NCH L=180.000000682412E-9 W=999.999997475243E-9 +AD=270.000005426346E-15 AS=270.000005426346E-15 PD=1.53999997110077E-6 +PS=1.53999997110077E-6 M=+1.00000000E+00 M1885 21 2 5 5 NCH L=180.000000682412E-9 W=999.999997475243E-9 +AD=270.000005426346E-15 AS=270.000005426346E-15 PD=1.53999997110077E-6 +PS=1.53999997110077E-6 M=+1.00000000E+00 M1887 5 2 21 5 NCH L=180.000000682412E-9 W=999.999997475243E-9 +AD=270.000005426346E-15 AS=270.000005426346E-15 PD=1.53999997110077E-6 +PS=1.53999997110077E-6 M=+1.00000000E+00 M1889 5 2 18 5 NCH L=180.000000682412E-9 W=999.999997475243E-9 +AD=270.000005426346E-15 AS=270.000005426346E-15 PD=1.53999997110077E-6 +PS=1.53999997110077E-6 M=+1.00000000E+00 M1891 18 2 5 5 NCH L=180.000000682412E-9 W=999.999997475243E-9 +AD=270.000005426346E-15 AS=270.000005426346E-15 PD=1.53999997110077E-6 +PS=1.53999997110077E-6 M=+1.00000000E+00 M1893 21 2 5 5 NCH L=180.000000682412E-9 W=999.999997475243E-9 +AD=270.000005426346E-15 AS=270.000005426346E-15 PD=1.53999997110077E-6 +PS=1.53999997110077E-6 M=+1.00000000E+00 M1895 5 2 18 5 NCH L=180.000000682412E-9 W=999.999997475243E-9 +AD=270.000005426346E-15 AS=270.000005426346E-15 PD=1.53999997110077E-6 +PS=1.53999997110077E-6 M=+1.00000000E+00 M1897 5 2 21 5 NCH L=180.000000682412E-9 W=999.999997475243E-9 +AD=270.000005426346E-15 AS=270.000005426346E-15 PD=1.53999997110077E-6 +PS=1.53999997110077E-6 M=+1.00000000E+00 M1899 18 2 5 5 NCH L=180.000000682412E-9 W=999.999997475243E-9 +AD=270.000005426346E-15 AS=270.000005426346E-15 PD=1.53999997110077E-6 +PS=1.53999997110077E-6 M=+1.00000000E+00 M1901 21 2 5 5 NCH L=180.000000682412E-9 W=999.999997475243E-9 +AD=270.000005426346E-15 AS=270.000005426346E-15 PD=1.53999997110077E-6 +PS=1.53999997110077E-6 M=+1.00000000E+00 M1903 5 2 18 5 NCH L=180.000000682412E-9 W=999.999997475243E-9 +AD=270.000005426346E-15 AS=270.000005426346E-15 PD=1.53999997110077E-6 +PS=1.53999997110077E-6 M=+1.00000000E+00 M1905 5 2 21 5 NCH L=180.000000682412E-9 W=999.999997475243E-9 +AD=270.000005426346E-15 AS=270.000005426346E-15 PD=1.53999997110077E-6 +PS=1.53999997110077E-6 M=+1.00000000E+00 M1907 21 2 5 5 NCH L=180.000000682412E-9 W=999.999997475243E-9 +AD=270.000005426346E-15 AS=270.000005426346E-15 PD=1.53999997110077E-6
147
+PS=1.53999997110077E-6 M=+1.00000000E+00 M1909 18 2 5 5 NCH L=180.000000682412E-9 W=999.999997475243E-9 +AD=270.000005426346E-15 AS=270.000005426346E-15 PD=1.53999997110077E-6 +PS=1.53999997110077E-6 M=+1.00000000E+00 M1911 5 2 21 5 NCH L=180.000000682412E-9 W=999.999997475243E-9 +AD=270.000005426346E-15 AS=270.000005426346E-15 PD=1.53999997110077E-6 +PS=1.53999997110077E-6 M=+1.00000000E+00 M1913 5 2 18 5 NCH L=180.000000682412E-9 W=999.999997475243E-9 +AD=270.000005426346E-15 AS=270.000005426346E-15 PD=1.53999997110077E-6 +PS=1.53999997110077E-6 M=+1.00000000E+00 M1915 18 2 5 5 NCH L=180.000000682412E-9 W=999.999997475243E-9 +AD=270.000005426346E-15 AS=270.000005426346E-15 PD=1.53999997110077E-6 +PS=1.53999997110077E-6 M=+1.00000000E+00 M1917 21 2 5 5 NCH L=180.000000682412E-9 W=999.999997475243E-9 +AD=270.000005426346E-15 AS=270.000005426346E-15 PD=1.53999997110077E-6 +PS=1.53999997110077E-6 M=+1.00000000E+00 M1919 5 2 18 5 NCH L=180.000000682412E-9 W=999.999997475243E-9 +AD=270.000005426346E-15 AS=270.000005426346E-15 PD=1.53999997110077E-6 +PS=1.53999997110077E-6 M=+1.00000000E+00 M1921 5 2 21 5 NCH L=180.000000682412E-9 W=999.999997475243E-9 +AD=270.000005426346E-15 AS=270.000005426346E-15 PD=1.53999997110077E-6 +PS=1.53999997110077E-6 M=+1.00000000E+00 M1923 18 2 5 5 NCH L=180.000000682412E-9 W=999.999997475243E-9 +AD=270.000005426346E-15 AS=270.000005426346E-15 PD=1.53999997110077E-6 +PS=1.53999997110077E-6 M=+1.00000000E+00 M1925 21 2 5 5 NCH L=180.000000682412E-9 W=999.999997475243E-9 +AD=270.000005426346E-15 AS=270.000005426346E-15 PD=1.53999997110077E-6 +PS=1.53999997110077E-6 M=+1.00000000E+00 M1927 5 2 18 5 NCH L=180.000000682412E-9 W=999.999997475243E-9 +AD=270.000005426346E-15 AS=270.000005426346E-15 PD=1.53999997110077E-6 +PS=1.53999997110077E-6 M=+1.00000000E+00 M1929 5 2 21 5 NCH L=180.000000682412E-9 W=999.999997475243E-9 +AD=270.000005426346E-15 AS=270.000005426346E-15 PD=1.53999997110077E-6 +PS=1.53999997110077E-6 M=+1.00000000E+00 M1931 21 2 5 5 NCH L=180.000000682412E-9 W=999.999997475243E-9 +AD=270.000005426346E-15 AS=270.000005426346E-15 PD=1.53999997110077E-6 +PS=1.53999997110077E-6 M=+1.00000000E+00 M1933 18 2 5 5 NCH L=180.000000682412E-9 W=999.999997475243E-9 +AD=270.000005426346E-15 AS=270.000005426346E-15 PD=1.53999997110077E-6 +PS=1.53999997110077E-6 M=+1.00000000E+00 M1935 5 2 18 5 NCH L=180.000000682412E-9 W=999.999997475243E-9 +AD=270.000005426346E-15 AS=270.000005426346E-15 PD=1.53999997110077E-6 +PS=1.53999997110077E-6 M=+1.00000000E+00 M1937 5 2 21 5 NCH L=180.000000682412E-9 W=999.999997475243E-9 +AD=270.000005426346E-15 AS=270.000005426346E-15 PD=1.53999997110077E-6 +PS=1.53999997110077E-6 M=+1.00000000E+00 M1939 18 2 5 5 NCH L=180.000000682412E-9 W=999.999997475243E-9 +AD=270.000005426346E-15 AS=270.000005426346E-15 PD=1.53999997110077E-6 +PS=1.53999997110077E-6 M=+1.00000000E+00 M1941 21 2 5 5 NCH L=180.000000682412E-9 W=999.999997475243E-9 +AD=270.000005426346E-15 AS=270.000005426346E-15 PD=1.53999997110077E-6 +PS=1.53999997110077E-6 M=+1.00000000E+00 M1943 5 2 18 5 NCH L=180.000000682412E-9 W=999.999997475243E-9 +AD=270.000005426346E-15 AS=270.000005426346E-15 PD=1.53999997110077E-6 +PS=1.53999997110077E-6 M=+1.00000000E+00 M1945 5 2 21 5 NCH L=180.000000682412E-9 W=999.999997475243E-9
148
+AD=270.000005426346E-15 AS=270.000005426346E-15 PD=1.53999997110077E-6 +PS=1.53999997110077E-6 M=+1.00000000E+00 M1947 18 2 5 5 NCH L=180.000000682412E-9 W=999.999997475243E-9 +AD=270.000005426346E-15 AS=270.000005426346E-15 PD=1.53999997110077E-6 +PS=1.53999997110077E-6 M=+1.00000000E+00 M1949 21 2 5 5 NCH L=180.000000682412E-9 W=999.999997475243E-9 +AD=270.000005426346E-15 AS=270.000005426346E-15 PD=1.53999997110077E-6 +PS=1.53999997110077E-6 M=+1.00000000E+00 M1951 5 2 21 5 NCH L=180.000000682412E-9 W=999.999997475243E-9 +AD=270.000005426346E-15 AS=270.000005426346E-15 PD=1.53999997110077E-6 +PS=1.53999997110077E-6 M=+1.00000000E+00 M1953 5 2 18 5 NCH L=180.000000682412E-9 W=999.999997475243E-9 +AD=270.000005426346E-15 AS=270.000005426346E-15 PD=1.53999997110077E-6 +PS=1.53999997110077E-6 M=+1.00000000E+00 M1955 21 2 5 5 NCH L=180.000000682412E-9 W=999.999997475243E-9 +AD=270.000005426346E-15 AS=479.999991576802E-15 PD=1.53999997110077E-6 +PS=2.96000007438124E-6 M=+1.00000000E+00 M1957 18 2 5 5 NCH L=180.000000682412E-9 W=999.999997475243E-9 +AD=270.000005426346E-15 AS=479.999991576802E-15 PD=1.53999997110077E-6 +PS=2.96000007438124E-6 M=+1.00000000E+00 M1959 29 29 28 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=2.3999999036739E-12 AS=1.34999997292162E-12 PD=10.9599995994358E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M1961 28 29 37 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=2.3999999036739E-12 PD=5.54000007468858E-6 +PS=10.9599995994358E-6 M=+1.00000000E+00 M1963 27 27 28 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=2.3999999036739E-12 AS=1.34999997292162E-12 PD=10.9599995994358E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M1965 28 27 38 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=2.3999999036739E-12 PD=5.54000007468858E-6 +PS=10.9599995994358E-6 M=+1.00000000E+00 M1967 36 38 34 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=2.3999999036739E-12 AS=1.34999997292162E-12 PD=10.9599995994358E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M1969 28 19 36 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=2.3999999036739E-12 AS=1.34999997292162E-12 PD=10.9599995994358E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M1971 36 37 33 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=2.3999999036739E-12 AS=1.34999997292162E-12 PD=10.9599995994358E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M1973 34 38 36 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M1975 36 19 28 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M1977 33 37 36 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M1979 36 38 34 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M1981 28 19 36 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00
149
M1983 36 37 33 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M1985 36 19 28 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M1987 33 37 36 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M1989 34 38 36 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M1991 36 38 34 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M1993 28 19 36 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M1995 36 37 33 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M1997 34 38 36 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M1999 36 19 28 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2001 33 37 36 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2003 36 37 33 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2005 36 38 34 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2007 28 19 36 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2009 34 38 36 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2011 36 19 28 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2013 33 37 36 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2015 36 38 34 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2017 28 19 36 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2019 36 37 33 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6
150
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151
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152
M2095 13 16 10 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=2.3999999036739E-12 AS=1.34999997292162E-12 PD=10.9599995994358E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2097 11 17 13 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2099 13 2 5 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2101 10 16 13 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2103 13 17 11 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2105 5 2 13 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2107 13 16 10 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2109 11 17 13 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2111 13 2 5 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2113 10 16 13 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2115 13 17 11 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2117 5 2 13 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2119 13 16 10 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2121 10 16 13 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2123 11 17 13 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2125 13 2 5 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2127 13 17 11 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2129 5 2 13 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2131 13 16 10 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6
153
+PS=5.54000007468858E-6 M=+1.00000000E+00 M2133 11 17 13 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2135 13 2 5 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2137 10 16 13 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2139 13 17 11 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2141 5 2 13 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2143 13 16 10 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2145 11 17 13 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2147 13 2 5 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2149 10 16 13 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2151 5 2 13 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2153 13 16 10 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2155 13 17 11 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2157 11 17 13 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2159 13 2 5 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2161 10 16 13 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2163 13 17 11 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2165 5 2 13 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2167 13 16 10 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2169 11 17 13 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6
154
+AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2171 13 2 5 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2173 10 16 13 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2175 13 17 11 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2177 5 2 13 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2179 13 16 10 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2181 11 17 13 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2183 13 2 5 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2185 10 16 13 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2187 13 16 10 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2189 13 17 11 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2191 5 2 13 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2193 11 17 13 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2195 13 2 5 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2197 10 16 13 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2199 13 17 11 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2201 5 2 13 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2203 13 16 10 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=1.34999997292162E-12 PD=5.54000007468858E-6 +PS=5.54000007468858E-6 M=+1.00000000E+00 M2205 11 17 13 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=2.3999999036739E-12 PD=5.54000007468858E-6 +PS=10.9599995994358E-6 M=+1.00000000E+00
155
M2207 13 2 5 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=2.3999999036739E-12 PD=5.54000007468858E-6 +PS=10.9599995994358E-6 M=+1.00000000E+00 M2209 10 16 13 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=1.34999997292162E-12 AS=2.3999999036739E-12 PD=5.54000007468858E-6 +PS=10.9599995994358E-6 M=+1.00000000E+00 M2211 5 2 2 5 NCH L=180.000000682412E-9 W=4.99999987368938E-6 +AD=2.3999999036739E-12 AS=2.3999999036739E-12 PD=10.9599995994358E-6 +PS=10.9599995994358E-6 M=+1.00000000E+00 .TEMP 25.0000 .OP .OPTION INGOLD=2 ARTIST=2 PSF=2 PROBE=0 .END
156
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