M.tech Theis - - VLSI Architecture for Discrete Fractional Fourier Transform

VLSI ARCHITECTURE FOR DISCRETE FRACTIONAL FOURIER TRANSFORM

A THESIS

SUBMITTED IN PARTIAL FULFILMENT OF THE REQUIREMENTS

FOR THE DEGREE OF

MASTER OF TECHNOLOGY IN INFORMATION TECHNOLOGY

(MICRO ELECTRONICS)

INDIAN INSTITUTE OF INFORMATION TECHNOLOGY, ALLAHABAD, U.P. 211012, INDIA

JUNE, 2010

Submitted By V. Naga Vara Prasad M.

M. Tech. IT (MI) IIIT-Allahabad

IMI2008007

Under the Supervision of Dr. K. C. Ray IIIT-Allahabad

INDIAN INSTITUTE OF INFORMATION TECHNOLOGY

ALLAHABAD

(Deemed University) (A Centre of Excellence in Information Technology, Established by Govt. of India)

Date: ______________

WE DO HEREBY RECOMMEND THAT THE THESIS WORK

PREPARED UNDER OUR SUPERVISION BY V. NAGA VARA PRASAD M.

ENTITLED VLSI ARCHITECTURE FOR DISCRETE FRACTIONAL

FOURIER TRANSFORM BE ACCEPTED IN PARTIAL FULFILMENT OF

THE REQUIREMENTS FOR THE DEGREE OF MASTER OF

TECHNOLOGY IN INFORMATION TECHNOLOGY (MICRO

ELECTRONICS) FOR EXAMINATION.

COUNTERSIGNED

Prof. S. Sanyal,

DEAN (ACADEMICS)

Dr. K. C. Ray THESIS ADVISOR

INDIAN INSTITUTE OF INFORMATION TECHNOLOGY

ALLAHABAD

(Deemed University) (A Centre of Excellence in Information Technology, Established by Govt. of India)

CERTIFICATE OF APPROVAL*

The foregoing thesis is hereby approved as a creditable study in the area of

information technology carried out and presented in a manner satisfactory to

warrant its acceptance as a pre-requisite to the degree for which it has been

submitted. It is understood that by this approval the undersigned do not

necessarily endorse or approve any statement made, opinion expressed or

conclusion drawn therein but approve the thesis only for the purpose for

which it is submitted.

COMMITTEE ON

FINAL EXAMINATION

FOR EVALUATION

OF THE THESIS

* Only in case the recommendation is concurred in

CANDIDATE DECLARATION

This is to certify that Report entitled “VLSI Architecture for Discrete

Fractional Fourier Transform” which is submitted by me in partial

fulfillment of the requirement for the completion of M.Tech. In Information

Technology (specialization in Microelectronics) to Indian Institute of

Information Technology, Allahabad comprises only my original work and

due acknowledgements has been made in the text to all other materials

used.

Date: V. Naga Vara Prasad M.

M.Tech. IT: Microelectronics

Enrollment No: IMI2008007

VLSI Architecture for Discrete Fractional Fourier Transform

Indian Institute of Information Technology, Allahabad v | P a g e

Abstract The conventional Fourier transform is recognized as a significant tool in wide

areas of signal, image processing and communication. Its discrete version turned as an

essential module in many applications with the advent of its hundreds of fast

computation algorithms and DSP processors. This thesis has been adding an

additional value to this integral transform with a novel architecture of its generalized

form. This generalized Fourier transform attracted the attention of signal, image and

optical processing communities. Researchers identified its benefits by finding wide

range of applications such as orthogonal frequency division multiplexing, optimum

filters, Image registration, Image encryption, Image water marking, modulation and

demodulation, human emotion detection, Optimal receivers, biomedical signal

detection etc. This thesis enables the real time implementation of their proposals for

different applications. Unlike the ordinary Fourier transform, the fractional Fourier

transform have multiple definitions. Among these definitions, many researches are

recommended a definition which is defined based on Eigen Vector Decomposition

(EVD) as a legitimate definition. With the study of its properties using MATLAB

simulations, we ensured the usability of this definition based on EVD. In this thesis,

we proposed architecture for discrete fractional Fourier transform, which consumes

hardware complexity of O(4N). Where N is transform order. This proposed

architecture has been simulated and synthesized using verilogHDL, targeting a FPGA

device (XLV5LX110T). Hardware simulations are compared with the MATLAB

simulations which show that the results are very close with some quantization error.

The synthesized results have been represented in terms of hardware utilization and

timing, which shows that the proposed architecture can be operated at maximum

frequency of 217MHz. The proposed architecture is also compared with the existing

architecture which shows that the proposed architecture in this thesis is better in terms

of timing and area complexity.


Indian Institute of Information Technology, Allahabad vi | P a g e

Acknowledgement

I would like to express my deep gratitude to Dr. K. C. Ray for the numerous inspiring discussions and constant support throughout this study.

I am highly thankful to him that in spite of his demanding professional

preoccupation he always made himself available for guidance to me in my thesis work.

I am very thankful to Prof. M. Radhakrishna, H.O.D, Department of Microelectronics, IIIT-A. For his vision, motivation and whole-hearted

support throughout my academics.

I am deeply indebted to Prof. B.R Signh and Mr. Manish goswami for their feedback and valuable comments during our regular presentations

which helped me a lot in this thesis work.


Indian Institute of Information Technology, Allahabad vii | P a g e

Contents

Certificate of Approval

Candidate Declaration

Abstract

Acknowledgement

Table of Contents

Chapter 1 Introduction………………………………………….... 01

1.1 Motivation …………………………………………….. 01

1.2 Objective ………………………………………….…… 02

1.3 Literature Survey ……………………………………… 03

1.4 Contribution to this Thesis……………………………... 05

1.5 Thesis outline…………………………………………. 05

Chapter 2 Mathematical background…………………………… 07

2.1 Continuous fractional Fourier Transform……………… 07

2.1.1 Linear Integral transform………………………………..… 08

2.1.2 Fractional Powers of Fourier Transform………...……... 10

2.1.3 Rotation in Time-Frequency Plane……………………….. 12


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2.2 Discrete Fractional Fourier Transform………….……... 12

2.2.1 Direct form DFrFT…………………………………………. 13

2.2.2 Improved sampling Type DFrFT………………….……… 13

2.2.3 Linear Combination Type DFrFT………………………… 13

2.2.4 Eigen vector Decomposition Type DFrFT……………… 14

2.3 Illustration of Fractional Fourier Transform Properties

using MATLAB Simulations…………………………... 17

2.4 CORDIC……………………………………………….. 22

Chapter 3 DFrFT using Discrete Hermite-Gaussian Functions. 25

Chapter 4 VLSI Architecture for Discrete Fractional Fourier

Transform……………………………………………... 29

4.1 Architecture of discrete fractional Fourier Transform

Level-I.............................................................................. 30


Level-II............................................................................ 35


Level-III........................................................................... 37

Chapter 5 Results and Discussion.................................................. 39

Chapter 6 Conclusion and future work…………………………. 56

References…................................................................... 57

Appendix A Xilinx-ISE Simulation Results of Proposed DFrFT

Architecture.................................................................... 61

Publications………………………………………….... 67


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List of Figures

Fig.1.1 Block diagram of Discrete Fractional Fourier Transform……… 02

Fig.2.1 Illustration of linearity Property using MATLAB Simulations

for f1 (x) = sin(π*x), f2 (x) = cos(π*x)………………………….. 17

Fig.2.2 Illustration of Inverse Property using MATLAB simulations for

sinusoidal signal………………………………………………... 18

Fig.2.3 Illustration of Index additive Property using MATLAB

Simulations for sinusoidal signal……………………………….. 18

Fig.2.4 Illustration of Index and Integer Properties using MATLAB

Simulations for sinusoidal signal……………………………..… 19

Fig.2.5 Illustration of Commutative Property using MATLAB


Fig.2.6 Illustration of Associative Property using MATLAB


Fig. 2.7 Graphical representation of CORDIC (a) Circular CORDIC (b)

Linear CORDIC………………………………………………… 23

Fig. 2.8 Normalized angle representation for CORDIC……………….... 24

Fig. 4.1 Block diagram of the DFrFT…………………………………… 29

Fig. 4.2a Calculation of Eigen values…………………………………….. 31


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Fig. 4.2b Architecture of Pipelined CORDIC…………………………… 31

Fig. 4.2c Architecture of single stage pipelined CORDIC……………… 32

Fig. 4.3 The Data flow for part II of level-I……………………………... 33

Fig. 4.4 Data flow Diagram of DFRFT………………………………….. 35

Fig. 4.5 Complex Multiplier with shifting operation……………………. 36

Fig. 4.6 Signal Flow graph for level-III…………………………………. 37

Fig. 5.1 Interpretation of fractional Fourier Transform in Time

Frequency Representation………………………………............. 40

Fig. 5.2 Input Samples for MATLAB Simulation of DFrFT……………. 41

Fig. 5.3 MATLAB Simulation Result of DFrFT for α=00………………. 41

Fig. 5.4 MATLAB Simulation Result of DFrFT for α=300……………... 42



Fig. 5.7 MATLAB Simulation Result of DFrFT for α=1200……………. 43



Fig. 5.10 MATLAB Simulation Result of DFrFT for α=2100…………..... 44






Indian Institute of Information Technology, Allahabad xi | P a g e


Fig. a.1 The Input Samples for the Simulation of proposed DFrFT

architecture using ‘Xilinx ISE’ Simulator……………………… 62

Fig. a.2 The Simulation Result of proposed DFrFT architecture for

Rotation angle of ‘00’ using ‘Xilinx ISE’ Simulator…………… 62


Rotation angle of ‘300’ using ‘Xilinx ISE’ Simulator………….. 63






Rotation angle of ‘1200’ using ‘Xilinx ISE’ Simulator………… 64










Rotation angle of ‘2700’ using ‘Xilinx ISE’ Simulator…………

65




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Rotation angle of ‘3300’ using ‘Xilinx ISE’ Simulator….... 66

Fig. 4.14 The Simulation Result of proposed DFrFT architecture for

Rotation angle of ‘3600’ using ‘Xilinx ISE’ Simulator…… 66


Indian Institute of Information Technology, Allahabad xiii | P a g e

List of Tables

Table-2.1 Mathematical expression for the properties of discrete fractional Fourier transform ………………………………... 14

Table-2.2 Comparison between the three different definitions of discrete fractional Fourier transform………………………... 16

Table-4.1 Arrangement of the elements of Matrix “UT” in ROMs……. 32

Table-5.1 Hardware Requirement for N-point DFrFT…………............ 40

Table-5.2 Comparison of MATLAB and Xilinx-ISE simulation results for Rotation Angle of 00………………………..................... 46

Table-5.3 Comparison of MATLAB and Xilinx-ISE simulation results for Rotation Angles of 300and 600…..................................... 47

Table-5.4 Comparison of MATLAB and Xilinx-ISE simulation results for Rotation Angles of 900and 1200………………………… 48

Table-5.5 Comparison of MATLAB and Xilinx-ISE simulation results for Rotation Angles of 1500 and 1800………………………. 49

Table-5.6 Comparison of MATLAB and Xilinx-ISE simulation results for Rotation Angles of 2100 and 2400………………………. 50

Table-5.7 Comparison of MATLAB and Xilinx-ISE simulation results for Rotation Angles of 2700 and 3000…………..................... 51

Table-5.8 Comparison of MATLAB and Xilinx-ISE simulation results for Rotation Angles of 3300 and 3600……………………… 52

Table-5.9 HDL Synthesis Report- Macro Statistics…………………… 53

Table-5.10 Device utilization-summary report………………………….. 54

Table-5.11 Comparison of proposed architecture with [27] for 1024-point DFrFT…………………………………………………. 55


Indian Institute of Information Technology, Allahabad 1 | P a g e

Chapter 1

Introduction

he Fourier transform has been played an important role in wide range of

signal processing applications. Its discrete version also had a crucial role in

real-time processing of signals and its abilities are enhanced with the DSP

Processors and fast computational algorithms. Its generalized version has been

emerging as a novel mathematical tool for many domains by having the Fourier

transform as a special case of it. Recently researchers have been stated to recommend

this tool in many areas of different domains like optics, Signal processing, Image

processing, and Time-frequency representation.

1.1. Motivation

Since two decades the generalized Fourier transform known as fractional

Fourier transform (FrFT) has been accepted as a novel mathematical tool for the

analysis of non-stationary signals. The FrFT have several applications in the areas of

signal and image processing applications as signal detectors, correlation, pattern

recognition, time variant filtering, multiplexing, image encryption, and signal and

image recovery, restoration.

The real time implementation of the fractional Fourier transform is essential

requirement for all above applications. Especially to implement a versatile device for

T



all above real time applications, the real time computation of FrFT can be

accomplished by implementing its discrete form known as discrete fractional Fourier

transform. Hardware implementation of DFrFT needs the flexibility to change the

rotation angle which is an important parameter in many applications, here only few of

them have been presented. For example in filtering, we have to rotate the signal in

time-frequency plane in order to find the exact rotation angle where the noise is not

overlap the signal [5]. Similarly, for encryption of an image we have to rotate the set

of input pixels as per the given rotation angle (here the value of rotation angle is the

encryption key) and also for analysis of signal in time frequency plane [37]. In all

above applications we need real time hardware with two inputs one to receive signal

samples and another for rotation angle, an output as rotated input samples as shown in

the block diagram of Fig.1.1. Thus the real time hardware for computation of the

DFrFT with flexibility is essential for the real time application.

1.2. Objective

As discussed in previous section, a flexible architecture is required for real

time applications, thus the objective of this thesis is to design a flexible and efficient

architecture of DFrFT of order N (Transform length) equal to 16 that suitable for

VLSI Implementation.

Fig.1.1. Block diagram of Discrete Fractional Fourier Transform

DFrFT

Input Samples

f (x)

Input Rotation Angle α

Rotated Samples f α(x)



1.3. Literature Survey

In this section the research of many authors for generalization of conventional

Fourier transform, its discrete version and the applications has been discussed. The

research on fractional Fourier transform has taken its momentum since the year of

1972, some of them has been briefly highlighted here.

In the year of 1972, James H. McClellan and Thomas has represented the DFT

as a linear Transformation and found the Eigen values {1, -1, j, -j} and their

multiplicities [1]. In this paper, it has been stated the possibility of implementation of

DFT by finding the orthogonal Eigen vector basis which has many entries as zeros

and ones only. Such Eigen vectors structure is better with the comparison of FFT.

Namias [2] first introduced the Fractional order of Fourier Transform in 1980. Here

the integral transform has been used for the construction of fractional order Fourier

transform, which has been applied in quantum mechanics for describing quantum

mechanical dynamics of electrons in time varying magnetic field.

In the applications such as linear algebra and matrix, B. W. Dickinson

reported his work in 1982 [3]. In this publication Dickinson analyzed the Eigen

vectors with the help of commuting matrices and they also efficiently computed

fractional powers of DFT. The new multiplexing and transform coding with the use of

this fractionalized DFT has been suggested by them. A couple of decades later L. B.

Almeria interpreted this fractional Fourier transform as rotation operator that rotates

the signal in time-frequency plane. Before publication in [4] the FrFT remained as

unknown by Signal Processing Community. Almedia introduced some properties of

the FrFT and also related this Fractional Fourier Transform with other time-frequency

representations as Wigner distribution, the short time Fourier transform, ambiguity

function, and the spectrogram.

In 1994, H. M. Ozaktas introduced applications of FrFT in [5] by interpreting

Fractional Fourier Transform as time-frequency representation. The convolution,

filtering and multiplexing applications that are useful in optical information

processing are covered in this work. In his filtering application he explained how to



remove the noise that may overlap in both conventional space and frequency domain

but not in the fractional domain.

B. Santhanam represented the DFrFT as angular generalization of DFT in [6].

In this work the angular parameter values of 00 and 3600 as identity operation, and 900

as DFT Operation are presented by him. He presented the DFrFT signal as equivalent

to mixture of signal, its DFT, time inversion of the signal and it’s DFT. Even by the

present of discrete version of FrFT, there is lot of demand for fast computational

algorithm. Ozaktas presented the algorithm that computes N points DFrFT in O (N log

N). But this algorithm of discrete fractional Fourier transform not satisfied the all

properties of FrFT, and results are not same as continuous Fractional Fourier

Transform. The Fourier transform and Fractional Fourier transform are related by the

A. I. Zayed in [8] for understanding properties and to find its application in the areas

where the ordinary Fourier transform have been used.

Since last two decades researchers have been trying to get most efficient and

fast algorithm for computation of discrete fractional Fourier transform. The

researchers have fallowed three different approaches to define DFrFT. B. Almedia[4],

B. Santhanam [6], J. H. Mc Clellan[9] , N. Laurenti [10], G. cariolaro [11] are

presented the DFrFT by liner weighted-type DFrFT. T. Erseghe [12], Peter K [13], A.

Bultheel[14], Z. Xinghao, T.Ran [15] are defined the DFrFT by sampling type. The

other type of definition for DFrFT is using discrete hermite-Gaussian functions. This

definition which only have ability to be a legitimate is emerged with the work of

Candan in [16],[17],[18], Soo-Chang Pei, M. H. Yeh and C. C. Tseng in [19], [20],

[21], [22], [23], [24], [25], [26].

The architecture of configurable centered discrete fractional Fourier transform

processor has been presented in [27] by P. sinha and S. Sarkar. This is array type

architecture. For an N point DFrFT hardware complexity is order of N2 and the clock

cycles are required in the order of 11+ (3N + 2 log2N).

The Architecture of CORDIC for computation of trigonometric functions is

presented in [28] by K. C. Ray. This computes using only adders rather than the



multipliers. In our architecture we use this architecture for trigonometric

computations.

The applications of this DFrFT are presented in [29], [33], [31]. In these

applications authors discussed the optical, signal and image processing applications

like image encryption, Image registration and biomedical signal detection.

1.4. Contribution to this Thesis

In this thesis, a new VLSI architecture for implementing DFrFT has been

proposed. This proposed architecture has been designed using verilogHDL. This

design has been simulated and implemented targeting a Field Programmable Gate

array (FPGA) device XLV5LX110T using Xilinx-ISE simulator and XST synthesis

tool. In this thesis, the various properties of DFrFt have been simulated using

MATLAB.

1.5. Thesis Outline

Chapter 1: In this Chapter, the brief review of various literatures has been presented

along with the motivation and objective of this thesis.

Chapter 2: The definitions of Continuous fractional Fourier Transform, Discrete

Fractional Fourier Transform and its different interpretations are discussed here. The

observations of the properties of fractional Fourier Transform through MATLAB

Simulations are shown in this chapter.

Chapter 3: The details of selected discrete fractional Fourier transform definition for

the implementation of architecture have been presented.

Chapter 4: The details of the proposed architecture on DFrFT have been discussed.



Chapter 5: The Xilinx simulation results for 16 point DFrFT and its implementation

results are presented in this chapter, which also concludes this thesis and highlighted

the future scope of this work.



Chapter 2

Mathematical Background

he mathematical tool for generalized Fourier transform have been emerging

since past three decades i.e. the generalized Fourier transforms is interpreted

in many ways like decomposing the signal in terms of chirps [02], rotation

of a signal in time-frequency plane [06] and fractionalizing Fourier transform

operation [20]. Its linear integral kernel gives the flexibility for the applications of

Fourier Transform. This Fractionalized Fourier transform theory has number of

applications in many domains by having conventional Fourier transform as the special

case. In this chapter, discussion has been made for the different interpretations of this

fractional Fourier transform, its discretized form and properties, since the computation

of discrete fractional Fourier transform requires trigonometric or exponential

functions, which can be computed using well known CORDIC algorithm. At the end

of this chapter, the basic on CORDIC and its essential for computing DFrFT has been

highlighted.

2.1. Continuous Fractional Fourier Transform

In 1929, a transform kernel which has the Hermite Gaussian functions as eigen

functions is discussed by wiener [33]. In 1956 this transformation related to matrices

by Gujnand [33]. Later on, this concept has been developed by many researchers as

Bragmann and Candan in 1961v [39], Khare in 1971 [39], Bruijin in 1973 [39],

T



Namias in 1980 [02]. During this generalization process this fractional Fourier

transform have multiple definitions like Liner integral transform, Fractional powers of

Fourier transform, Relation in time frequency plane etc.

2.1.1. Linear Integral Transform:

The fractional Fourier transform with a linear kernel Ka(x, xa) of the ath order

for the function f(x) is defined as

Where the kernel

And α= (aπ)/2

For the interval 0 < |a| < 2

Here, the sgn(.) is signum function

This transform transfers the signal from domain x to the domain xa.

Depending upon the value of a the kernel have been changes as fallowing

Except for the fractional values that are integer multiples of two, the magnitude of the

kernel simplifies to

(2.1)

(2.2)



If the value of ‘a’ is integer multiple of four, then the kernel un-affect the input signal.

The fractional Fourier transform becomes as an identity operator.

If the value of ‘a’ is integer multiple of ±2, then this integral transform turns as an

time inversion operator.

For different values of ‘a’, transform kernel Ka have different forms, i.e

(i) For a=0, the transform kernel turns as an identity operation. As a 0,

means as a 0, cot α, sin α approaches to and α respectively. With the

sense of generalized functions [40]

And (2.1) Reduces to

(ii) For a=1, the fractional Fourier transform is same as Fourier transform

(iii) For a=2 the FrFT operation makes the signal into time inversion

With this expression we have been know that, when the transform order is

zero the fractional Fourier transform changes to simple identity operation. If the

(2.3)

(2.4)

(2.5)

(2.6)



transformation order is one, then the fractional Fourier transform changes to the

conventional Fourier transform. If the transform order of FrFT is two then the

transform operator performs a time inversion operation. As the fractional transform

order approaches to the three this linear integral transform becomes inverse Fourier

transform operator. Finally if the order of FrFT is four, then the operator becomes

again an identity operator.

2.1.2. Fractional Powers of Fourier Transform:

In the interpretation, fractional powers of Fourier transform it decomposes the

input signal in terms of Hermite-Gaussian function. The Hermite Gaussian function is

also known as Eigen function of conventional Fourier transform. This operator is

linear and defined as

Here Ψl (x) is lth order Hermite Gaussian function, λl is the corresponding Eigen

value.

For an input function f(x), the fractional Fourier transform with fractional order ‘a’ is

obtained by decomposing the signal in terms of Hermite Gaussian function as

By taking ath order Fourier transform

(2.7)

(2.8)

(2.9)



From equations (2.8) and (2.9) the kernel of Fractional Fourier transform is extracted

as

Ψl(x) – is defined as Hermite-Gaussian function of order l.

With the use of Hermite-Gaussian polynomials properties

The relation for Hermite-Gaussian function is

Thus the discrete Hermite Gaussian functions are known to be Eigen functions of

FrFT.

This interpretation became most popular than the other interpretation and this

definition have attracted the researchers attention for the discretizing the fractional

Fourier transform, which has to be a legitimate definition by satisfying the many

properties like integer orders, inverse, unitary, index additive, commutative, linearity

etc.

(2.10)

(2.11)

(2.12)

(2.13)

(2.14)



2.1.3. Rotation in Time-Frequency Plane:

The FrFT is directly defined as Rotation of a signal in time-Frequency Plane.

For the ath order fractional Fourier transform the transform matrix is

This a two dimensional rotation matrix in time-frequency plane, which rotates

Wigner distribution of a signal in clock wise direction by an angle α, where α = (aπ)/2

in time-frequency plane as [35]

The rotated Wigner distribution (W) in time-frequency plane for angle α, which

transforms the Wigner distribution from u-domain to ua-domain is equivalent to the

fractional Fourier transform of the signal in u-domain for fractional value 'a’,

where α = (aπ)/2

The relation between fractional Fourier transform and time-frequency plane is

2.2. Discrete Fractional Fourier Transform

Unlike Discrete Fourier Transform, The Fractional Fourier Transform has

many definitions. Further continuous fractional Fourier transform has been discretized

for digital computation. The first work on discrete fractional Fourier transform

(DFrFT) is claimed by santhanam[6] in 1995. After that many researchers are trying

to discretize this linear integral transform. Based on the method used to discrete the

FrFT, the definitions are mainly divided into various types such as direct form,

Improved Sampling, Linear Combination and Eigen vector decomposition. Here we

(2.15)



discuss about the definitions briefly. Among these definitions, the eigen vector

decomposition is popular because of its ability to satisfy many properties which has

been presented in subsequent subsections.

2.2.1. Direct form DFrFT:

In this method, the DFrFT is derived by taking samples directly from

continuous fractional Fourier transform. But with this definition it loses important

properties like unitary property, reversibility, additive, and closed form.

2.2.2. Improved Sampling Type DFrFT:

In this method, the sampling of present mathematical equation of continuous

fractional Fourier transform is properly achieved. In this type the required DFrFT

computation time is very small, but it not satisfying the orthogonal and additive

properties. Because of rapid oscillations of kernel it required large number of samples.

Especially when the transform order approaches 0 or ±2 too many number of samples

are required.

2.2.3. Linear Combination Type DFrFT:

This definition is derived based on the linear combination of identity operator,

Discrete Fourier transform, time inverse operation and inverse discrete Fourier

transform. This definition is interpreted as rotation of a signal in time-frequency

plane. This definition satisfies the orthogonal, additive and reversibility properties but

the results are not matching with the continuous fractional Fourier transform. The

mathematical expression for this definition is



Where

2.2.4. Eigen vector Decomposition Type DFrFT:

This is defined in terms of particular set of Eigen vectors. This Eigen vectors

are discrete version of the continuous Hermite-Gaussian functions. This definition

satisfies the important properties such as unitary, index additive, reduction to DFT

when order is equal to unity and approximation of Continuous FrFT.

The Properties of the Eigen vector decomposition type discrete Fractional

Fourier transform and their corresponding mathematical forms are as in fallowing

Table-2.1

Table-2.1: Mathematical expression for the properties of

discrete fractional Fourier transform

Inverse (Fa)-1 F-a

Unitary (Fa)-1 (Fa)H

Index additive Fa2 Fa1 Fa1+a2

Commutative Fa1 Fa2 Fa2 Fa1

Associative Fa3 (Fa2 Fa1) (Fa3 Fa2) Fa1

Linearity Fa [u f1 (x)+ v f2 (x)] Fa1 [u f1 (x)]+ Fa [vf2 (x)]

The DFrFT for N pint is as fallows [17]



Where uk[n] is kth discrete Hermite-Gaussian function. The discrete values of

continuous Hermite-Gaussian function ψk(v)are approximated by using eigen vectors

of commuting matrix S. The N point DFrFT Matrix for rotation angle α is defined as

Fα = U E UT

Where U is discrete Hermite-Gaussian matrix consists of discrete Hermite-

Gaussian functions as in the fallowing equation

and ‘E’ is a diagonal matrix that consist of the eigen values e-j0α, e-j1α, e-j2α,..... e-j(N-2)α,

e-jMα of DFrFT matrix Fα as diagonal elements.

The response of an N-point DFrFT ‘fα[n]’, for N input samples f[n] with

rotation angle α can be calculated by fα[n]= Fα f[n]. i.e.

fαN×1=UN×N*(EN×N*(UTN×N*fN×1)). Here * indicates matrix multiplication operation.

For the proposed architecture the matrix E is replaced with a column matrix C that

contains the Eigen values of DFrFT for given input angle α and middle matrix

multiplication is replaced by an array multiplication. The modified expression is

fαN×1=UN×N*(CN×1×(UTN×N*fN×1)), Where‘×’ indicates the array multiplication

operation.

Where, k ≠ N, for N odd k ≠ N-1, for N even

Fα = uk[n] e-jαk uTk [n] Σ

N

k=0

M=N; for N even

U=

u0[0] u1[0] . . uN-2[0] uM[0] u0[1] u1[1] . . uN-2[1] uM[1] u0[2] u1[2] . . uN-2[2] uM[2] . . . . . . . . u0[N] u1[N] . . uN-2[N] uM[N]

Here M=N-1; for N odd



The fallowing comparative study shows the eigen vector decomposition

method is the legitimate approach [39].

Table-2.2: Comparison between the three different definitions of discrete fractional

Fourier transform

Improved sampling

type

Linear

Combination Type

Eigen vector

Decomposition type

Unitarity No Yes Yes

Additive No Yes Yes

Approximation Yes No Yes

Complexity O(NlogN) O(NlogN) O(N2)

Closed-form Yes YEs No

The calculation of discrete Hermite Gaussian matrix and the algorithm for

calculation of DFrFT matrix are explained detail in the Chapter 3, which has been

used for our proposed architecture.



2.3. Illustration of Discrete Fractional Fourier Transform

Properties using MATLAB Simulations:

Fractional Fourier Transform is linear but not shift-invariant. It fallows the

properties like integer property, index property, inverse property, index additive,

Commutative, associative properties. We illustrated these properties are illustrates

through the MATLAB simulations. We simulated the FrFT with a sinusoidal signal

sin (π *x) as an input..

Linearity property: The simulation outputs for each case have been shown in

Fig.2.1, which highlights the

linearity property i.e.

F 0.2 [2f1 (x)+ 3f2 (x)] F 0.2 [2f1 (x)]

F 0.2 [3f2 (x)] ] F 0.2 [2f1 (x)]+ F 0.2 [3f2 (x)]

Fig.2.1. Illustration of linearity Property using MATLAB Simulations for



Inverse Property: To verify Inverse property we used a signal f (x) = sin(π*x). The

simulation outputs for each case have been shown in Fig.2.2, which highlights the

Inverse property i.e. [F 0.1 [f (x)]]-1 = F -0.1 [f (x)]

[F 0.1 [f (x)]]-1 F -0.1 [f (x)]

Fig.2.2. Illustration of Inverse Property using MATLAB Simulations for sinusoidal

signal sin (π *x)

Additive Property: To verify Index additive property we used a signal f (x) =

sin(π*x). The simulation outputs for each case have been shown in Fig.2.3, which

highlights the Index additive property i.e.

F 0.2 [f (x)] F 0.2 [F 0.8 [f (x)] ]

F 1 [f (x)] ]

Fig.2.3. Illustration of Index additive Property using MATLAB Simulations for

sinusoidal signal sin (π *x)



Index and Integer property: To verify Index and integer property we used a signal f

(x) = sin(π*x). The simulation outputs for each case have been shown in fig.2.4,

which highlights the Index and

integer property

F 0 [f (x)] F 1 [f (x)]

F 2 [f (x)] F 3 [f (x)]

F 4 [f (x)]

Fig.2.4. Illustration of Index and Integer Properties using MATLAB Simulations for




Commutative Property: To verify Commutative property we used a signal f (x) =


highlights the Commutative property i.e.

F 0.1 [f (x)] F 0.9 [F 0.1 [f (x)] ]

F 0.9 [f (x)] F 0.1 [F 0.9 [f (x)] ]

F 1 [f (x)]

Fig.2.5. Illustration of Commutative Property using MATLAB Simulations for




Associative property: To verify Associative property we used a signal f (x) =


highlights the Associative property i.e.

F 0.7 [F 0.2 [F 0.1 [f (x)] ] ] = F 0.1 [F 0.7 [F 0.2 [f (x)] ] ] = F 1 [f (x)] ]

F 0.1 [f (x)] F 0.2 [F 0.1 [f (x)] ]

F 0.7 [F 0.2 [F 0.1 [f (x)] ] ] F 1 [f (x)] ]

F 0.7 [F 0.2 [f (x)] ] F 0.1 [F 0.7 [F 0.2 [f (x)] ] ]

Fig.2.6. Illustration of Associative Property using MATLAB Simulations for




2.4 CORDIC

As has been presented in previous section, the DFrFT needs the computational

intensive trigonometric function, which can be accomplished using a well known

hardware efficient CORDIC ( Co-ordinate rotational Digital Computer) processor.

Hence, the CORDIC which is one of the basic building block of the proposed

architecture as presented here. In CORDIC all the trigonometric computations are

performed with the use of only additions and subtractions [28].

The generalized CORDIC equation is

= cos sinsin cos

In this algorithm, a vector point (x, y) have been rotated through required angle (θ)

where – π/2 ≤ θ ≤ π/2 is divided in to subsections by splitting the target angle in terms

of small angles. θ = α0 ± α1 ± α2 ± . . . ± αi ± . . . ± αb-1 ,

Where b indicates the number of bit precision and i=0 to b-1.

Precisely

∑ .di αi

Where αi = tan-1 (2-i) and di { -1,1}.

With maintaining the total angle equal θ, the signs of elementary angles are

considered. So that

by separating the cosine terms



Where

Have to scale the resultant values by 1.6473 for 16 iterations

The CORDIC algorithm can be implemented using either iterative or pipelined

architecture. The graphical representation for a signle stage CORDIC is represented in

Fig.2.7. it representing separately for both circular CORDIC and Linear CORDIC.

Here, X and Y are input vector registers and Z remaining angle and a hard shifter. ai is

micro rotation angle in each iteration or stage.

Fig. 2.7 Graphical representation of CORDIC

(a) Circular CORDIC (b) Linear CORDIC

The value of n varies from 0 to N, thus angle is vary from 0 to 2π. So

CORDIC should be able to compute for these entire angles in this range. A

conventional CORDIC algorithm can compute for the angles in the range -π/2 to π/2.

Here normalized angle format has been used to cover all angles from 0 to 2π. The

quadrant transformation for maintaining 0 to 2π rotations has been explained in Fig.

2.8.



Fig. 2.8. Normalized angle representation for CORDIC

The binary representation format for the residue angle (Z) is chosen in such a

way it had a range of 0 to 2π covering all the quadrants completely. The

representation of Z is in the format of -π, π/2, π/4. . . π/2b-1 where b is the word length.

For the easy of identifying the quadrant relevant to the rotation angle by simply

observing first two bits from MSB side.

First two MSBs 00,01,10,11 represent the 1st, 2nd, 3rd and 4th quadrants where

residue angle Z lies. The transformation from 2nd and 3rd to 4th and 1st quadrant

respectively by replacing first most significant bits with second most significant, i.e.

01-11 and 10-00 where CORDIC can compute for the vectors in its range. The output

vectors are sending back to its original quadrant by assigning proper sign to the

vectors. The equations of iterative CORDIC are

This CORDIC architecture is well suitable for trigonometric computations in

our architecture.



Chapter 3

DFrFT using Discrete Hermite-

Gaussian Functions

ny discrete fractional Fourier transform must satisfy three properties that

are unitary, index additive and reduction to DFT when order is 1. Many

authors have recommended the DFrFT with the use of discrete Hermite-

Gaussian, because of its ability to be a legitimate definition. In this section the work

presented in [21] for this definition has been presented. This definition must satisfy

the fallowing three properties

1. Unitary property: (Fa)-1 = F-a = (Fa) §, where (.) § denotes Hermite conjugation.

2. Index additive: Fa1 Fa2 = Fa2 F a1 = Fa1+a2.

3. Reduction to ordinary transform when a=1: F1 = F, where F is a DFT Matrix.

With the action of desecrating the equation

Where ψk(u) is the kth order Hermite-Gaussian function,

Hk is the kth order Hermite polynomial. Rotation angle α= aπ/2

By assuming pk[n] as an arbitrary orthonormal eigen vector set of the N×N DFT

matrix and λk is corresponding eigen value. Then the discrete analogous of (3.1) is

A

Kα (u,v) = Σ ∞

k=0

ψk(v) e-jαk ψk(u) (3.1)



Fa is DFrFT matrix, and λk is corresponding eigen vector of this DFrFT

Here two ambiguities have been settled. Among them, having only four distinct Eigen

values {1, -1, j, -j} to the DFT matrix is first ambiguity. Because of this the

degenerated eigen values are not unique. This problem have been settle down by

choosing a common Eigen set of the commuting matrices S and F as the same

ambiguity that resolved by taking Hermite Gaussian functions in continuous FrFT

case. Taking fractional power which is not having single value is another ambiguity.

This problem have been avoided by taking (λk)a = exp (-jπak/2).

Now the expression for the computation of DFrFT is changed to

The S matrix is defined as

2 1 0 . . 0 1

1 2 cos2

4 1 . . 0 0

0 1 2 cos 22

4 . . 0 0: : : . : :

1 0 0 . . 1 2 cos2

1 4

To select correct eigen vector set for the commuting matrices S and F, the property of

eigen vector of DFT matrices is used. That is the eigen vectors of DFT matrices are

either even or odd sequences. The eigen vectors are orthogonal to each other because

of the matrix S is real and symmetric. Here a matrix P is introduced which splits a

function f[n] into its even and odd sequences. The matrix P of 16×16 is defined as

pk[m] (λk)a pk[n] Fa [m, n] = Σ N-1

k=0

(3.2)

uk[m] e-(jπka)/2 uk[n] Fa [m, n] = Σ N-1

k=0

(3.2)



P =

√2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 1 0 0 0 0 0 0 0 0 0 0 0 0 0 10 0 1 0 0 0 0 0 0 0 0 0 0 0 1 00 0 0 1 0 0 0 0 0 0 0 0 0 1 0 00 0 0 0 1 0 0 0 0 0 0 0 1 0 0 00 0 0 0 0 1 0 0 0 0 0 1 0 0 0 00 0 0 0 0 0 1 0 0 0 1 0 0 0 0 00 0 0 0 0 0 0 1 0 1 0 0 0 0 0 00 0 0 0 0 0 0 0 √2 0 0 0 0 0 0 00 0 0 0 0 0 0 1 0 1 0 0 0 0 0 00 0 0 0 0 0 1 0 0 0 1 0 0 0 0 00 0 0 0 0 1 0 0 0 0 0 1 0 0 0 00 0 0 0 1 0 0 0 0 0 0 0 1 0 0 00 0 0 1 0 0 0 0 0 0 0 0 0 1 0 00 0 1 0 0 0 0 0 0 0 0 0 0 0 1 00 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Since the matrix S contains only even or odd sequences the Eigen vectors of S are the

odd and even extension of the PSP-1 which is in the form

PSP-1 = Ev 00 Od

Based on the number of sign changes of the discrete Hermite Gaussian functions we

arrange the selected Eigen vectors in correspond to the discrete Hermite Gaussian

function. The arrangement of these Eigen vectors is as fallows.

1/√2 √2 êk[0] êk[1] .. êk[N/2] : êk[N/2] .. êk[1] √2êk[0]

Where êk is Eigen vector of Ev with k zero crossings.

Similarly, odd eigenvectors of are derived from the eigenvectors of by zero padding

and transformation.

Candan [17] presented an algorithm for the calculation of DFrFT which has been

described in fallowing steps.

1. Generating matrices S and P.

2. Generate Ev and Od matrices.

k zero crossings k zero crossings



3. Find eigen values and eigen vectors of Ev and Od.

4. Sort the Eigen vectors of Ev (Od) in the descending order of eigen values of

Ev (Od) and denote the sorted eigenvectors as ek (ok).

5. Let u2k[n] = p [ ekT | 0 . . . 0]T. Let u2k+1[n] = P [0 . . . 0 | ok

T]T

6. Define

uk[m] e-(jπka)/2 uk[n] Fa [m, n] = ΣN-1

k=0



Chapter 4

VLSI Architecture for Discrete

Fractional Fourier Transform

he proposed architecture is composed of three levels. The input data to be

process is flow through all the three serially connected levels as shown in

Fig.4.1.

The level-I performs two mathematical operations, one is calculation of eigen

values for given input rotation angle and Another is calculation of the response of

matrix UT for input samples f. These two operations are carried out by two blocks of

T

Fig.4.1: Block diagram of the DFrFT

Level-II

Level-I

Level-III

Rotated input ‘fα’

E

Input ‘f ’ Rotation angle (α)

C U1

U2



level-I named as C and U1. This level passes two computed results that are matrix C

and UT*f to the level-II, which execute the multiplication of eigen values with the

response of U1 block and feeds the product C×UT*f to the level-III. Here * indicates

matrix multiplication operation and ‘×’ indicates the array multiplication operation. In

this level we get the rotated input samples fα = U*C×UT*f as an output, by the act of

matrix multiplication between level-III input and Hermite-Gaussian matrix U.

If input samples are complex values (f=a+jb), have to calculate the response of

U1 block separately for both real and imaginary parts, so that here two U1 blocks are

needed. Similarly for any type of input samples f, two U2 blocks are required to

process Level-III real and imaginary inputs separately. For this reason in Fig.4.1 the

blocks U1 and U2 are denoted as multi-blocks. In Fig. 4.4, the data flow between

these blocks is given in detail.

The time period between two successive input samples f and the time period

between two successive output results fα are same. The rest of this section presents the

detail description of each level of proposed architecture.


Level-I:

In an N-point DFrFT, this level-I is partitioned into two parts. The first part

performs the calculation of Eigen values for given rotation angle (α) using a block

named as C in the architecture as shown in Fig.4.2.

This block receives an angle for every N clock cycles and it computes

corresponding N complex conjugated Eigen values. The results of block C for given

angle α are ej0α, ej1α, ej2α,….ej(N-2)α, ejMα, where M=N-1, for N odd and M=N, for N

even.



The architecture for calculation of Eigen values requires two clocks, i.e.

clock1 (Clk) having the frequency same as sampling frequency and another clock2

(Clkn) having 1/Nth of frequency of clock1. With active high enable signal, the

counter counts in sequence …0, 1, 2,…N-2, M, 0, 1, 2... . This counter output is

connected to a multiplier which took rotation angle as another input through a register

‘R1’ that receives clock2. The results of multiplier 0, α, 2α… (N-2)α, Mα; M=N-1 for

N odd, M=N for N even are fed to the pipelined CORDIC (CO-ordinate Rotation

DIgital Computer) by another register ‘R2’. The pipelined CORDIC is shown in

fig.4.2.b, where the architecture for each stage of pipelined rotational CORDIC is

given in Fig.4.2.c

Fig. 4.2.b: Architecture of pipelined CORDIC.

Counter Counts (0 – N‐1); If N Odd

Counts (0 – N‐2, N); If N Even Rotation angle

(α)

C.E

R1

Clkn Clk

Clk

Fig. 4.2a: Calculation of Eigen values of Level-I.

Output (Real Part)

Output (Imaginary Part)

Enable

C

*R2

Imaginary Part

Real Part

Clk

Pipelined CORDIC (Calculates Sin & Cos Values)

R31 R41 RN1

ClkClk Clk R32 R42 RN2

Clk Clk Clk

Clkn

Clk



Fig. 4.2.c: Architecture of Single stage pipelined CORDIC.

The CORDIC [15] calculates the cosine and sine values of its input angles,

which are real and imaginary parts of complex conjugated Eigen values for given

rotation angle. The real and imaginary parts of computed results pass to the output

real part port and output imaginary part port respectively through a set of registers as

shown in fig.4.2. The requirement of these registers has been presented at the end of

Level-I explanation.

The block ‘U1’ of second part of level-I multiplies input values f with the

matrix UT. This part consist of a mod-N counter, ‘N’ number of ROMs with N

address locations per each ROM, N Multipliers, N accumulators, one N to 1

Multiplexer and set of buffers. The data flow in this part is shown in Fig.4.3. As in

block ‘C’ this ‘U1’block also operates with two clocks named clock1 (clk) and clock2

(clkn). The N rows of the matrix UT are stored in N ROMs. The arrangement of rows

of matrix UT in ROM is shown in Table-4.1.

TABLE-4.1

ARRANGEMENT OF THE ELEMENTS OF MATRIX “UT” IN ROMS

Address Location ROM 1 ROM 2 . ROM N-1 ROM N 0 UT

R+1,1 UTR+2,1 . UT

R-1,1 UT R,1

1 UTR+1,2 UT

R+2,2 . UTR-1,2 UT

R,2 . . . . . .

N-1 UTR+1,N UT

R+2,N . UTR-1,N UT

R,N

UTk,l – Indicates the element belongs to kth row and lth column of UT Matrix, R is the

value of N/2 that’s Rounded towards Zero



The ROMs are accessed with a ring counter with active high enable signal as shown

in Fig.4.3.

All the data of corresponding address locations of N ROMs is preceded to N

multipliers with sampled input f[n] as another input. At every clock1 cycle, all the N

multipliers multiplies sampled input with output values of the corresponding N

ROMs, and forwards these results to their N accumulators through registers as shown

Clk

n

Fig. 4.3: The Data flow for part II of level-I

Accumulator2 Accumulator N

Cou

nter

R22

Clk

Accumulator1

R5

R4

Clk

Clk

Clr

Clk

Counter Out

*

U1

Enab

le

ROM

2

01 2 .

. N‐1

ROM

1

01 2 .

. N‐1

R21

*Clk Clk Clk

ClrClk

Clk Clr

ROM

N

0 1 2 .

. N‐1

* R2N

R31 R32 Clkn Clkn Clkn R3N

R1

N to 1 MUX

Clk

C.E

R(C

i+1)

Clk

f

f(n)

*UT

Clk



in Fig.4.3. Each of these N accumulators performs addition operation between its

input and output values on every clock1 cycle.

When all these N accumulators adds their N set of inputs, these accumulators

sends the resultant data to next stage and clears the accumulators to add N set of fresh

inputs. The N accumulator outputs passes through the Nto1 multiplexer to set of

registers that are operate with clock1 (clk). The multiplexer selection line is connected

to counter output. The multiplexer inputs are connected to the N accumulator outputs

in such a way that the 1st, 2nd, 3rd….Nth valid output values of the Nto1 multiplexer

should be the 1st, 2nd, 3rd….Nth accumulator output values.

In level-II we have to execute a mathematical operation in between the outputs

of block C and block U1. So that it is necessary to forward the computed results of

block C and block U1 at the same time to level-II, but the latency of block C varies

with the number of pipelines used in CORDIC and the latency of block U1 depends

upon the value of N.

In order to maintain same latency for both the blocks, it is necessary to insert a

set of registers either in block C or block U1. The number of registers is depends upon

the values of N and Ci, where Ci is number of pipelines used in CORDIC. If N>Ci–1,

then the N+1–Ci number of registers have to add in block C, addition of register set in

block U1 is not required and the latency is L=N+3. If N<Ci–1, then the Ci–(N+1)

number of registers have to add at the output of multiplexer in block U1, addition of

register set in block C is not required and the latency is L= Ci+2. If N=Ci+1, then the

latency of both the blocks is same, register set is not required in both C, U1 blocks

and latency is L=N+3=Ci+2. The data flow from this block to next blocks is shown in

Fig.4.4.




Level-II:

The Level-II has a complex multiplier followed by two serial in parallel out

shift registers and a set of 2N Registers. Block E of this level receives the real,

imaginary parts of complex conjugated eigen values form the block C through its

Real2(R2), Imag.2(I2) ports respectively and the response of block U1 for input

samples ‘f’ is received by its another two input ports Real1(R1), Imag.1(I1). The

Block diagram is shown in fig.4.5.

‘U1’

Enable

Clkn

Fig. 4.4: Data flow Diagram of DFRFT

Real (fα[n])

Imag. (fα[n])

‘U2’ for Real Part

‘U2’ for Imag. Part

E

Count r1 r2 rN i1 i2 iN Count

‘C’

Imag.2

Clk En

able

Rotation Angle α

Real 2

Imag.(f) ‘U1’

Clk

Real1 Counter out Counter out

Real(f)

Enable

Clk

Imag.1

Clkn

Clkn

C



The complex multiplier of this block is different from the ordinary complex

numbers multiplier. This complex multiplier performs the multiplication between the

eigen values and the results of block U1 by taking the complex conjugate of eigen

values and the results of block U1 as inputs. For every clock cycle the complex

multiplier multiplies a new pair of complex numbers. The outputs of complex

multiplier out1, out2 release the results of mathematical computations (R1×R2) +

(I1×I2), (R2×I1) – (R1×I2) respectively.

The two resultant outputs, one is real part and another imaginary part are

connected to two serial in parallel out shift registers. The number of registers required

for each shift register is N-1. For every N-1 clock cycles the complex multiplier

passes the N-1 results to this serial in parallel out shift register. The shift register

Real1(R1) Real2(R2) Imag.2(I2) Imag.1(I1)

R3 R4

+

Clk

Clk

Clkn

R2 R1 Clk

Clkn

Out1 Out2 E

Clk

Real Part Output Imaginary Part Output

‘2N’ Number of Registers

Fig.4.5: Complex Multiplier with shifting operation of Level-II

Clk

–

× × × ×

Serial in Parallel out Shift Register

Cl k Cl k Serial in Parallel out Shift Register



fallowed by a set of 2N registers. The first and (N+1)th register are connected to real

and imaginary outputs of complex multiplier respectively. Remaining 2 to N and N+2

to 2N registers are connected to the N-1outputs of first shift register (corresponding to

out1) and N-1 outputs of second shift register (corresponding to out2) respectively as

shown in Fig.4.5. But these registers operate with the clock2, unlike the shift registers,

which operate by the clock1.


Level-III:

This level-III performs another matrix multiplication operation on the outputs

of level II. The signal flow graph is shown in Fig.3.6.

U2

Input 1

Count Input

Input 2 Input N

Data 1 Data 2 Data N

Address

Adder

fα Fig. 4.6: Signal Flow graph for level-III

ROM 1

0 1 2 . .

N‐1

ROM 2

01 2 . .

N‐1

ROM N 0 1 2 . .

N‐1

* * *

Address Address



This level has N ROMs, each ROM stores a column of matrix U of size N×N.

Because of accessing all ROMs using the counter output of block U1, to maintain the

synchronous between ROMs output values and input values of multiplier the

arrangement of matrix elements in ROMs is as fallows, the data of address 0 of all

ROMs contain the rth row of matrix U. where r is the remainder of (N+L)/N. The

address1 of N ROMs stores the next row of the matrix, and remaining locations of N

ROMs fallows the same sequence. By fallowing this sequence the (r-1)th memory

location stores the first row of the matrix. When counter counts k, all the data in kth

memory locations of N ROMs multiplies with output values of level-II as shown in

the Fig.4.6.

This N resultant multiplier outputs are added by using N-1 adders and send out

as rotated input samples in time-frequency plane with given angle α.



Chapter 5

Results and Discussion

he proposed architecture discussed in the previous section had been

designed using verilogHDL for the input of order N equal to Sixteen The

design has been simulated using Xilinx-ISE 10.1i simulator with sinusoidal

input samples f(n) as test vector.

For the sake of simplicity and to realize the outputs of the design, the integer

values for the inputs have been chosen which are representing with sixteen bits (one

bit for sign and Six bits for integer value). The internal precession of each block has

been chosen according to avoid maximum truncation error.

Finally the outputs are given in 16-bit format (where one bit for sign, Six bits

for integer and eleven bits for fractional value). Similarly for the fractional value α,

the format has been chosen with binary weightage as [-π . . . ]. In this case

b=16. The hardware complexity of the proposed design for the N-point of DFrFT has

been summarized in Table-5.1. This design is based on pipelined approach; hence the

design requires latency period L+N+1, where L is Latency of the CORDIC.

T

π 2b-1

π 23

π 22

π 21



TABLE-5.1

HARDWARE REQUIREMENT FOR N-POINT DFRFT

Component Name Number of ComponentsN×16NbitROM 2

Multipliers 4N+5 Adders/Subtractors 4N+ Adders in CORDIC N to 1 Multiplexers 2

Counters 2 Registers 10N+6+Ci+2×(|N+1-Ci|)

Simulation results: The simulation Shown in appendix-A.

The DFrFT presented in chapter 3 has been simulated using MATLAB for

various values of α with a test signal of sinusoidal. The interpretation of these results

in time-frequency plane is shown in the Fig. 5.1. The simulation outputs are shown in

Fig. 5.2 – 5.15. The proposed architecture described in chapter-4 is coded using

verilogHDL and simulated using Xilinx10.1i whose outputs are shown in appendix A

and presented in table 5.2 to 5.8 for comparison with MATLAB simulation outputs.

The comparative study shows that hardware simulation output is very close to

MATLAB simulation outputs.

f (t) / FrFT of f (t)

0

FFT of f (t)

FFT of f (-t)

f (-t) / FrFT of f (t)

0

FrFT of f (t) with α=300








Fig. 5.1 Interpretation of fractional Fourier Transform in Time Frequency Representation



The hexadecimal values of the input vector used for the simulation of Discrete Fractional Fourier transform is

f[n]={0000, 0271, 0475, 05b5, 05f7, 0532, 0387, 013f, fec1, fc79, face, fa09, fa4b,fb8b, fd90, 0000} and the corresponding equivalent input vector in decimal is f[n]= {0.0000, 1.2210, 2.2290, 2.8530, 2.9820, 2.5980, 1.7640, 0.6240, -0.6240, -1.7640, -2.5980, -2.9820, -2.8530, -2.2290, -1.2180, 0.0000}

And we simulated the DFrFT for the rotation angles (fractional values) 00(0.00), 300(0.33), 600(0.67), 900(1.00), 1200(1.33), 1500(1.67), 1800(2.00), 2100(2.33), 2400(2.67), 2700(3.00), 3000(3.33), 3300(3.67) and 3600(4.00).

Fig.5.2: Input Samples for MATLAB Simulation of DFrFT

Fig.5.3: MATLAB Simulation Result of DFrFT for α=00



TABLE-5.2

COMPARISON OF MATLAB AND XILINX-ISE SIMULATION RESULT FOR ROTATION ANGLE OF 00

Sample No.

Input Samples for both Matlab and Xilinx-ISE

Simulator

MATLAB Simulation Results for α = 00

Xilinx-ISE Simulation

Results of Proposed Architecture for α = 00

01 0000 + 0000 i 0000 + 0000 i 0000 + 0000 i

02 0271 + 0000 i 0271 + 0000 i 0270 + 0000 i

03 0475 + 0000 i 0475 + 0000 i 0474 + 0000 i

04 05b5 + 0000 i 05b5 + 0000 i 05b4 + 0000 i

05 05f7 + 0000 i 05f7 + 0000 i 05f7 + 0000 i

06 0532 + 0000 i 0532 + 0000 i 0531 + 0000 i

07 0387 + 0000 i 0387 + 0000 i 0387 + 0000 i

08 013f + 0000 i 013f + 0000 i 013f + 0000 i

09 fec1 + 0000 i fec1 + 0000 i fec1 + 0000 i

10 fc79 + 0000 i fc79 + 0000 i fc78 + 0000 i

11 face + 0000 i face + 0000 i facd + 0000 i

12 fa09 + 0000 i fa09 + 0000 i fa09 + 0000 i

13 fa4b + 0000 i fa4b + 0000 i fa4b + 0000 i

14 fb8b + 0000 i fb8b + 0000 i fb8a + 0000 i

15 fd90 + 0000 i fd90 + 0000 i fd90 + 0000 i

16 0000 + 0000 i 0000 + 0000 i ffff + 0000 i



TABLE-5.3

COMPARISON OF MATLAB AND XILINX-ISE SIMULATION RESULTS FOR ROTATION ANGLE OF 300 AND 600

Sample No.


Xilinx-ISE Simulation Results of Proposed

Architecture for α = 300




01 009d + 00e7 i 009c + 00e6 i 006b + 0005 i 006b + 00004 i

02 000e + 015e i 000e + 015d i ff4d + 00a4 i ff4c + 00a3 i

03 fe1f + 026d i fe1f + 026c i ffc0 + febd i ffbf + febc i

04 fad1 + febe i fad0 + febd i 01ac + 0003 i 01ab + 0002 i

05 ff06 + f991 i ff06 + f991 i ff4d + 032f i ff4c + 032e i

06 03c5 + fbc3 i 03c4 + fbc2 i fa9c + fd58 i fa9b + fd58 i

07 03c5 + fe6d i 03c5 + fe6d i 0318 + f88b i 0318 + f88b i

08 01b8 + ffeb i 01b8 + ffeb i 0458 + ff9f i 0457 + ff9e i

09 fea2 + ffc3 i fea1 + ffc3 i fe35 + ff58 i fe35 + ff57 i

10 fc08 + 0035 i fc07 + 0034 i f96e + 018d i f96d + 018c i

11 faa1 + 01ac i faa0+ 01ac i fca3 + 0692 i fca4 + 0692 i

12 fbdb + 04f4 i fbda + 04f3 i 0392 + 0310 i 0391 + 0310 i

13 0107 + 0543 i 0107 + 0543 i 015f + fdf6 i 015f + fdf5 i

14 0327 + 0145 i 0327 + 0144 i fefd + ff9a i fefc + ff9a i

15 016f + ff41 i 016f + ff40 i ffb6 + 0050 i ffb6 + 004f i

16 002d + ff23 i 002d + ff23 i 0021 + 0073 i 0022 + 0072 i



TABLE-5.4


Sample No.







01 ffae + 0000 i ffae + ffff i 006b + fffb i 006b + fffb i

02 0052 + 0010 i 0051 + 0010 i 0021 + ff8d i 0021 + ff8d i

03 ffae + ffde i ffae + ffde i ffb6 + ffb0 i ffb6 + ffb0 i

04 0054 + 0037 i 0053 + 0037 i fefd + 0066 i fefc + 0065 i

05 ffaa + ffaa i ffaa + ffaa i 015f + 020a i 015f + 0209 i

06 005b + 0088 i 005a + 0087 i 0392 + fcf0 i 0391 + fcef i

07 ff91 + fef4 i ff91 + fef4 i fca3 + f96e i fca3 + f96d i

08 fdc1 + f4b5 i fdc1 + f4b4 i f96e + fe73 i f96d + fe73 i

09 0000 + 0000 i 0000 + 0000 i fe35 + 00a8 i fe34 + 00a7 i

10 fdc1 + 0b4b i fdc0 + 0b4b i 0458 + 0061 i 0458 + 0061 i

11 ff91 + 010c i ff91 + 010b i 0318 + 0775 i 0318 + 0774 i

12 005b + ff78 i 005a + ff78 i fa9c + 02a8 i fa9b + 02a7 i

13 ffaa + 0056 i ffaa + 0055 i ff4d + fcd1 i ff4c + fcd1 i

14 0054 + ffc9 i 0053 + ffc8 i 01ac + fffd i 01ab + fffc i

15 ffae + 0022 i ffae + 0021 i ffc0 + 0143 i ffbf + 0143 i

16 0052 + fff0 i 0051 + ffef i ff4d + ff5c i ff4c + fff5c i



TABLE-5.5


Sample No.







01 009d + ff19 i 009d + ff18 i 0000 + 0000 i 0000 + 0000 i

02 002d + 00dd i 002d + 00dd i 0000 + 0000 i ffff + 0000 i

03 016f + 00bf i 016e + 00bf i fd90 + 0000 i fd90 + ffff i

04 0327 + febb i 0327 + febb i fb8b + 0000 i fb8a + 0000 i

05 0107 + fabd i 0107 + fabc i fa4b + 0000 i fa4a + 0000 i

06 fbdb + fb0c i fbdb + fb0c i fa09 + 0000 i fa08 + ffff i

07 faa1 + fe54 i faa1 + fe53 i face + 0000 i facd + 0000 i

08 fc08 + ffcb i fc07 + ffcb i fc79 + 0000 i fc78 + 0000 i

09 fea2 + 003d i fea1 + 003c i fec1 + 0000 i fec1 + 0000 i

10 01b8 + 0015 i 01b8 + 0015 i 013f + 0000 i 013f + ffff i

11 03c5 + 0193 i 03c5 + 0192 i 0387 + 0000 i 0387 + ffff i

12 03c5 + 043d i 03c4 + 043d i 0532 + 0000 i 0532 + 0000 i

13 ff06 + 066f i ff06 + 066e i 05f7 + 0000 i 05f7 + ffff i

14 fad1 + 0142 i fad0 + 0141 i 05b5 + 0000 i 05b5 + ffff i

15 fe1f + fd93 i fe1f + fd93 i 0475 + 0000 i 0475 + 0000 i

16 000e + fea2 i 000e + fea2 i 0271 + 0000 i 0271 + ffff i



TABLE-5.6


Sample No.







01 009d + 00e7 i 009c +00e6 i 006b + 0005 i 006b + 0004 i

02 002d + ff23 i 002d + ff22 i 0021 + 0073 i 0021 + 0072 i

03 016f + ff41 i 016e + ff40 i ffb6 + 0050 i ffb5 + 004f i

04 0327 + 0145 i 0327 + 0144 i fefd + ff9a i fefc + ff9a i

05 0107 + 0543 i 0107 + 0543 i 015f + fdf6 i 015f + fdf5 i

06 fbdb + 04f4 i fbda + 04f3 i 0392 + 0310 i 0391 + 0310 i

07 faa1 + 01ac i faa0 + 01ac i fca3 + 0692 i fca3 + 0692 i

08 fc08 + 0035 i fc08 + 0034 i f96e + 018d i f96e + 018c i

09 fea2 + ffc3 i fea1 + ffc3 i fe35 + ff58 i fe35 + ff57 i

10 01b8 + ffeb i 01b7 + ffea i 0458 + ff9f i 0457 + ff9e i

11 03c5 + fe6d i 03c5 + fe6d i 0318 + f88b i 0318 + f88b i

12 03c5 + fbc3 i 03c5 + fbc2 i fa9c + fd58 i fa9b + fd59 i

13 ff06 + f991 i ff06 + f991 i ff4d + 032f i ff4c + 032e i

14 fad1 + febe i fad0 + febd i 01ac + 0003 i 01ab + 0002 i

15 fe1f + 026d i fe1f + 026d i ffc0 + febd i ffc0 + febc i

16 000e + 015e i 000e + 015e i ff4d + 00a4 i ff4d + 00a3 i



TABLE-5.7


Sample No.







01 ffae + 0000 i ffae + ffff i 006b + fffb i 006b + fffb i

02 0052 + fff0 i 0052 + ffef i ff4d + ff5c i ff4c + ff5c i

03 ffae + 0022 i ffae + 0021 i ffc0 + 0143 i ffbf + 0143 i

04 0054 + ffc9 i 0053 + ffc8 i 01ac + fffd i 01ab + fffc i

05 ffaa + 0056 i ffaa + 0055 i ff4d + fcd1 i ff4c + fcd1 i

06 005b + ff78 i 005a + ff78 i fa9c + 02a8 i fa9b + 02a7 i

07 ff91 + 010c i ff91 + 010b i 0318 + 0775 i 0318 + 0074 i

08 fdc1 + 0b4b i fdc0 + 0b4b i 0458 + 0061 i 0458 + 0061 i

09 0000 + 0000 i 0000 + 0000 i fe35 + 00a8 i fe34 + 00a7 i

10 fdc1 + f4b5 i fdc0 + f4b4 i f96e + fe73 i f96d + fe73 i

11 ff91 + fef4 i ff91 + fef4 i fca3 + f96e i fca3 + f96d i

12 005b + 0088 i 005a + 0087 i 0392 + fcf0 i 0392 + fcf0 i

13 ffaa + ffaa i ffaa + ffaa i 015f + 020a i 015f + 020a i

14 0054 + 0037 i 0053 + 0036 i fefd + 0066 i fefc + 0065 i

15 ffae + ffde i ffae + ffde i ffb6 + ffb0 i ffb6 + ffb0 i

16 0052 + 0010 i 0051 + 0010 i 0021 + ff8d i 0021 + ff8d i



TABLE-5.8


Sample No.







01 009d + ff19 i 009d + ff18 i 0000 + 0000 i 0000 + 0000 i

02 000e + fea2 i 000e + fea1 i 0271 + 0000 i 0270 + 0000 i

03 fe1f + fd93 i fe1f + fd93 i 0475 + 0000 i 0474 + 0000 i

04 fad1 + 0142 i fad0 + 0141 i 05b5 + 0000 i 05b4 + 0000 i

05 ff06 + 066f i ff06 + 006e i 05f7 + 0000 i 05f7 + 0000 i

06 03c5 + 043d i 03c4 + 043d i 0532 + 0000 i 0531 + 0000 i

07 03c5 + 0193 i 03c5 + 0192 i 0387 + 0000 i 0387 + 0000 i

08 01b8 + 0015 i 01b8 + 0015 i 013f + 0000 i 013f + 0000 i

09 fea2 + 003d i fea1 + 003c i fec1 + 0000 i fec1 + 0000 i

10 fc08 + ffcb i fc07 + ffcb i fc79 + 0000 i fc78 + 0000 i

11 faa1 + fe54 i faa1 + fe53 i face + 0000 i facd + 0000 i

12 fbdb + fb0c i fbdb + fb0c i fa09 + 0000 i fa09 + 0000 i

13 0107 + fabd i 0107 + fabc i fa4b + 0000 i fa4b + 0000 i

14 0327 + febb i 0327 + febb i fb8b + 0000 i fb8a + 0000 i

15 016f + 00bf i 016f + 00bf i fd90 + 0000 i fd90 + 0000 i

16 002d + 00dd i 002d + 00dd i 0000 + 0000 i ffff + 0000 i



The MATLAB simulation results are presented in Fig.5.2 to fig 5.15.The

simulated output with timing has been shown in Appendix-A. This shows that the

proposed architecture takes latencies of 19 clock cycles (14 clock cycles for Level-I

and 5 clock cycles for both Level-II and Level-III discussed in previous section). The

Results shows that the signal is rotating in time frequency plane. When the rotation

angle is zero the output results is same as input means it acts as a identity operator.

When the rotation angle is 900, the output result is same as the Fourier transform of

the given input signal. When the rotation angle is 1800, the signal is time inverted.

For the final rotation angle 3600, the output result is same as the input means the

fractional Fourier transform acted as an identity operator.

Implementation results:

Finally the proposed design has been synthesized using Xilinx XST tool,

targeting a FPGA device (XLV5LX110T) [40]. The synthesis results obtained for

hardware has been presented in Table-5.9. And the device utilization summary report

is presented in Table-5.10.

TABLE-5.9

HDL SYNTHESIS REPORT- MACRO STATISTICS

Component Name Number of Components

16×64bitROM 2

Multipliers 69

Adders/Subtractors 104

16 to 1 Multiplexers 2

Counters 2

Registers 217

Accumulators 33

The synthesis report in this table-5.9 shows that the synthesis results for hardware

requirement are approximately same as the theoretical results. Timing report of this



implementation shows that the proposed design can be operated at maximum

frequency of 217MHz.

The proposed architecture in this paper has been compared with the architecture

presented in [27] for N=1024. The comparison for hardware and timing has been

highlighted in Table-5.11.

TABLE-5.10

DEVICE UTILIZATION-SUMMARY REPORT

Selected Device : 5vlx110tff1136-3

Slice Logic Utilization:

Number of Slice Registers: 5661 out of 69120 8%

Number of Slice LUTs: 3635 out of 69120 5%

Number used as Logic: 3417 out of 69120 4%

Number used as Memory: 218 out of 17920 1%

Number used as SRL: 218

Slice Logic Distribution:

Number of LUT Flip Flop pairs used: 7283

Number with an unused Flip Flop: 1622 out of 7283 22%

Number with an unused LUT: 3648 out of 7283 50%

Number of fully used LUT-FF pairs: 2013 out of 7283 27%

Number of unique control sets: 19

IO Utilization:

Number of IOs: 82

Number of bonded IOBs: 82 out of 640 12%

IOB Flip Flops/Latches: 16

Specific Feature Utilization:

Number of Block RAM/FIFO: 4 out of 148 2%

Number using Block RAM only: 4

Number of BUFG/BUFGCTRLs: 4 out of 32 12%

Number of DSP48Es: 36 out of 64 56%



TABLE-5.11

COMPARISON OF PROPOSED ARCHITECTURE WITH [27]

FOR 1024-POINT DFRFT

Hardware requirement

Component Name Number of Components

Architecture in [27] Proposed Architecture

Multipliers 1048576 4101

Adders/ Subtactors 1048576 4144

Registers 5242880 12280

Multiplexers 3072 (2:1 Mux)

3072 (4:1 Mux) 2 (1024:1 Mux)

Counters Not Mentioned 2

Timing details

Maximum speed 99.58 MHz 217.39 MHz

Sampling frequency 33.00 MHz 217.39MHz

This shows that the proposed design in this paper is better in terms of hardware

complexity and timing compared to architecture presented in [27].



Chapter 6

Conclusion and Future work

his thesis added an additional value to the conventional Fourier transform with a novel architecture of its generalized form which widens its applications range. The architecture achieves a better tradeoff between the area and timing

constraints that suitable for many applications. In signal, image processing applications like optimal filtering, optimal receivers, multiplexing, modulation and demodulation, image encryption, image compression and image restoration applications it is necessary to have flexibility to change the rotation angle along with fixed input vector length, which is achieved with this thesis. The closeness of the Xilinx ISE simulation results with the MATLAB simulations have been ensures its accuracy. This work achieved better results in terms of both hardware optimization and timing issues without compromising the accuracy of the results.

Future scope:

• The variable length fractional Fourier transform that is suitable for most of the applications.

• ASIC implementation of this proposed architecture for improvement of timing performance.

T



Chapter 6

Conclusion and Future work

his thesis added an additional value to the conventional Fourier transform with a novel architecture of its generalized form which widens its applications range. The architecture achieves a better tradeoff between the area and timing

constraints that suitable for many applications. In signal, image processing applications like optimal filtering, optimal receivers, multiplexing, modulation and demodulation, image encryption, image compression and image restoration applications it is necessary to have flexibility to change the rotation angle along with fixed input vector length, which is achieved with this thesis. The closeness of the Xilinx ISE simulation results with the MATLAB simulations have been ensures its accuracy. This work achieved better results in terms of both hardware optimization and timing issues without compromising the accuracy of the results.

To make this novel architecture most beneficial we recommend addition of flexibility to this tool in terms of its input vector length. By making the vector length flexible this architecture has been a singular for many applications. We conclude this chapter with the recommendation of variable length discrete fractional Fourier transform as future scope of work.

T



References

[01] McClellan J H, Parks T W. “Eigenvalue and eigenvector decomposition of the

discrete Fourier transform”. IEEE Trans Audio Eletroacoustics, 1972, AU-20:

66-74

[02] Namias V. “The fractional order Fourier transform and its application to quantum

mechanics”. J Inst Math Appl, 1980, 25: 241_265

[03] Dickinson B W, Steiglitz K. “Eigenvectors and functions of the discrete Fourier

transform”. IEEE Trans Acoust Speech Signal Process, 1982, ASSP-30: 25_31

[04] Almeida L B. “The fractional Fourier transform and time-frequency

representations”. IEEE Trans Signal Process, 1994, 42: 3084-3091

[05] Ozaktas H M, Barshan B, Mendlovic D, et al. “Convolution, filtering, and

multiplexing in fractional Fourier domains and their relationship to chirp and

wavelet transform”. J Opt Soc Amer A, 1994, 11: 547-559

[06] Santhanam B, McClellan J H. “The DRFT—a rotation in time-frequency space”.

In: Proc IEEE Int Conf Acoustics Speech Signal Process. New York: IEEE Press,

1995. 921-924

[07] Ozaktas H M, Arikan O, Kutay M A, et al. “Digital computation of the fractional

Fourier transform”. IEEE Trans Signal Process, 1996, 44: 2141-2150

[08] Zayed A I. “On the relationship between the Fourier transform and fractional

Fourier transform”. IEEE Signal Process Lett, 1996, 3: 310-311

[09] Santhanam B, McClellan J H. “The discrete rotational Fourier transform”. IEEE

Trans Signal Process, 1996, 42: 994-998

[10] Cariolaro G, Erseghe T, Kraniauskas P, et al. “A unified framework for the

fractional Fourier transform”. IEEE Trans Signal Process, 1998, 46: 3206-3219



[11] Cariolaro G, Erseghe T, Kraniauskas P, et al. “Multiplicity of fractional Fourier

transforms and their relationships”. IEEE Trans Signal Process, 2000, 48: 227-

241

[12] Kraniauskas P, Cariolaro G, Erseghe T. “Method for defining a class of fractional

operations”. IEEE Trans Signal Process, 1998, 46: 2804-2807

[13] Erseghe T, Kraniauskas P, Cariolaro G. “Unified fractional Fourier transform and

sampling theorem”. IEEE Trans Signal Process, 1999, 47: 3419-3423

[14] Bultheel A, Sulbaran H M. “Computation of the fractional Fourier transform”.

Appl Comput Harmon Anal, 2004, 16: 182-202

[15] Zhao X H, Tao R, Deng B. “Practical normalization methods in the digital

computation of the fractional Fourier transform”. In: Proc IEEE Int Conf Signal

Process. New York: IEEE Press, 2004, 1: 105-108

[16] Candan C, Kutay M A, Ozaktas H M. “The discrete fractional Fourier

transform”. In: Proc IEEE Int Conf Acoustics Speech Signal Process. New York:

IEEE Press, 1999. 1713-1716

[17] Candan C, Kutay M A, Ozaktas H M. “The discrete fractional Fourier

transform”. IEEE Trans Signal Process, 2000, 48: 1329-1337

[18] Candan C. “On higher order approximations for Hermite-Gaussian functions and

discrete fractional Fourier transforms”. IEEE Signal Process Lett, 2007, 14: 699-

702

[19] Pei S C, Yeh M H. “Discrete fractional Fourier transform”. Proc IEEE Int Symp

Circ Syst, 1996. 536-539

[20] Pei S C, Tseng C C. “A new discrete fractional Fourier transform based on

constrained eigendecomposition of DFT matrix by Largrange multiplier

method”. In: Proc IEEE Int Conf Acoustics Speech Signal Process. New York:

IEEE Press, 1997. 3965-3968

[21] Pei S C, Tseng C C, Yeh M H, et al. “Discrete fractional Hartley and Fourier

transform”. IEEE Trans Circ Syst II, 1998, 45: 665-675

[22] Pei S C, Yeh M H, Tseng C C. “Discrete fractional Fourier transform based on

orthogonal projections”. IEEE Trans Signal Process, 1999, 47: 1335-1348



[23] Pei S C, Tseng C C, Yeh M H. “A new discrete fractional Fourier transform

based on constrained eigen decomposition of DFT matrix by Largrange

multiplier method”. IEEE Trans Circuits Syst II, 1999, 46: 1240-1245

[24] Hanna M T, Seif N P A, Ahmed W A E M. “Hermite-Gaussian-like eigenvectors

of the discrete Fourier transform matrix based on the singular value

decomposition of its orthogonal projection matrices”. IEEE Trans Circ Syst I,

2004, 51: 2245-2254

[25] Pei S C, Hsue W L, Ding J J. “Discrete fractional Fourier transform based on

new nearly tridiagonal commuting matrices”. Proc IEEE Int Conf Acoustics

Speech and Signal Process, 2005. 385-388

[26] Pei S C, Hsue W L, Ding J J. “Discrete fractional Fourier transform based on

new nearly tridiagonal commuting matrices”. IEEE Trans Signal Process, 2006,

54: 3815-3828

[27] P. Sinha, S. Sarkar, A. Sinha, D. Basu, “ Architecture of a configurable Centered

Discrete Fractional Fourier Transform Processor” IEEE Circuits and Systems,

MWSCAS 2007. 50th Midwest Symposium, pp.329-332, 2007.

[28] K.C. Ray and A.S. Dhar, “CORDIC-based unified VLSI architecture for

implementing window functions for real time spectral analysis”, IEE Proc.-

Circuits Devices Syst., Vol. 153, pp. 539-544 , December 2006.

[29] N. Zhou, T. Dong, “Optical image encryption scheme based on multiple

parameter random fractional Fourier transform”, 2009 Second Int. Symposium On

electronic commerce and security, pp. 48-51, 2009.

[30] Y. Zhang, Q. Zhang, Shaohua Wu, “Biomedical signal detection based on

Fractional Fourier Transform”, IEEE, ITAB 2008, pp.349 – 352, May 2008.

[31] W. Pan, K. Qin, Y. Chen, “An Adaptable-Multilayer Fractional Fourier

Transform Approach for Image Registration” IEEE Trans. on pattern analysis

and machine intelligence, vol 31, March 2009.

[32] Richman M S, Parks T W. “Understanding discrete rotations”. In: Proc IEEE Int

Conf Acoust Speech Signal Process. New York: IEEE Press, 1997, 3: 2057-2060

[33] Pei S C, Ding J J. “Closed-form discrete fractional and affine Fourier

transforms”. IEEE Trans Signal Process, 2000, 48: 1338-1353



[34] Yeh M H, Pei S C. “A method for the discrete fractional Fourier transform

computation”. IEEE Trans Signal Process, 2003, 51: 889-891

[35] A.W. Lohmann, “ Image Rotation, Wigner Rotation and The Fractional Fourier

Transform”, J. Opt. Soc. of America A, vol. 10, no. 10, pp. 2181-2186, 1993.

[36] Ran Q W, Yeung D S, E. Tsang C C, et al. “General multifractional Fourier

transform method based on the generalized permutation matrix group”. IEEE

Trans Signal Process, 2005, 53(1): 83-98

[37] Hanna M T, Seif N P A, Ahmed W A E M. “Hermite-Gaussian-like eigenvectors

of the discrete Fourier transform matrix based on the direct utilization of the

orthogonal projection matrices on its eigenspaces”. IEEE Trans Signal Process,

2006, 54: 2815-2819

[38] Arikan O, Kutay M A, Ozaktas H M, et al. “The discrete fractional Fourier

transformation”. In: Proc IEEE Int Symp Time-Frequency Time-Scale Anal.

New York: IEEE Press, 1996. 205-207

[39] T. Ran, Z. Feng & W. Yue, “ Research progress on discretization of fractional

Fourier transform”, Springer, Sci. China Ser F-Inf Sci., pp. 859-880, July 2008

[40] Xilinx, “Virtex-5 FPGA User Guide”, UG190 (v4.7) May 1, 2009.

[41] McBride A.C. and Keer F.H., “On Namia's Fractional Fourier Transform”, IMA J. Appl.

Math., vol.239, pp. 159-175, 1987.



Appendix-A

Xilinx-ISE Simulation Results of Proposed DFrFT Architecture

ilinx 10.1i – ISE Simulation results of the 16-point DFrFT with the sinusoidal input for the rotation angles (fractional values) of 00(0.00), 300(0.33), 600(0.67), 900(1.00), 1200(1.33), 1500(1.67), 1800(2.00),

2100(2.33), 2400(2.67), 2700(3.00), 3000(3.33), 3300(3.67) and 3600(4.00). The first and final inputs are sampled at 740ns and 1035ns. The simulation results are started to give from 1950ns to 2250ns as sown in fallowing figures fig.a.1 to fig.a.14. In the each figure the first and final samples are labeled.

X



Fig.

a.1:

The

Inpu

t Sam

ples

for t

he S

imul

atio

n of

pro

pose

d D

FrFT

arc

hite

ctur

e us

ing

‘Xili

nx IS

E’ S

imul

ator

Fig.

a.2:

The

Sim

ulat

ion

Res

ult o

f pro

pose

d D

FrFT

arc

hite

ctur

e fo

r Rot

atio

n an

gle

of ‘0

0 ’ usi

ng ‘X

ilinx

ISE’

Sim

ulat

or



Fig.

a.3:

The

Sim

ulat

ion

Res

ult o

f pro

pose

d D

FrFT

arc

hite

ctur

e fo

r Rot

atio

n an

gle

of ‘3

00 ’ usi

ng ‘X

ilinx

ISE’

Sim

ulat

or

Fig.

a.4:

The

Sim

ulat

ion

Res

ult o

f pro

pose

d D

FrFT

arc

hite

ctur

e fo

r Rot

atio

n an

gle

of ‘6

00 ’ usi

ng ‘X

ilinx

ISE’

Sim

ulat

or

Fig.

a.5:

The

Sim

ulat

ion

Res

ult o

f pro

pose

d D

FrFT

arc

hite

ctur

e fo

r Rot

atio

n an

gle

of ‘9

00 ’ usi

ng ‘X

ilinx

ISE’

Sim

ulat

or



Fig.

a.8:

The

Sim

ulat

ion

Res

ult o

f pro

pose

d D

FrFT

arc

hite

ctur

e fo

r Rot

atio

n an

gle

of ‘1

800 ’ u

sing

‘Xili

nx IS

E’ S

imul

ator

Fig.

a.7:

The

Sim

ulat

ion

Res

ult o

f pro

pose

d D

FrFT

arc

hite

ctur

e fo

r Rot

atio

n an

gle

of ‘1

500 ’ u

sing

‘Xili

nx IS

E’ S

imul

ator

Fig.

a.6:

The

Sim

ulat

ion

Res

ult o

f pro

pose

d D

FrFT

arc

hite

ctur

e fo

r Rot

atio

n an

gle

of ‘1

200 ’ u

sing

‘Xili

nx IS

E’ S

imul

ator



Fig.

a.11

: The

Sim

ulat

ion

Res

ult o

f pro

pose

d D

FrFT

arc

hite

ctur

e fo

r Rot

atio

n an

gle

of ‘2

700 ’ u

sing

‘Xili

nx IS

E’ S

imul

ator

Fig.

a.10

: The

Sim

ulat

ion

Res

ult o

f pro

pose

d D

FrFT

arc

hite

ctur

e fo

r Rot

atio

n an

gle

of ‘2

400 ’ u

sing

‘Xili

nx IS

E’ S

imul

ator

Fig.

a.9:

The

Sim

ulat

ion

Res

ult o

f pro

pose

d D

FrFT

arc

hite

ctur

e fo

r Rot

atio

n an

gle

of ‘2

100 ’ u

sing

‘Xili

nx IS

E’ S

imul

ator



Fig.

a.14

: The

Sim

ulat

ion

Res

ult o

f pro

pose

d D

FrFT

arc

hite

ctur

e fo

r Rot

atio

n an

gle

of ‘3

600 ’ u

sing

‘Xili

nx IS

E’ S

imul

ator

Fig.

a.13

: The

Sim

ulat

ion

Res

ult o

f pro

pose

d D

FrFT

arc

hite

ctur

e fo

r Rot

atio

n an

gle

of ‘3

300 ’ u

sing

‘Xili

nx IS

E’ S

imul

ator

Fig.

a.12

: The

Sim

ulat

ion

Res

ult o

f pro

pose

d D

FrFT

arc

hite

ctur

e fo

r Rot

atio

n an

gle

of ‘3

000 ’ u

sing

‘Xili

nx IS

E’ S

imul

ator



Publications M.V.N.V.Prasad, K.C.Ray and A.S.Dhar, “FPGA Implementation of Discrete

Fractional Fourier Transform” International Conference on Signal Processing and

Communications, IISc, Bangalore, India, July 17-21, 2010. Accepted.

M.tech Theis - - VLSI Architecture for Discrete Fractional Fourier Transform

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