MPC860 PowerQUICC Family Users ManualSupports MPC860P MPC860T MPC860SR MPC860DP MPC860DE MPC860EN MPC860DT

MPC860UM Rev. 3 07/2004

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MPC860UM Rev. 3 07/2004

Part IOverview Overview Signal Descriptions Part IIMPC8xx Microprocessor Module The MPC8xx Core MPC8xx Core Register Set MPC8xx Instruction Set Exceptions Instruction and Data Caches Memory Management Unit Instruction Execution Timing Part IIIConfiguration and Reset System Interface Unit Reset Part IVHardware Interface External Signals External Bus Interface Clocks and Power Control Memory Controller PCMCIA Interface Part VCommunications Processor Module Communications Processor Module and CPM Timers Communications Processor SDMA Channels and IDMA Emulation Serial Interface Serial Communications Controllers SCC UART Mode SCC HDLC Mode SCC AppleTalk Mode SCC Asynchronous HDLC Mode and IrDA SCC BISYNC Mode SCC Ethernet Mode SCC Transparent Mode Serial Management Controllers (SMCs) Serial Peripheral Interface (SPI) I2C Controller Parallel Interface Port (PIP) Parallel I/O Ports CPM Interrupt Controller

I1 2

II3 4 5 6 7 8 9

III10 11

IV12 13 14 15 16

V17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

I1 2

II3 4 5 6 7 8 9

III10 11

IV12 13 14 15 16

V17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Part IOverview Overview Signal Descriptions Part IIMPC8xx Microprocessor Module The MPC8xx Core MPC8xx Core Register Set MPC8xx Instruction Set Exceptions Instruction and Data Caches Memory Management Unit Instruction Execution Timing Part IIIConfiguration and Reset System Interface Unit Reset Part IVHardware Interface External Signals External Bus Interface Clocks and Power Control Memory Controller PCMCIA Interface Part VCommunications Processor Module Communications Processor Module and CPM Timers Communications Processor SDMA Channels and IDMA Emulation Serial Interface Serial Communications Controllers SCC UART Mode SCC HDLC Mode SCC AppleTalk Mode SCC Asynchronous HDLC Mode and IrDA SCC BISYNC Mode SCC Ethernet Mode SCC Transparent Mode Serial Management Controllers (SMCs) Serial Peripheral Interface (SPI) I2C Controller Parallel Interface Port (PIP) Parallel I/O Ports CPM Interrupt Controller

Part VIAsynchronous Transfer Mode (ATM) ATM Overview Buffer Descriptors and Connection Tables ATM Parameter RAM ATM Controller ATM Pace Control ATM Exceptions Interface Configuration UTOPIA Interface Part VIIFast Ethernet Controller (FEC) Fast Ethernet Controller (FEC) Part VIIISystem Debugging and Testing Support System Development and Debugging IEEE 1149.1 Test Access Port Byte Ordering Serial Communications Performance Register Quick Reference Guide Instruction Set Listings Serial ATM Scrambling, Reception, and SI Programming MPC860DE MPC860DT MPC860DP MPC860EN MPC860SR MPC860T Users Manual Revision History Glossary Index

VI35 36 37 38 39 40 41 42

VII43

VIII44 45 A B C D E F G H I J K L GLO IND

VI35 36 37 38 39 40 41 42

VII43

VIII44 45 A B C D E F G H I J K L GLO IND

Part VIAsynchronous Transfer Mode (ATM) ATM Overview Buffer Descriptors and Connection Tables ATM Parameter RAM ATM Controller ATM Pace Control ATM Exceptions Interface Configuration UTOPIA Interface Part VIIFast Ethernet Controller (FEC) Fast Ethernet Controller (FEC) Part VIIISystem Debugging and Testing Support System Development and Debugging IEEE 1149.1 Test Access Port Byte Ordering Serial Communications Performance Register Quick Reference Guide Instruction Set Listings Serial ATM Scrambling, Reception, and SI Programming MPC860DE MPC860DT MPC860DP MPC860EN MPC860SR MPC860T Users Manual Revision History Glossary Index

ContentsParagraph Number Title About This Book Part I Overview Chapter 1 MPC860 Overview 1.1 1.2 1.3 1.4 1.5 1.6 1.7 Features ............................................................................................................................ 1-2 Embedded MPC8xx Core ................................................................................................ 1-8 System Interface Unit (SIU) ............................................................................................ 1-9 PCMCIA Controller....................................................................................................... 1-10 Power Management ....................................................................................................... 1-10 Communications Processor Module (CPM) .................................................................. 1-10 ATM Capabilities ........................................................................................................... 1-11 Chapter 2 Memory Map Part II MPC8xx Microprocessor Module Chapter 3 The MPC8xx Core 3.1 3.2 3.2.1 3.3 3.4 3.4.1 3.4.2 3.4.3 3.4.3.1 3.4.3.2 3.5 3.6 3.6.1 The MPC8xx Core as a PowerPC Implementation ......................................................... 3-1 PowerPC Architecture Overview..................................................................................... 3-1 Levels of the PowerPC Architecture ........................................................................... 3-3 Features ............................................................................................................................ 3-4 Basic Structure of the Core .............................................................................................. 3-6 Instruction Flow........................................................................................................... 3-7 Basic Instruction Pipeline ............................................................................................ 3-8 Instruction Unit ............................................................................................................ 3-8 Branch Operations ................................................................................................... 3-8 Dispatching Instructions ........................................................................................ 3-10 Register Set .................................................................................................................... 3-10 Execution Units.............................................................................................................. 3-10 Branch Processing Unit ............................................................................................. 3-11MPC860 PowerQUICC Family Users Manual, Rev. 3 Freescale Semiconductor vii

Page Number

ContentsParagraph Number 3.6.2 3.6.3 3.6.3.1 3.6.3.2 3.6.3.3 3.6.3.4 3.6.3.5 3.6.3.6 3.7 Title Page Number Integer Unit ................................................................................................................ 3-11 Load/Store Unit.......................................................................................................... 3-11 Executing Load/Store Instructions......................................................................... 3-13 Serializing Load/Store Instructions ....................................................................... 3-13 Store Accesses ....................................................................................................... 3-13 Nonspeculative Load Instructions ......................................................................... 3-14 Unaligned Accesses ............................................................................................... 3-14 Atomic Update Primitives ..................................................................................... 3-15 The MPC860 and Implementation of the PowerPC Architecture ................................. 3-15 Chapter 4 MPC8xx Core Register Set 4.1 4.1.1 4.1.1.1 4.1.1.1.1 4.1.1.1.2 4.1.1.1.3 4.1.1.1.4 4.1.2 4.1.2.1 4.1.2.2 4.1.2.3 4.1.2.3.1 4.1.2.3.2 4.1.3 4.1.3.1 4.2 MPC860 Register Implementation .................................................................................. 4-1 PowerPC RegistersUser Registers ........................................................................... 4-1 PowerPC User-Level Register Bit Assignments ..................................................... 4-2 Condition Register (CR)...................................................................................... 4-2 Condition Register CR0 Field Definition ............................................................ 4-3 XER ..................................................................................................................... 4-3 Time Base Registers ............................................................................................ 4-4 PowerPC RegistersSupervisor Registers ................................................................. 4-5 DAR, DSISR, and BAR Operation.......................................................................... 4-5 Unsupported Registers............................................................................................. 4-6 PowerPC Supervisor-Level Register Bit Assignments............................................ 4-6 Machine State Register (MSR)............................................................................ 4-7 Processor Version Register .................................................................................. 4-9 MPC860-Specific SPRs............................................................................................... 4-9 Accessing SPRs ..................................................................................................... 4-11 Register Initialization at Reset ....................................................................................... 4-12 Chapter 5 MPC860 Instruction Set 5.1 5.1.1 5.1.2 5.2 5.2.1 5.2.1.1 5.2.1.2 Operand Conventions ...................................................................................................... 5-1 Data Organization in Memory and Data Transfers...................................................... 5-1 Aligned and Misaligned Accesses ............................................................................... 5-1 Instruction Set Summary ................................................................................................. 5-2 Classes of Instructions ................................................................................................. 5-3 Definition of Boundedly Undefined ........................................................................ 5-4 Defined Instruction Class ........................................................................................ 5-4MPC860 PowerQUICC Family Users Manual, Rev. 3 viii Freescale Semiconductor

ContentsParagraph Number 5.2.1.3 5.2.1.4 5.2.2 5.2.2.1 5.2.2.2 5.2.2.3 5.2.2.3.1 5.2.2.3.2 5.2.2.3.3 5.2.3 5.2.4 5.2.4.1 5.2.4.1.1 5.2.4.1.2 5.2.4.1.3 5.2.4.1.4 5.2.4.2 5.2.4.2.1 5.2.4.2.2 5.2.4.2.3 5.2.4.2.4 5.2.4.2.5 5.2.4.2.6 5.2.4.3 5.2.4.3.1 5.2.4.3.2 5.2.4.3.3 5.2.4.4 5.2.4.5 5.2.4.5.1 5.2.4.6 5.2.5 5.2.5.1 5.2.5.2 5.2.5.2.1 5.2.5.2.2 5.2.5.3 5.2.6 5.2.6.1 5.2.6.2 Title Page Number Illegal Instruction Class ........................................................................................... 5-4 Reserved Instruction Class ...................................................................................... 5-5 Addressing Modes ....................................................................................................... 5-5 Memory Addressing ................................................................................................ 5-6 Effective Address Calculation ................................................................................. 5-6 Synchronization ....................................................................................................... 5-6 Context Synchronization ..................................................................................... 5-6 Execution Synchronization.................................................................................. 5-7 Instruction-Related Exceptions............................................................................ 5-7 Instruction Set Overview ............................................................................................. 5-8 PowerPC UISA Instructions ........................................................................................ 5-8 Integer Instructions .................................................................................................. 5-8 Integer Arithmetic Instructions............................................................................ 5-8 Integer Compare Instructions .............................................................................. 5-9 Integer Logical Instructions............................................................................... 5-10 Integer Rotate and Shift Instructions ................................................................. 5-11 Load and Store Instructions ................................................................................... 5-12 Integer Load and Store Address Generation...................................................... 5-12 Register Indirect Integer Load Instructions ....................................................... 5-12 Integer Store Instructions................................................................................... 5-13 Integer Load and Store with Byte-Reverse Instructions.................................... 5-13 Integer Load and Store Multiple Instructions.................................................... 5-14 Integer Load and Store String Instructions ........................................................ 5-14 Branch and Flow Control Instructions................................................................... 5-15 Branch Instruction Address Calculation............................................................ 5-16 Branch Instructions............................................................................................ 5-16 Condition Register Logical Instructions............................................................ 5-17 Trap Instructions .................................................................................................... 5-17 Processor Control Instructions............................................................................... 5-17 Move to/from Condition Register Instructions.................................................. 5-17 Memory Synchronization InstructionsUISA ..................................................... 5-18 PowerPC VEA Instructions ....................................................................................... 5-20 Processor Control Instructions............................................................................... 5-20 Memory Synchronization InstructionsVEA ...................................................... 5-20 eieio Behavior.................................................................................................... 5-21 isync Behavior ................................................................................................... 5-21 Memory Control InstructionsVEA .................................................................... 5-21 PowerPC OEA Instructions ....................................................................................... 5-22 System Linkage Instructions.................................................................................. 5-22 Processor Control InstructionsOEA .................................................................. 5-23MPC860 PowerQUICC Family Users Manual, Rev. 3 Freescale Semiconductor ix

ContentsParagraph Number 5.2.6.2.1 5.2.6.2.2 5.2.6.3 Title Page Number Move to/from Machine State Register Instructions........................................... 5-23 Move to/from Special-Purpose Register Instructions........................................ 5-23 Memory Control InstructionsOEA .................................................................... 5-24 Chapter 6 Exceptions 6.1 6.1.1 6.1.2 6.1.2.1 6.1.2.2 6.1.2.3 6.1.2.4 6.1.2.5 6.1.2.6 6.1.2.6.1 6.1.2.7 6.1.2.8 6.1.2.9 6.1.2.10 6.1.2.11 6.1.3 6.1.3.1 6.1.3.2 6.1.3.3 6.1.3.4 6.1.3.5 6.1.3.6 6.1.4 6.1.5 6.1.6 6.1.7 Exceptions........................................................................................................................ 6-1 Exception Ordering...................................................................................................... 6-3 PowerPC-Defined Exceptions ..................................................................................... 6-4 System Reset Interrupt (0x00100) ........................................................................... 6-5 Machine Check Interrupt (0x00200) ....................................................................... 6-5 DSI Exception (0x00300) ........................................................................................ 6-6 ISI Exception (0x00400).......................................................................................... 6-6 External Interrupt Exception (0x00500).................................................................. 6-6 Alignment Exception (0x00600) ............................................................................. 6-7 Integer Alignment Exceptions ............................................................................. 6-8 Program Exception (0x00700)................................................................................. 6-9 Decrementer Exception (0x00900)........................................................................ 6-10 System Call Exception (0x00C00) ........................................................................ 6-11 Trace Exception (0x00D00)................................................................................... 6-11 Floating-Point Assist Exception ............................................................................ 6-12 Implementation-Specific Exceptions......................................................................... 6-12 Software Emulation Exception (0x01000) ............................................................ 6-12 Instruction TLB Miss Exception (0x01100) .......................................................... 6-13 Data TLB Miss Exception (0x01200).................................................................... 6-13 Instruction TLB Error Exception (0x01300) ......................................................... 6-14 Data TLB Error Exception (0x01400) ................................................................... 6-14 Debug Exceptions (0x01C000x01F00) ............................................................... 6-15 Implementing the Precise Exception Model.............................................................. 6-16 Recoverability After an Exception ............................................................................ 6-17 Exception Latency ..................................................................................................... 6-19 Partially Completed Instructions ............................................................................... 6-20 Chapter 7 Instruction and Data Caches 7.1 7.2 7.3 Instruction Cache Organization ....................................................................................... 7-2 Data Cache Organization ................................................................................................. 7-5 Cache Control Registers .................................................................................................. 7-8MPC860 PowerQUICC Family Users Manual, Rev. 3 x Freescale Semiconductor

ContentsParagraph Number 7.3.1 7.3.1.1 7.3.1.2 7.3.1.2.1 7.3.1.2.2 7.3.1.2.3 7.3.1.2.4 7.3.1.2.5 7.3.2 7.3.2.1 7.3.2.2 7.3.2.2.1 7.3.2.2.2 7.3.2.2.3 7.3.2.2.4 7.3.2.2.5 7.3.2.2.6 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 7.5 7.5.1 7.5.2 7.5.3 7.5.4 7.5.5 7.6 7.6.1 7.6.2 7.6.3 7.6.3.1 7.6.3.2 7.6.4 7.6.4.1 7.6.4.2 7.6.5 Title Page Number Instruction Cache Control Registers ............................................................................ 7-8 Reading Data and Tags in the Instruction Cache................................................... 7-11 IC_CST Commands............................................................................................... 7-12 Instruction Cache Enable/Disable Commands .................................................. 7-12 Instruction Cache Load and Lock Cache Block Command .............................. 7-12 Instruction Cache Unlock Cache Block Command ........................................... 7-13 Instruction Cache Unlock All Command .......................................................... 7-13 Instruction Cache Invalidate All Command ...................................................... 7-14 Data Cache Control Registers.................................................................................... 7-14 Reading Data Cache Tags and Copyback Buffer................................................... 7-17 DC_CST Commands ............................................................................................. 7-18 Data Cache Enable/Disable Commands ............................................................ 7-18 Data Cache Load and Lock Cache Block Command ........................................ 7-19 Data Cache Unlock Cache Block Command..................................................... 7-19 Data Cache Unlock All Command .................................................................... 7-20 Data Cache Invalidate All Command................................................................ 7-20 Data Cache Flush Cache Block Command........................................................ 7-20 Cache Control Instructions ............................................................................................ 7-21 Instruction Cache Block Invalidate (icbi).................................................................. 7-21 Data Cache Block Touch (dcbt) and Data Cache Block Touch for Store (dcbtst) ... 7-21 Data Cache Block Zero (dcbz) .................................................................................. 7-22 Data Cache Block Store (dcbst) ................................................................................ 7-22 Data Cache Block Flush (dcbf) ................................................................................. 7-22 Data Cache Block Invalidate (dcbi) .......................................................................... 7-23 Instruction Cache Operations......................................................................................... 7-23 Instruction Cache Hit ................................................................................................. 7-25 Instruction Cache Miss .............................................................................................. 7-25 Instruction Fetching on a Predicted Path ................................................................... 7-26 Fetching Instructions from Caching-Inhibited Regions............................................. 7-26 Updating Code and Memory Region Attributes ........................................................ 7-26 Data Cache Operation .................................................................................................... 7-27 Data Cache Load Hit.................................................................................................. 7-28 Data Cache Read Miss............................................................................................... 7-28 Write-Through Mode ................................................................................................. 7-29 Data Cache Store Hit in Write-Through Mode...................................................... 7-29 Data Cache Store Miss in Write-Through Mode ................................................... 7-29 Write-Back Mode....................................................................................................... 7-29 Data Cache Store Hit in Write-Back Mode ........................................................... 7-30 Data Cache Store Miss in Write-Back Mode......................................................... 7-30 Data Accesses to Caching-Inhibited Memory Regions ............................................. 7-31MPC860 PowerQUICC Family Users Manual, Rev. 3 Freescale Semiconductor xi

ContentsParagraph Number 7.6.6 7.7 7.8 7.8.1 7.8.2 Title Page Number Atomic Memory References...................................................................................... 7-31 Cache Initialization after Reset...................................................................................... 7-32 Debug Support ............................................................................................................... 7-33 Instruction and Data Cache Operation in Debug Mode............................................. 7-33 Instruction and Data Cache Operation with a Software Monitor Debugger.............. 7-33 Chapter 8 Memory Management Unit 8.1 8.2 8.3 8.3.1 8.3.2 8.3.3 8.4 8.5 8.6 8.7 8.7.1 8.7.2 8.7.3 8.8 8.8.1 8.8.2 8.8.3 8.8.4 8.8.5 8.8.6 8.8.7 8.8.8 8.8.9 8.8.10 8.8.11 8.8.12 8.8.12.1 8.8.12.2 8.8.12.3 8.8.12.4 8.8.12.5 Features ............................................................................................................................ 8-1 PowerPC Architecture Compliance ................................................................................. 8-2 Address Translation ......................................................................................................... 8-3 Translation Disabled .................................................................................................... 8-3 Translation Enabled ..................................................................................................... 8-3 TLB Operation............................................................................................................. 8-5 Using Access Protection Groups ..................................................................................... 8-6 Protection Resolution Modes........................................................................................... 8-7 Memory Attributes........................................................................................................... 8-8 Translation Table Structure .............................................................................................. 8-9 Level-One Descriptor ................................................................................................ 8-12 Level-Two Descriptor ................................................................................................ 8-13 Page Size.................................................................................................................... 8-14 Programming Model ...................................................................................................... 8-14 IMMU Control Register (MI_CTR) .......................................................................... 8-15 DMMU Control Register (MD_CTR) ....................................................................... 8-16 IMMU/DMMU Effective Page Number Register (Mx_EPN) .................................. 8-18 IMMU Tablewalk Control Register (MI_TWC) ....................................................... 8-18 DMMU Tablewalk Control Register (MD_TWC) .................................................... 8-19 IMMU Real Page Number Register (MI_RPN) ........................................................ 8-21 DMMU Real Page Number Register (MD_RPN) ..................................................... 8-22 MMU Tablewalk Base Register (M_TWB)............................................................... 8-24 MMU Current Address Space ID Register (M_CASID)........................................... 8-25 MMU Access Protection Registers (MI_AP/MD_AP) ............................................. 8-25 MMU Tablewalk Special Register (M_TW) ............................................................. 8-26 MMU Debug Registers.............................................................................................. 8-26 IMMU CAM Entry Read Register (MI_CAM)..................................................... 8-26 IMMU RAM Entry Read Register 0 (MI_RAM0)................................................ 8-28 IMMU RAM Entry Read Register 1 (MI_RAM1)................................................ 8-29 DMMU CAM Entry Read Register (MD_CAM).................................................. 8-30 DMMU RAM Entry Read Register 0 (MD_RAM0)............................................. 8-31MPC860 PowerQUICC Family Users Manual, Rev. 3 xii Freescale Semiconductor

ContentsParagraph Number 8.8.13 8.9 8.10 8.10.1 8.10.1.1 8.10.2 8.10.3 8.10.4 Title Page Number DMMU RAM Entry Read Register 1 (MD_RAM1)................................................. 8-32 Memory Management Unit Exceptions ......................................................................... 8-33 TLB Manipulation ......................................................................................................... 8-34 TLB Reload................................................................................................................ 8-34 Translation Reload Examples ................................................................................ 8-34 Locking TLB Entries ................................................................................................. 8-36 Loading Locked TLB Entries .................................................................................... 8-36 TLB Invalidation........................................................................................................ 8-37 Chapter 9 Instruction Execution Timing 9.1 9.1.1 9.1.2 9.1.3 9.1.4 9.1.5 9.1.6 9.1.7 9.2 9.2.1 9.2.2 9.2.3 Instruction Execution Timing Examples.......................................................................... 9-1 Data Cache Load with a Data Dependency ................................................................. 9-1 Writeback Arbitration .................................................................................................. 9-2 Private Writeback Bus Load ........................................................................................ 9-3 Fastest External Load (Data Cache Miss).................................................................... 9-3 A Full Completion Queue............................................................................................ 9-4 Branch Instruction Handling........................................................................................ 9-5 Branch Prediction ........................................................................................................ 9-5 Instruction Timing List .................................................................................................... 9-6 Load/Store Instruction Timing..................................................................................... 9-8 String Instruction Latency ........................................................................................... 9-8 Accessing Off-Core SPRs............................................................................................ 9-8 Part III Configuration and Reset Chapter 10 System Interface Unit 10.1 10.2 10.3 10.4 10.4.1 10.4.2 10.4.3 10.4.4 10.4.5 Features .......................................................................................................................... 10-1 System Configuration and Protection ............................................................................ 10-2 Multiplexing SIU Pins ................................................................................................... 10-3 Programming the SIU .................................................................................................... 10-4 Internal Memory Map Register (IMMR)................................................................... 10-5 SIU Module Configuration Register (SIUMCR)....................................................... 10-6 System Protection Control Register (SYPCR) .......................................................... 10-8 Transfer Error Status Register (TESR) ...................................................................... 10-9 Register Lock Mechanism ....................................................................................... 10-10MPC860 PowerQUICC Family Users Manual, Rev. 3 Freescale Semiconductor xiii

ContentsParagraph Number 10.5 10.5.1 10.5.2 10.5.3 10.5.3.1 10.5.4 10.5.4.1 10.5.4.2 10.5.4.3 10.5.4.4 10.6 10.7 10.7.1 10.8 10.8.1 10.9 10.9.1 10.9.2 10.9.3 10.10 10.10.1 10.10.2 10.10.3 10.10.4 10.11 10.11.1 10.11.2 10.11.3 10.12 10.12.1 10.12.2 Title Page Number System Configuration .................................................................................................. 10-12 Interrupt Structure.................................................................................................... 10-12 Priority of Interrupt Sources .................................................................................... 10-14 SIU Interrupt Processing.......................................................................................... 10-14 Nonmaskable InterruptsIRQ0 and SWT.......................................................... 10-15 Programming the SIU Interrupt Controller.............................................................. 10-16 SIU Interrupt Pending Register (SIPEND).......................................................... 10-16 SIU Interrupt Mask Register (SIMASK) ............................................................. 10-17 SIU Interrupt Edge/Level Register (SIEL) .......................................................... 10-18 SIU Interrupt Vector Register (SIVEC) ............................................................... 10-19 The Bus Monitor .......................................................................................................... 10-21 Software Watchdog Timer ........................................................................................... 10-22 Software Service Register (SWSR) ......................................................................... 10-23 The Decrementer.......................................................................................................... 10-24 Decrementer Register (DEC)................................................................................... 10-25 The Timebase............................................................................................................... 10-25 Timebase Register (TBU and TBL)......................................................................... 10-25 Timebase Reference Registers (TBREFA and TBREFB) ....................................... 10-26 Timebase Status and Control Register (TBSCR)..................................................... 10-27 The Real-Time Clock................................................................................................... 10-28 Real-Time Clock Status and Control Register (RTCSC)......................................... 10-29 Real-Time Clock Register (RTC) ............................................................................ 10-30 Real-Time Clock Alarm Register (RTCAL)............................................................ 10-30 Real-Time Clock Alarm Seconds Register (RTSEC) .............................................. 10-31 Periodic Interrupt Timer (PIT)..................................................................................... 10-32 Periodic Interrupt Status and Control Register (PISCR) ......................................... 10-33 PIT Count Register (PITC) ...................................................................................... 10-34 PIT Register (PITR)................................................................................................. 10-34 General SIU Timers Operation .................................................................................... 10-35 Freeze Operation...................................................................................................... 10-35 Low-Power Stop Operation ..................................................................................... 10-35 Chapter 11 Reset 11.1 11.1.1 11.1.2 11.1.3 11.1.3.1 Types of Reset................................................................................................................ 11-1 Power-On Reset ......................................................................................................... 11-2 External Hard Reset ................................................................................................... 11-2 Internal Hard Reset .................................................................................................... 11-2 Software Watchdog Reset...................................................................................... 11-3MPC860 PowerQUICC Family Users Manual, Rev. 3 xiv Freescale Semiconductor

ContentsParagraph Number 11.1.3.2 11.1.4 11.1.5 11.1.6 11.1.7 11.1.8 11.1.9 11.2 11.3 11.3.1 11.3.1.1 11.3.2 11.4 Title Page Number Checkstop Reset..................................................................................................... 11-3 Debug Port Hard or Soft Reset .................................................................................. 11-3 JTAG Reset ................................................................................................................ 11-3 Power-On and Hard Reset Sequence ......................................................................... 11-3 External Soft Reset .................................................................................................... 11-4 Internal Soft Reset ..................................................................................................... 11-4 Soft Reset Sequence................................................................................................... 11-4 Reset Status Register (RSR) .......................................................................................... 11-5 MPC860 Reset Configuration........................................................................................ 11-6 Hard Reset.................................................................................................................. 11-7 Hard Reset Configuration Word ............................................................................ 11-9 Soft Reset..................................................................................................................11-11 TRST and Power Mode Considerations .......................................................................11-11 Part IV Hardware Interface Chapter 12 External Signals 12.1 12.2 12.3 12.4 12.4.1 12.4.1.1 12.4.2 12.4.3 12.4.4 12.5 System Bus Signals........................................................................................................ 12-5 Active Pull-Up Buffers ................................................................................................ 12-23 Internal Pull-Up and Pull-Down Resistors ................................................................. 12-25 Recommended Basic Pin Connections ........................................................................ 12-25 Reset Configuration ................................................................................................. 12-26 Bus Control Signals and Interrupts...................................................................... 12-26 JTAG and Debug Ports ............................................................................................ 12-26 Unused Inputs .......................................................................................................... 12-27 Unused Outputs........................................................................................................ 12-27 Signal States During Reset........................................................................................... 12-27 Chapter 13 External Bus Interface 13.1 13.2 13.3 13.4 13.4.1 13.4.2 Features .......................................................................................................................... 13-1 Bus Transfer Overview .................................................................................................. 13-1 Bus Interface Signal Descriptions.................................................................................. 13-2 Bus Operations............................................................................................................... 13-6 Basic Transfer Protocol.............................................................................................. 13-6 Single-Beat Transfer .................................................................................................. 13-7MPC860 PowerQUICC Family Users Manual, Rev. 3 Freescale Semiconductor xv

ContentsParagraph Number 13.4.2.1 13.4.2.2 13.4.3 13.4.4 13.4.5 13.4.6 13.4.6.1 13.4.6.2 13.4.6.3 13.4.6.4 13.4.7 13.4.7.1 13.4.7.2 13.4.7.3 13.4.7.3.1 13.4.7.3.2 13.4.7.3.3 13.4.7.3.4 13.4.7.3.5 13.4.8 13.4.8.1 13.4.8.2 13.4.8.3 13.4.8.4 13.4.9 13.4.9.1 13.4.9.2 13.4.10 13.4.10.1 Title Page Number Single-Beat Read Flow .......................................................................................... 13-7 Single-Beat Write Flow ....................................................................................... 13-10 Burst Transfers......................................................................................................... 13-14 Burst Operations ...................................................................................................... 13-15 Alignment and Data Packing on Transfers .............................................................. 13-24 Arbitration Phase ..................................................................................................... 13-27 Bus Request (BR) ................................................................................................ 13-28 Bus Grant (BG).................................................................................................... 13-28 Bus Busy (BB)..................................................................................................... 13-28 External Bus Parking ........................................................................................... 13-31 Address Transfer Phase-Related Signals ................................................................. 13-31 Transfer Start (TS) ............................................................................................... 13-31 Address Bus ......................................................................................................... 13-32 Transfer Attributes ............................................................................................... 13-32 Read/Write (RD/WR) ...................................................................................... 13-32 Burst Indicator (BURST)................................................................................. 13-32 Transfer Size (TSIZ)........................................................................................ 13-32 Address Types (AT) ......................................................................................... 13-33 Burst Data in Progress (BDIP) ........................................................................ 13-35 Termination Signals ................................................................................................. 13-35 Transfer Acknowledge (TA) ................................................................................ 13-35 Burst Inhibit (BI) ................................................................................................. 13-35 Transfer Error Acknowledge (TEA).................................................................... 13-35 Termination Signals Protocol .............................................................................. 13-35 Memory Reservation................................................................................................ 13-37 Cancel Reservation (CR) ..................................................................................... 13-37 Kill Reservation (KR).......................................................................................... 13-38 Bus Exception Control Cycles................................................................................. 13-39 RETRY ................................................................................................................ 13-40 Chapter 14 Clocks and Power Control 14.1 14.2 14.2.1 14.2.1.1 14.2.1.2 14.2.2 14.2.2.1 Features .......................................................................................................................... 14-1 The Clock Module ......................................................................................................... 14-2 External Reference Clocks......................................................................................... 14-3 Off-Chip Oscillator Input (EXTCLK) ................................................................... 14-4 Crystal Oscillator Support (EXTAL and XTAL)................................................... 14-4 System PLL................................................................................................................ 14-5 SPLL Reset Configuration..................................................................................... 14-6MPC860 PowerQUICC Family Users Manual, Rev. 3 xvi Freescale Semiconductor

ContentsParagraph Number 14.2.2.2 14.2.2.3 14.2.2.4 14.3 14.3.1 14.3.1.1 14.3.1.2 14.3.1.3 14.3.1.4 14.3.1.5 14.3.2 14.3.3 14.4 14.4.1 14.4.2 14.4.3 14.4.4 14.5 14.5.1 14.5.2 14.5.3 14.5.4 14.5.5 14.5.6 14.5.7 14.5.7.1 14.5.7.2 14.5.7.3 14.5.8 14.6 14.6.1 14.6.2 Title Page Number SPLL Output Characteristics and Stability............................................................ 14-7 System Phase-Locked Loop Pins (VDDSYN, VSSSYN, VSSSYN1, XFC)........ 14-8 Disabling the SPLL................................................................................................ 14-9 Clock Signals ................................................................................................................. 14-9 Clocks Derived from the SPLL Output ................................................................... 14-10 The Internal General System Clocks (GCLK1C, GCLK2C, GCLK1, GCLK2) ........................................................................................................... 14-11 Memory Controller and External Bus Clocks (GCLK1_50, GCLK2_50, CLKOUT)........................................................................................................ 14-12 CLKOUT Special Considerations: 1:2:1 Mode................................................... 14-14 The Baud Rate Generator Clock (BRGCLK)...................................................... 14-15 The Synchronization Clock (SYNCCLK, SYNCCLKS) .................................... 14-15 The PIT and RTC Clock (PITRTCLK).................................................................... 14-16 The Time Base and Decrementer Clock (TMBCLK).............................................. 14-17 Power Distribution....................................................................................................... 14-17 I/O Buffer Power (VDDH) ...................................................................................... 14-18 Internal Logic Power (VDDL)................................................................................. 14-19 Clock Synthesizer Power (VDDSYN, VSSSYN, VSSYN1) .................................. 14-19 Keep-Alive Power (KAPWR) ................................................................................. 14-19 Power Control (Low-Power Modes)............................................................................ 14-19 Normal High Mode.................................................................................................. 14-23 Normal Low Mode................................................................................................... 14-23 Doze High Mode...................................................................................................... 14-23 Doze Low Mode ...................................................................................................... 14-24 Sleep Mode .............................................................................................................. 14-25 Deep-Sleep Mode .................................................................................................... 14-25 Power-Down Mode.................................................................................................. 14-26 Software Initiation of Power-Down Mode, with Automatic Wake-Up ............... 14-26 Maintaining the Real-Time Clock (RTC) During Shutdown or Power Failure... 14-28 Register Lock Mechanism: Protecting SIU Registers in Power-Down Mode..... 14-28 TMIST: Facilitating Nesting of SIU Timer Interrupts............................................. 14-29 Clock and Power Control Registers............................................................................. 14-29 System Clock and Reset Control Register (SCCR) ................................................. 14-29 PLL, Low-Power, and Reset Control Register (PLPRCR)...................................... 14-32 Chapter 15 Memory Controller 15.1 15.2 Features .......................................................................................................................... 15-1 Basic Architecture.......................................................................................................... 15-3MPC860 PowerQUICC Family Users Manual, Rev. 3 Freescale Semiconductor xvii

ContentsParagraph Number 15.3 15.3.1 15.3.2 15.3.3 15.3.4 15.3.5 15.3.6 15.3.7 15.3.8 15.3.9 15.4 15.4.1 15.4.2 15.4.3 15.4.4 15.4.5 15.4.6 15.4.7 15.4.8 15.5 15.5.1 15.5.1.1 15.5.1.2 15.5.1.3 15.5.1.4 15.5.1.5 15.5.1.6 15.5.2 15.5.3 15.5.4 15.6 15.6.1 15.6.1.1 15.6.1.2 15.6.1.3 15.6.1.4 15.6.2 15.6.3 15.6.4 15.6.4.1 Title Page Number Chip-Select Programming Common to the GPCM and UPM ....................................... 15-6 Address Space Programming..................................................................................... 15-7 Register Programming Order..................................................................................... 15-7 Memory Bank Write Protection................................................................................. 15-7 Address Type Protection............................................................................................ 15-7 8-, 16-, and 32-Bit Port Size Configuration............................................................... 15-7 Parity Configuration .................................................................................................. 15-8 Memory Bank Protection Status ................................................................................ 15-8 UPM-Specific Registers ............................................................................................ 15-8 GPCM-Specific Registers.......................................................................................... 15-8 Register Descriptions ..................................................................................................... 15-9 Base Registers (BRx)................................................................................................. 15-9 Option Registers (ORx) ........................................................................................... 15-10 Memory Status Register (MSTAT) .......................................................................... 15-13 Machine A Mode Register/Machine B Mode Registers (MxMR) .......................... 15-13 Memory Command Register (MCR) ....................................................................... 15-15 Memory Data Register (MDR) ................................................................................ 15-17 Memory Address Register (MAR) .......................................................................... 15-17 Memory Periodic Timer Prescaler Register (MPTPR) ............................................ 15-18 General-Purpose Chip-Select Machine (GPCM)......................................................... 15-18 Timing Configuration .............................................................................................. 15-19 Chip-Select Assertion Timing ............................................................................. 15-20 Chip-Select and Write Enable Deassertion Timing ............................................. 15-21 Relaxed Timing.................................................................................................... 15-23 Output Enable (OE) Timing ................................................................................ 15-26 Programmable Wait State Configuration ............................................................. 15-26 Extended Hold Time on Read Accesses .............................................................. 15-26 Boot Chip-Select Operation..................................................................................... 15-29 External Asynchronous Master Support .................................................................. 15-30 Special Case: Bursting with External Transfer Acknowledge:................................ 15-31 User-Programmable Machines (UPMs)....................................................................... 15-32 Requests ................................................................................................................... 15-33 Internal/External Memory Access Requests........................................................ 15-34 UPM Periodic Timer Requests ............................................................................ 15-34 Software RequestsMCR RUN Command ......................................................... 15-35 Exception Requests.............................................................................................. 15-35 Programming the UPM............................................................................................ 15-35 Control Signal Generation Timing........................................................................... 15-36 The RAM Array....................................................................................................... 15-38 RAM Words......................................................................................................... 15-39MPC860 PowerQUICC Family Users Manual, Rev. 3 xviii Freescale Semiconductor

ContentsParagraph Number 15.6.4.2 15.6.4.3 15.6.4.4 15.6.4.5 15.6.4.6 15.6.4.7 15.6.4.8 15.6.4.9 15.6.4.10 15.6.4.11 15.6.4.11.1 15.6.4.11.2 15.7 15.7.1 15.7.2 15.8 15.8.1 15.8.2 15.8.3 15.8.4 15.8.4.1 15.8.4.2 15.8.4.3 15.8.5 15.8.5.1 15.8.5.2 15.9 15.9.1 15.9.2 Title Page Number Chip-Select Signals (CSTx)................................................................................. 15-42 Byte-Select Signals (BSTx)................................................................................. 15-43 General-Purpose Signals (GxTx, G0x)................................................................ 15-44 Loop Control (LOOP).......................................................................................... 15-46 Exception Pattern Entry (EXEN)......................................................................... 15-47 Address Multiplexing (AMX) ............................................................................. 15-47 Transfer Acknowledge and Data Sample Control (UTA, DLT3) ........................ 15-51 Disable Timer Mechanism (TODT)..................................................................... 15-52 The Last Word (LAST)........................................................................................ 15-52 Wait Mechanism (WAEN) ................................................................................... 15-52 Internal and External Synchronous Masters .................................................... 15-53 External Asynchronous Masters...................................................................... 15-53 Handling Devices with Slow or Variable Access Times.............................................. 15-54 Hierarchical Bus Interface Example ........................................................................ 15-55 Slow Devices Example ............................................................................................ 15-55 External Master Support .............................................................................................. 15-55 Synchronous External Masters ................................................................................ 15-56 Asynchronous External Masters .............................................................................. 15-56 Special Case: Address Type Signals for External Masters ...................................... 15-56 UPM Features Supporting External Masters ........................................................... 15-56 Address Incrementing for External Synchronous Bursting Masters ................... 15-57 Handshake Mechanism for Asynchronous External Masters.............................. 15-57 Special Signal for External Address Multiplexer Control ................................... 15-57 External Master Examples ....................................................................................... 15-57 External Masters and the GPCM ......................................................................... 15-57 External Masters and the UPM............................................................................ 15-59 Memory System Interface Examples ........................................................................... 15-64 Page-Mode DRAM Interface Example.................................................................... 15-64 Page Mode Extended Data-Out Interface Example................................................. 15-75 Chapter 16 PCMCIA Interface 16.1 16.2 16.2.1 16.2.2 16.2.3 16.2.4 16.3 System Configuration .................................................................................................... 16-1 PCMCIA Module Signal Definitions ............................................................................ 16-1 PCMCIA Cycle Control Signals................................................................................ 16-2 PCMCIA Input Port Signals ...................................................................................... 16-4 PCMCIA Output Port Signals (OP[04]) .................................................................. 16-5 Other PCMCIA Signals ............................................................................................. 16-5 Operation Description.................................................................................................... 16-5MPC860 PowerQUICC Family Users Manual, Rev. 3 Freescale Semiconductor xix

ContentsParagraph Number 16.3.1 16.3.2 16.3.3 16.3.4 16.3.5 16.3.6 16.4 16.4.1 16.4.2 16.4.3 16.4.4 16.4.5 16.4.6 16.5 Title Page Number Memory-Only Cards .................................................................................................. 16-5 I/O Cards.................................................................................................................... 16-6 Interrupts.................................................................................................................... 16-6 Power Control ............................................................................................................ 16-7 Reset and Three-State Control ................................................................................... 16-7 DMA .......................................................................................................................... 16-7 Programming Model ...................................................................................................... 16-8 PCMCIA Interface Input Pins Register (PIPR) ......................................................... 16-8 PCMCIA Interface Status Changed Register (PSCR) ............................................... 16-9 PCMCIA Interface Enable Register (PER) ............................................................. 16-11 PCMCIA Interface General Control Register (PGCRx).......................................... 16-12 PCMCIA Base Registers 07 (PBR0PBR7).......................................................... 16-13 PCMCIA Option Register 07 (POR0POR7) ....................................................... 16-14 PCMCIA Controller Timing Examples ....................................................................... 16-17 Part V Communications Processor Module Chapter 17 Communications Processor Module and CPM Timers 17.1 17.2 17.2.1 17.2.2 17.2.2.1 17.2.2.2 17.2.2.3 17.2.2.4 17.2.2.5 17.2.2.6 17.2.3 17.2.3.1 17.2.4 17.2.4.1 17.2.4.2 17.2.4.3 17.2.4.4 17.2.5 Features .......................................................................................................................... 17-2 CPM General-Purpose Timers ....................................................................................... 17-4 Features...................................................................................................................... 17-5 CPM Timer Operation ............................................................................................... 17-6 Timer Clock Source ............................................................................................... 17-6 Timer Reference Count.......................................................................................... 17-6 Timer Capture ........................................................................................................ 17-6 Timer Gating.......................................................................................................... 17-7 Cascaded Mode...................................................................................................... 17-7 Timer 1 and SPKROUT......................................................................................... 17-8 CPM Timer Register Set............................................................................................ 17-8 Timer Global Configuration Register (TGCR)...................................................... 17-8 Timer Mode Registers (TMR1TMR4)..................................................................... 17-9 Timer Reference Registers (TRR1TRR4) ......................................................... 17-10 Timer Capture Registers (TCR1TCR4) ............................................................. 17-11 Timer Counter Registers (TCN1TCN4) ............................................................ 17-11 Timer Event Registers (TER1TER4)................................................................. 17-12 Timer Initialization Examples.................................................................................. 17-12

MPC860 PowerQUICC Family Users Manual, Rev. 3 xx Freescale Semiconductor

ContentsParagraph Number Title Chapter 18 Communications Processor 18.1 18.2 18.3 18.4 18.5 18.5.1 18.5.2 18.5.3 18.5.3.1 18.5.3.2 18.6 18.6.1 18.6.2 18.6.3 18.7 18.7.1 18.7.2 18.7.3 18.7.3.1 18.7.3.2 18.7.4 18.7.5 18.7.6 18.7.7 18.7.8 Features .......................................................................................................................... 18-1 Communicating with the Core ....................................................................................... 18-2 Communicating with the Peripherals............................................................................. 18-2 CP Microcode Revision Number ................................................................................... 18-4 CP Register Set and CP Commands .............................................................................. 18-4 RISC Controller Configuration Register (RCCR) ..................................................... 18-4 CP Command Register (CPCR)................................................................................. 18-5 CP Commands ........................................................................................................... 18-7 CP Command Examples ........................................................................................ 18-9 CP Command Execution Latency.......................................................................... 18-9 Dual-Port RAM.............................................................................................................. 18-9 System RAM and Microcode Packages................................................................... 18-11 The Buffer Descriptor (BD)..................................................................................... 18-12 Parameter RAM ....................................................................................................... 18-12 The RISC Timer Table................................................................................................. 18-13 RISC Timer Table Scan Algorithm.......................................................................... 18-14 The SET TIMER Command........................................................................................ 18-15 RISC Timer Table Parameter RAM and Timer Table Entries ................................. 18-15 RISC Timer Command Register (TM_CMD) ..................................................... 18-16 RISC Timer Table Entries.................................................................................... 18-17 RISC Timer Event Register (RTER)/Mask Register (RTMR) ................................ 18-17 PWM Mode.............................................................................................................. 18-17 RISC Timer Initialization ........................................................................................ 18-18 RISC Timer Interrupt Handling ............................................................................... 18-19 Using the RISC Timers to Track CP Loading ......................................................... 18-19 Chapter 19 SDMA Channels and IDMA Emulation 19.1 19.1.1 19.1.2 19.2 19.2.1 19.2.2 19.2.3 19.2.4 19.3 SDMA Channels ............................................................................................................ 19-1 SDMA Transfers........................................................................................................ 19-2 U-Bus Arbitration and the SDMA Channels ............................................................. 19-2 SDMA Registers ............................................................................................................ 19-3 SDMA Configuration Register (SDCR) .................................................................... 19-3 SDMA Status Register (SDSR) ................................................................................. 19-4 SDMA Mask Register (SDMR)................................................................................. 19-5 SDMA Address Register (SDAR) ............................................................................. 19-5 IDMA Emulation ........................................................................................................... 19-5MPC860 PowerQUICC Family Users Manual, Rev. 3 Freescale Semiconductor xxi

Page Number

ContentsParagraph Number 19.3.1 19.3.2 19.3.3 19.3.3.1 19.3.3.2 19.3.3.3 19.3.4 19.3.4.1 19.3.4.2 19.3.5 19.3.6 19.3.6.1 19.3.6.2 19.3.7 19.3.7.1 19.3.7.2 19.3.7.2.1 19.3.7.2.2 19.3.8 19.3.8.1 19.3.8.2 19.3.9 19.3.9.1 19.3.9.2 19.3.9.3 19.3.9.4 19.3.10 19.3.11 Title Page Number IDMA Features .......................................................................................................... 19-6 IDMA Parameter RAM ............................................................................................. 19-6 IDMA Registers......................................................................................................... 19-7 DMA Channel Mode Registers (DCMR) .............................................................. 19-8 IDMA Status Registers (IDSR1 and IDSR2) ........................................................ 19-8 IDMA Mask Registers (IDMR1 and IDMR2)....................................................... 19-9 IDMA Buffer Descriptors (BD)................................................................................. 19-9 Function Code RegistersSFCR and DFCR...................................................... 19-12 Auto-Buffering and Buffer-Chaining .................................................................. 19-12 IDMA CP Commands.............................................................................................. 19-13 IDMA Channel Operation ....................................................................................... 19-13 Activating an IDMA Channel.............................................................................. 19-13 Suspending an IDMA Channel............................................................................ 19-14 IDMA Interface SignalsDREQ and SDACK....................................................... 19-14 IDMA Requests for Memory/Memory Transfers ................................................ 19-14 IDMA Requests for Peripheral/Memory Transfers ............................................. 19-15 Level-Sensitive Requests................................................................................. 19-15 Edge-Sensitive Requests.................................................................................. 19-15 IDMA TransfersDual-Address and Single-Address ............................................ 19-16 Dual-Address (Dual-Cycle) Transfer................................................................... 19-16 Single-Address (Single-Cycle) Transfer (Fly-By)............................................... 19-16 Single-Buffer Mode on IDMA1A Special Case .................................................. 19-19 IDMA1 Channel Mode Register (DCMR) (Single-Buffer Mode) ...................... 19-20 IDMA1 Status Register (IDSR1) (Single-Buffer Mode) ..................................... 19-21 IDMA1 Mask Register (IDMR1) (Single-Buffer Mode) .................................... 19-21 Burst Timing (Single-Buffer Mode) .................................................................... 19-22 External Recognition of an IDMA Transfer ............................................................ 19-22 Interrupts During an IDMA Bus Transfer ............................................................... 19-23 Chapter 20 Serial Interface 20.1 20.2 20.2.1 20.2.2 20.2.3 20.2.3.1 20.2.3.2 20.2.3.3 SI Features ..................................................................................................................... 20-2 The Time-Slot Assigner (TSA)...................................................................................... 20-3 TSA Signals ............................................................................................................... 20-7 Enabling Connections to the TSA ............................................................................. 20-8 SI RAM...................................................................................................................... 20-9 Disabling and Reenabling the TSA ..................................................................... 20-10 One TDM Channel with Static Frames................................................................ 20-10 Two TDM Channels with Static Frames.............................................................. 20-10MPC860 PowerQUICC Family Users Manual, Rev. 3 xxii Freescale Semiconductor

ContentsParagraph Number 20.2.3.4 20.2.3.5 20.2.3.6 20.2.3.7 20.2.3.8 20.2.4 20.2.4.1 20.2.4.2 20.2.4.3 20.2.4.4 20.2.4.5 20.2.4.6 20.2.5 20.2.5.1 20.2.5.2 20.2.6 20.2.6.1 20.2.6.2 20.2.6.2.1 20.2.6.2.2 20.2.6.3 20.3 20.4 20.4.1 20.4.2 20.4.3 Title Page Number SI RAM Dynamic Changes ................................................................................. 20-11 One TDM Channel with Dynamic Frames.......................................................... 20-14 Two TDM Channels with Dynamic Frames ........................................................ 20-14 Programming the SI RAM................................................................................... 20-15 SI RAM Programming Example ......................................................................... 20-17 The SI Registers....................................................................................................... 20-18 SI Global Mode Register (SIGMR) ..................................................................... 20-18 SI Mode Register (SIMODE) .............................................................................. 20-19 SI Clock Route Register (SICR).......................................................................... 20-24 SI Command Register (SICMR).......................................................................... 20-25 SI Status Register (SISTR) .................................................................................. 20-26 SI RAM Pointer Register (SIRP)......................................................................... 20-27 IDL Bus Implementation ......................................................................................... 20-29 ISDN Terminal Adaptor Application................................................................... 20-30 Programming the IDL Interface........................................................................... 20-32 GCI Bus Implementation ......................................................................................... 20-33 GCI Activation/Deactivation ............................................................................... 20-35 Programming the GCI Interface .......................................................................... 20-35 Normal Mode................................................................................................... 20-35 SCIT Mode ...................................................................................................... 20-36 GCI Interface (SCIT Mode) Programming Example .......................................... 20-36 NMSI Configuration .................................................................................................... 20-37 Baud Rate Generators (BRGs)..................................................................................... 20-40 Baud Rate Generator Configuration Registers (BRGCn)........................................ 20-41 Autobaud Operation on the SCC UART.................................................................. 20-42 UART Baud Rate Examples .................................................................................... 20-43 Chapter 21 Serial Communications Controllers 21.1 21.2 21.2.1 21.2.2 21.2.3 21.2.4 21.3 21.4 21.4.1 21.4.2 Features .......................................................................................................................... 21-2 SCC Registers ............................................................................................................... 21-3 General SCC Mode Register (GSMR)....................................................................... 21-3 Protocol-Specific Mode Register (PSMR) .............................................................. 21-10 Data Synchronization Register (DSR)..................................................................... 21-10 Transmit-on-Demand Register (TODR) .................................................................. 21-11 SCC Buffer Descriptors (BDs) .................................................................................... 21-12 SCC Parameter RAM................................................................................................... 21-14 Function Code Registers (RFCR and TFCR) .......................................................... 21-16 Handling SCC Interrupts ......................................................................................... 21-16MPC860 PowerQUICC Family Users Manual, Rev. 3 Freescale Semiconductor xxiii

ContentsParagraph Number 21.4.3 21.4.4 21.4.4.1 21.4.4.2 21.4.5 21.4.5.1 21.4.6 21.4.7 21.4.7.1 21.4.7.2 21.4.7.3 21.4.7.4 21.4.7.5 21.4.8 Title Page Number SCC Initialization .................................................................................................... 21-17 Controlling SCC Timing with RTS, CTS, and CD.................................................. 21-18 Synchronous Protocols ........................................................................................ 21-18 Asynchronous Protocols ...................................................................................... 21-21 Digital Phase-Locked Loop (DPLL) Operation....................................................... 21-22 Encoding Data with a DPLL................................................................................ 21-24 Clock Glitch Detection ............................................................................................ 21-26 Reconfiguring the SCCs .......................................................................................... 21-26 General Reconfiguration Sequence for an SCC Transmitter............................... 21-26 Reset Sequence for an SCC Transmitter.............................................................. 21-27 General Reconfiguration Sequence for an SCC Receiver ................................... 21-27 Reset Sequence for an SCC Receiver.................................................................. 21-27 Switching Protocols ............................................................................................. 21-27 Saving Power ........................................................................................................... 21-28 Chapter 22 SCC UART Mode 22.1 22.2 22.3 22.4 22.5 22.6 22.7 22.8 22.9 22.10 22.11 22.12 22.13 22.14 22.15 22.16 22.17 22.18 22.19 22.20 22.21 22.22 Features .......................................................................................................................... 22-2 Normal Asynchronous Mode......................................................................................... 22-3 Synchronous Mode ........................................................................................................ 22-3 SCC UART Parameter RAM ......................................................................................... 22-4 Data-Handling Methods: Character- or Message-Based ............................................... 22-5 Error and Status Reporting............................................................................................. 22-6 SCC UART Commands ................................................................................................. 22-6 Multidrop Systems and Address Recognition ............................................................... 22-7 Receiving Control Characters ........................................................................................ 22-7 Hunt Mode (Receiver) ................................................................................................... 22-9 Inserting Control Characters into the Transmit Data Stream......................................... 22-9 Sending a Break (Transmitter)..................................................................................... 22-10 Sending a Preamble (Transmitter) ............................................................................... 22-10 Fractional Stop Bits (Transmitter) ............................................................................... 22-11 Handling Errors in the SCC UART Controller ............................................................ 22-12 UART Mode Register (PSMR).................................................................................... 22-13 SCC UART Receive Buffer Descriptor (RxBD) ......................................................... 22-15 SCC UART Transmit Buffer Descriptor (TxBD) ........................................................ 22-18 SCC UART Event Register (SCCE) and Mask Register (SCCM) .............................. 22-19 SCC UART Status Register (SCCS)............................................................................ 22-22 SCC UART Programming Example ............................................................................ 22-22 S-Records Loader Application..................................................................................... 22-24MPC860 PowerQUICC Family Users Manual, Rev. 3 xxiv Freescale Semiconductor

ContentsParagraph Number Title Chapter 23 SCC HDLC Mode 23.1 23.2 23.3 23.4 23.5 23.6 23.7 23.8 23.9 23.10 23.11 23.12 23.13 23.13.1 23.13.2 23.14 23.14.1 23.14.2 23.14.3 23.14.4 23.14.5 23.14.6 23.14.6.1 23.14.6.2 SCC HDLC Features ..................................................................................................... 23-1 SCC HDLC Channel Frame Transmission .................................................................... 23-2 SCC HDLC Channel Frame Reception ......................................................................... 23-3 SCC HDLC Parameter RAM......................................................................................... 23-3 Programming the SCC HDLC Controller...................................................................... 23-5 SCC HDLC Commands................................................................................................. 23-5 Handling Errors in the SCC HDLC Controller.............................................................. 23-6 HDLC Mode Register (PSMR)...................................................................................... 23-7 SCC HDLC Receive Buffer Descriptor (RxBD) ........................................................... 23-9 SCC HDLC Transmit Buffer Descriptor (TxBD)........................................................ 23-12 HDLC Event Register (SCCE)/HDLC Mask Register (SCCM) ................................. 23-13 SCC HDLC Status Register (SCCS)............................................................................ 23-15 SCC HDLC Programming Examples .......................................................................... 23-16 SCC HDLC Programming Example #1................................................................... 23-16 SCC HDLC Programming Example #2................................................................... 23-18 HDLC Bus Mode with Collision Detection................................................................. 23-18 HDLC Bus Features................................................................................................. 23-21 Accessing the HDLC Bus ........................................................................................ 23-21 Increasing Performance ........................................................................................... 23-22 Delayed RTS Mode.................................................................................................. 23-23 Using the Time-Slot Assigner (TSA) ...................................................................... 23-24 HDLC Bus Protocol Programming.......................................................................... 23-25 Programming GSMR and PSMR for the HDLC Bus Protocol ........................... 23-25 HDLC Bus Controller Programming Example.................................................... 23-25 Chapter 24 SCC AppleTalk Mode 24.1 24.2 24.3 24.4 24.4.1 24.4.2 24.4.3 24.4.4 Operating the LocalTalk Bus ......................................................................................... 24-1 Features .......................................................................................................................... 24-2 Connecting to AppleTalk ............................................................................................... 24-2 Programming the SCC in AppleTalk Mode................................................................... 24-3 Programming the GSMR ........................................................................................... 24-3 Programming the PSMR............................................................................................ 24-4 Programming the TODR............................................................................................ 24-4 SCC AppleTalk Programming Example.................................................................... 24-4 Page Number

MPC860 PowerQUICC Family Users Manual, Rev. 3 Freescale Semiconductor xxv

ContentsParagraph Number Title Chapter 25 SCC Asynchronous HDLC Mode and IrDA 25.1 25.2 25.3 25.4 25.5 25.6 25.7 25.8 25.9 25.9.1 25.9.2 25.10 25.11 25.12 25.13 25.13.1 25.13.2 25.13.3 25.14 25.15 25.16 25.17 25.18 Asynchronous HDLC Features ...................................................................................... 25-1 Asynchronous HDLC Frame Transmission Processing................................................. 25-1 Asynchronous HDLC Frame Reception Processing...................................................... 25-2 Transmitter Transparency Encoding .............................................................................. 25-3 Receiver Transparency Decoding .................................................................................. 25-3 Exceptions to RFC 1549 ................................................................................................ 25-4 Asynchronous HDLC Channel Implementation............................................................ 25-5 Asynchronous HD