MPC5643L Dual Motor Controller Board User GuideR363 populated M1 PFC UNI-3 M1 PFC output signal is...

MPC5643L Dual Motor Controller Board User Guide

Devices Supported:MPC5643L

Document Number: MPC5643LDMCBUG

Rev.007/2012

MPC5643L Dual Motor Controller Board User Guide, Rev.0

Freescale Semiconductor 1


2 Freescale Semiconductor

Petr Konvicny

Freescale Semiconductor

Roznov Czech System Center

About This BookThis document describes the MPC5643L Controller Board design targeted for rapid development of motor control applications.

To locate any published updates for this document, refer to the Freescale website at: http://www.freescale.com/.

Revision History

Documentation

The MPC5643L documentation is available on the Freescale web site, http://www.freescale.com:

• Reference manuals — MPC5643L modules in detail

• Data sheets — Information mainly on the device’s AC, DC, thermal characteristics, and packages pin-out

• Product briefs — Device overview

• Application notes — Addresses specific design issues

Table i. Revision history table

DateRevision

levelDescription

Page number(s)

08/08/2012 0 Initial release N/A



http://www.freescale.com

http://www.freescale.com/coldfire/

Chapter 1 Introduction1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71.2 MPC5643L Dual Motor Controller Board architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . .81.3 Board jumper configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101.4 Board LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Chapter 2 Interface Description2.1 Power supply J100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152.2 UNI3 Interface J300, and J304 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152.3 MC33937A interface J303 and J305 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182.4 Resolver connector J200 and J207 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192.5 Encoder/Hall connector J500 and J501 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202.6 LIN connector J101 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212.7 CAN connector J102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212.8 USB Connector J14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222.9 Header J1 and J4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222.10 Header J3, J6, and J8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242.11 Header J11 and J12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252.12 Header J13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Chapter 3 Design Consideration3.1 MPC5643L features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273.2 Clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303.3 UNI3 interfaces and external fault management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303.4 Encoder/Hall sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323.5 Resolver and SinCos sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333.6 Analog signal sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373.7 Power supplies and voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373.8 UNI-3 PFC-PWM signal (power factor correction) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .383.9 UNI-3 brake signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .383.10 CAN Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .383.11 FlexRAY interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Chapter 4 Electrical Characteristics

Chapter 5 Board Setup Guide

Chapter 6 MPC5643L Dual Motor Controller Board Schematics


Introduction

Chapter 1 IntroductionThe Freescale MPC5643L Dual Motor Controller Board is a controller board integrated into the Freescale embedded motion-control series of development tools. It is supplied with a universal interface interconnecting with one of the embedded motion-power stages or evaluation boards, providing a ready-made software-development platform for various electrical motors, and DC/DC converters.

The MPC5643L Dual Motor Controller Board is an evaluation-module type of board that includes an MPC5643L device, various position sensing interfaces, communication options, digital and analog power supplies, and peripheral expansion connectors. The expansion connectors are intended for signal monitoring and user expandability. Test pads are provided for monitoring critical signals and voltage levels.

The MPC5643L Dual Motor Controller Board facilitates the evaluation of various features in the MPC5643L. It can be used to develop real-time software and hardware products based on the MPC5643L in MAPBGA257 package. It provides the features necessary for you to write and debug software, demonstrate software function, and to interface with customer application specific devices. The MPC5643L Dual Motor Controller Board is flexible and allows you to fully exploit the MPC5643L features and optimize product performance. See Figure 1-1.

1.1 FeaturesThe MPC5643L Dual Motor Controller Board evaluates various features in the MPC5643L. The following are board features:

• MPC5643L microcontroller, MAPBGA257 package

• JTAG/NEXUS interfaces for MCU code download and debugging

• System-basis chip MCZ33905D

• Motor control interface:

— Two UNI-3

— Two MC33937A predriver

— Two Resolver

— Two Encoder/Hall sensors

• Connectivity interface:

— LIN

— CAN

— FlexRay

— USB interface

• LEDs:

— Power-supply indicators

— PWM control signals

— Faults monitoring

— SBC safe mode

— User application



Introduction

• Two push buttons and switch for application control

• MCU pins accessible via pin headers

• Power plug 2.1 mm connector

1.2 MPC5643L Dual Motor Controller Board architectureThe MPC5643L Dual Motor Controller Board is flexible enough to allow to fully exploit the MPC5643L features and optimize performance of their product. Its basic building blocks are shown in (see Figure 1-1). The block colors differentiate a block function:

• Blue — MCU and application software download and the debug interface

• Green — Motor control related hardware

• Red — Board power supply and connectivity

• Violet — Application control

Figure 1-1. MPC5643L controller board block diagram

The board can be supplied by VBAT voltage in the range of 8 V to 18 V. The MC33905 provides two independent voltage sources, the first for supplying the MCU and the second for auxiliary logic. Both sources provide either 3.3 V or 5 V, depending on the assembled SBC version.

The UNI-3 expansion interface enables the MCU to direct control of the electrical motor or DC/DC converters.



Introduction

The Fault logic triggers several important system faults as described. The circuitry behavior depends on the selected configuration. For more information see Chapter 3.3, “UNI3 interfaces and external fault management".

The application can be controlled using the switches USB interface (RS232), CAN, and LIN buses.

The JTAG/NEXUS interfaces are present on-board to enable download and debug MCU code.

For the on-board block location, see Figure 1-1.

Figure 1-2. MPC5643L Dual Motor Controller Board block location



Introduction

1.3 Board jumper configuration

See Table 1-1 and Figure 1-3 for proper jumper configuration.

Table 1-1. MPC5643L board configuration

Jumper Selector Function Connections

JP100 JP101

CANTermination

Terminate CAN bus node Closed

JP102MC33905

debug modeEnter SBC driver MC33905 to debug mode Closed

JP103MC33905save mode

Enter SBC driver MC33905 to safe mode Closed

JP206 Resolver EnableResolver reference input signal from SWG module 1–2

Resolver reference input signal from eTimer1-channel5 2–3

J202J209

Resolver SIN input

Positive input for SIN OPAM is DC offset voltage set up by trimmer R208, R258

1–2

Positive input for SIN OPAM is REFSIN input of resolver 2–3

J205J212

Resolver COS input

Positive input for COS OPAM is DC offset voltage set up by trimmer R208, R258

1–2

Positive input for COS OPAM is REFCOS input of resolver 2–3

J201J208

Phase Adigital signal

Resolver_X Phase A signals is connected to eTimer0-channel[0] resp. eTimer1-channel[1]

Closed

Resolver_X Phase A signals is not connected to eTimer0-channel[0] resp. eTimer1-channel[1].

Closed

J203J210

Phase Bdigital signal

Resolver_X Phase B signals is connected to eTimer0-channel[1] resp. eTimer1-channel[1].

Closed

Resolver_X Phase B signals is not connected to eTimer0-channel[1] resp. eTimer1-channel[1].

Closed

J301 FAULT1 selection

UNI-3 M1 Phase A over-current signal is connected to FAULT1 input G[9].

1–2

UNI-3 M1 DC-bus over-current signal is connected to FAULT1 input G[9].

2–3

J302 FAULT5 selection

UNI-3 M2 Phase A over-current signal is connected to FAULT5 input I[1].

1–2

UNI-3 M2 DC-bus over-current signal is connected to FAULT5 input I[1].

2–3

J17 J18 J19

BOOT selectionFAB — MPC5643L boot from internal Flash.ABS0 — See MPC5643L documentationABS1 — See MPC5643L documentation

Closed



Introduction

J500Encoder 1Phase A

Encoder1 JP500 pin three “PHASE A” is connected to eTimer0-channel[0].

1–2

UNI-3 “M1_BEMFZCA” is connected to eTimer0-channel[0]. 2–3

J501Encoder 1Phase B

Encoder1 JP500 pin four “PHASE B” is connected to eTimer0-channel[1].

1–2

UNI-3 “M1_BEMFZCB” input signal is connected to eTimer0-channel[1].

2–3

J502Encoder 1

Index

Encoder1 JP500 pin five “INDEX” is connected to eTimer0-channel[4].

1–2

UNI-3 “M1_BEMFZCC” input signal is connected to eTimer0-channel[4].

2–3

J503Encoder 1

HomeEncoder1 JP500 pin six “HOME” is connected to

eTimer0-channel[5].Closed

J504Encoder 2Phase A

Encoder2 JP501 pin three “PHASE A” is connected to eTimer1-channel[1].

1–2

UNI-3 “M2_BEMFZCA” input signal is connected to eTimer1-channel[1].

2–3

J505Encoder 2Phase B

Encoder2 JP501 pin four “PHASE B” is connected to eTimer1-channel[2].

1–2

UNI-3 “M2_BEMFZCB” input signal is connected to eTimer1-channel[2].

2–3

J506Encoder 2

Index

Encoder2 JP501 pin five “INDEX” is connected to eTimer1-channel[3].

1–2

UNI-3 “M2_BEMFZCC” input signal is connected to eTimer1-channel[3].

2–3

J507Encoder 2

HomeEncoder2 JP501 pin six “HOME” is connected to

eTimer1-channel[4].closed

M1 DC BUS Voltage

M1 DC BUS Voltage signal from UNI-3 is connected to GPIO B[8], ADC0 channel1.

R336 populated

M1 DC BUS Current

M1 DC BUS Current signal from UNI-3 is connected to GPIO B[14], ADC1 channel1.

R338 populated

M2 DC BUS Voltage

M2 DC BUS Voltage signal from UNI-3 is connected to GPIO C[0], ADC0 channel3.

R337 populated

M2 DC BUS Current

M2 DC BUS Current signal from UNI-3 is connected to GPIO C[2], ADC1 channel3.

R339 populated

Table 1-1. MPC5643L board configuration (continued)




Introduction

Analog input 11

UNI-3 M1 Phase A current is connected to GPIO B[9], ADC 0/1 input 11.

R343 populated

UNI-3 M1 Phase A Back-EMF Voltage is connected to GPIO B[9], ADC 0/1 input 11.

R348 populated

Analog input 12

UNI-3 M1 Phase B current is connected to GPIO B[10], ADC 0/1 input 12.

R352 populated

UNI-3 M1 Phase B Back-EMF Voltage is connected to GPIO B[10]m ADC 0/1 input 12.

R354 populated

ADC0 Analog input 2

UNI-3 M1 Phase C current is connected to GPIO C[1], ADC 0 input 2.

R358 populated

UNI-3 M1 Phase C Back-EMF Voltage is connected to GPIO C[1]m ADC 0 input 2.

R360 populated

Analog input 13

UNI-3 M2 Phase A current is connected to GPIO B[11], ADC 0/1 input 13.

R344 populated

UNI-3 M2 Phase A Back-EMF Voltage is connected to GPIO B[11], ADC 0/1 input 13.

R349 populated

Analog input 14

UNI-3 M2 Phase B current is connected to GPIO B[12], ADC 0/1 input 14.

R353 populated

UNI-3 M2 Phase B Back-EMF Voltage is connected to GPIO B[12]m ADC 0/1 input 14.

R355 populated

ADC1 Analog input 2

UNI-3 M2 Phase C current is connected to GPIO B[15], ADC 1 input 2.

R359 populated

UNI-3 M2 Phase C Back-EMF Voltage is connected to GPIO B[15]m ADC 1 input 2.

R361 populated

M1 TEMP UNI-3 Temperature signal is connected to ADC0 input four.R370

populated

M2 TEMP UNI-3 Temperature signal is connected to ADC1 input four.R371

populated

M1 BRAKEUNI-3 M1 Brake output signal is connected to GPIO G[6]

(PWM0-A3).R362

populated

M2 BRAKEUNI-3 M2 Brake output signal is connected to GPIO H[14]

(PWM1-A3).R363

populated

M1 PFCUNI-3 M1 PFC output signal is connected to GPIO G[7]

(PWM0-B3).R364

populated

M2 PFCUNI-3 M2 PFC output signal is connected to GPIO H[15]

(PWM1-B3).R365

populated





Introduction

Figure 1-3. MPC5643L board jumper position

M1 PFC_EN UNI-3 M1 PFC Enable signal is connected to GPIO C[10].R366

populated

M2 PFC_EN UNI-3 M2 PFC Enable signal is connected to GPIO E[13].R367

populated





Introduction

1.4 Board LEDsThe Table 1-2 displays the on-board LEDs. For on-board LED locations, see Figure 1-2.

Table 1-2. On-board LEDs

LED Signal Name Description

D112 +12 V +12 V power supply input

D107 /SAFE MCZ33905 safe pin state (ON - SBC in safe mode)

D113 MCU_3.3V + 3.3 V MCU power supply

D114 PER_3.3V + 3.3 V AUX power supply

D1 PWM0 B0 Motor 1 Phase A bottom switch signal

D2 PWM0 B1 Motor 1 Phase B bottom switch signal

D3 PWM0 B2 Motor 1 Phase C bottom switch signal

D4 PWM0 A2 Motor 1 Phase C top switch signal

D5 PWM0 A1 Motor 1 Phase B top switch signal

D6 PWM0 A0 Motor 1 Phase A top switch signal

D7 PWM1 B0 Motor 2 Phase A bottom switch signal

D8 PWM1 B1 Motor 2 Phase B bottom switch signal

D9 PWM1 B2 Motor 2 Phase C bottom switch signal

D10 PWM1 A2 Motor 2 Phase C top switch signal

D11 PWM1 A1 Motor 2 Phase B top switch signal

D12 PWM1 A0 Motor 2 Phase A top switch signal

D13 FAULTB1 Motor 1 FAULTB1 signal






D19 A12 User LED 1


D21 PWM0 A3 PWM module 0, A3 output

D22 A13 User LED 1

D23 PWM0 B3 PWM module 0, B3 output




Interface Description

Chapter 2 Interface DescriptionThe following chapters summarize the on-board connectors and headers pin-outs, signal meanings, and MCU pin assignments.

2.1 Power supply J100The MPC5643L Dual Motor Controller Board can be supplied either by using the 2.1 mm DC power plug, J100, or the UNI-3 connectors (J300, J304, pin 19).

The controller board is powered by two independent voltage regulators that provide 5 V for auxiliary logic and 5 V for MCU and debugger logic. Both voltages are generated by the MC33905 SBC integrated circuit. Proper operation is monitored by LEDs D113 for the MCU 3.3 V line and D114 for the AUX 3.3 V line (see Table 1-2).

The board is designed to operate in the voltage range from 8 V to 18 V. The board is protected against a reverse battery.

2.2 UNI3 Interface J300, and J304The UNI-3 interface (connector J300, J304) defines the interface between the MPC5643L Dual Motor Controller Board and a 3 phase electrical motor power stages.

The list of UNI-3 signals:

• Control signals:

— PWM phase A, B, C top and bottom switches control

— Brake signal control

— Power Factor Correction (PFC)

• Monitor signals

— DC-bus voltage

— DC-bus current

— Phase A, B, C current

— Zero-cross signals

— Back-EMF phase A, B, C

— Temperature monitoring

• Power Supply 12 V

• Serial line — A bidirectional communication line between the controller board and power stage

Table 2-1 defines the UNI-3 pin-out and pin assignment to the MCU.




Table 2-1. Motor 1 — UNI-3 signal description

Interface Pin Signal Name MCU Signal Description Direction

1 PWM_AT PWM0_A0 Phase A top switch control (H -> Turn OFF) Digital output

3 PWM_AB PWM0_B0 Phase A bottom switch control (H -> Turn ON) Digital output

5 PWM_BT PWM0_A1 Phase B top switch control (H -> Turn OFF) Digital output

7 PWM_BB PWM0_B1 Phase B bottom switch control (H -> Turn ON) Digital output

9 PWM_CT PWM0_A2 Phase C top switch control (H -> Turn OFF) Digital output

11 PWM_CB PWM0_B2 Phase C bottom switch control (H -> Turn ON) Digital output

2, 4, 6, 8, 10 Shield– PWM signals shield

(grounded on the power stage side only)–

12,13 GND_D – Digital power supply ground –

14, 15 +5 V DC – +5 V digital power supply –

17, 18 AGND – Analog power supply ground –

19 +12/+15 V DC – Analog power supply –

16,20, 27, 28,37 NC – Not connected –

21 VDCBUS B[8] DC-bus voltage sensing, 0 V – 3.3 V, ADC0 channel 1

Analog input

22 IDCBUS B[14] DC-bus current sensing, 0 V – 3.3 V, ADC1 channel 1

Analog input

23 IA B[9] Phase A current sensing, 0 V – 3.3 V, ADCx channel 11

Analog input

24 IB B[10] Phase B current sensing, 0 V – 3.3 V, ADCx channel 12

Analog input

25 IC C[1] Phase C current sensing, 0 V – 3.3 V, ADC0 channel 2

Analog input

26 TEMP E[6] Analog temperature 0 V – 3.3 V, ADC0 channel 4 Analog input

29 BRAKE_CONT PWM0_A3 DC-bus brake control Digital output

30 SERIAL – Serial interface Digital bidirectional

31 PFC – Power factor correction PWM Digital output

32 PFCEN – Power factor correction enable Digital output

33 PFCZC – Power factor correction Zero-cross Digital input

34 ZCA D[9] or A[0] Phase A Back-EMF zero crossing Digital input

35 ZCB D[12] or A[1] Phase B Back-EMF zero crossing Digital input

36 ZCC G[2] or C[11] Phase C Back-EMF zero crossing Digital input

38 Back-EMF_A B[9] Phase A Back-EMF voltage sensing Analog input




39 Back-EMF_B B[10] Phase B Back-EMF voltage sensing Analog input

40 Back-EMF_C C[1] Phase C Back-EMF voltage sensing Analog input

Table 2-2. Motor 2 — UNI-3 signal description


1 PWM_AT PWM1_A0 Phase A top switch control (H -> Turn OFF) Digital output

3 PWM_AB PWM1_B0 Phase A bottom switch control (H -> Turn ON) Digital output

5 PWM_BT PWM1_A1 Phase B top switch control (H -> Turn OFF) Digital output

7 PWM_BB PWM1_B1 Phase B bottom switch control (H -> Turn ON) Digital output

9 PWM_CT PWM1_A2 Phase C top switch control (H -> Turn OFF) Digital output

11 PWM_CB PWM1_B2 Phase C bottom switch control (H -> Turn ON) Digital output

2, 4, 6, 8, 10 Shield– PWM signals shield

(grounded on the power stage side only)–

12,13 GND_D – Digital power supply ground –

14, 15 +5V DC – +5 V digital power supply –

17, 18 AGND – Analog power supply ground –

19 +12/+15V DC – Analog power supply –

16,20, 27, 28,37 NC – Not connected –

21 VDCBUS C[2] DC-bus voltage sensing, 0 V – 3.3 V, ADC0 channel 3

Analog input

22 IDCBUS C[0] DC-bus current sensing, 0 V – 3.3 V, ADC1 channel 3

Analog input

23 IA B[11] Phase A current sensing, 0 V – 3.3 V, ADCx channel 13

Analog input

24 IB B[12] Phase B current sensing, 0 V – 3.3 V, ADCx channel 14

Analog input

25 IC B[15] Phase C current sensing, 0 V – 3.3 V, ADC1 channel 2

Analog input

26 TEMP E[6] Analog temperature 0 V – 3.3 V, ADC0 channel 4 Analog input

29 BRAKE_CONT PWM1_A3 DC-bus brake control Digital output

30 SERIAL – Serial interface Dig. bidirectional

31 PFC PWM1_B3 Power factor correction PWM Digital output

32 PFCEN E[13] Power factor correction enable Digital output

33 PFCZC – Power factor correction Zero-cross Digital input

34 ZCA H[4] or C[13] Phase A Back-EMF zero crossing Digital input

Table 2-1. Motor 1 — UNI-3 signal description (continued)





2.3 MC33937A interface J303 and J305While using Freescale 3-phase power stages, the electrical inverter switches are controlled by the MC33937A pre-driver. The device behavior is configured by this interface, see Table 2-3.

35 ZCB H[7] or C[14] Phase B Back-EMF zero crossing Digital input

36 ZCC H[10] or F[12] Phase C Back-EMF zero crossing Digital input

38 Back-EMF_A B[11] Phase A Back-EMF voltage sensing Analog input

39 Back-EMF_B B[12] Phase B Back-EMF voltage sensing Analog input

40 Back-EMF_C B[15] Phase C Back-EMF voltage sensing Analog input

Table 2-3. Motor 1 — MC33937A signal description


1 NC – Not connected –


3 MC33937_EN A[11] Motor 1 device-enable output Digital output

4 MC33937_OC D[6] Over-current input Digital input

5 MC33937_/RST A[10] Reset output. Active in low Digital output

6 MC33937_INT D[5] Interrupt pin Digital input

7 MC33937_SOUT DSPI0_SINInput data from MC33937 SPI port. Tri-state

until CS becomes low.Digital input

8 MC33937_SCK DSPI0_SCK Clock for SPI port. Output. Digital output

9 MC33937_CS DSPI0_/CS0Chip-select 0 output. It frames SPI command and enables SPI port.

Digital output

10 MC33937_SIN DSPI0_SOUT Output data for MC33937 SPI port. Clocked on the falling edge of SCLK, MSB first.

Digital output

Table 2-4. Motor 2 — MC33937A signal description




3 MC33937_EN A[9] Motor 2 device-enable output Digital output

4 MC33937_OC D[6] Over-current input Digital input

5 MC33937_/RST A[10] Reset output. Active in low Digital output

6 MC33937_INT D[5] Interrupt pin Digital input

Table 2-2. Motor 2 — UNI-3 signal description (continued)





2.4 Resolver connector J200 and J207The controller board calculates motor rotor position from two resolver or SIN/COS sensors. They are connected to the board through connectors J200 resp. J207. Table 2-5 and Table 2-6 shows the pin description for resolver 1 and for resolver 2.

7 MC33937_SOUT DSPI0_SIN Input data from MC33937 SPI port. Tri-state until CS becomes low.

Digital input

8 MC33937_SCK DSPI0_SCK Clock for SPI port. Output Digital output

9 MC33937_CS DSPI0_/CS1 Chip-select 1 output. It frames SPI command and enables SPI port.

Digital output

10 MC33937_SIN DSPI0_SOUT Output data for MC33937 SPI port. Clocked on the falling edge of SCLK, MSB first.

Digital output

Table 2-5. Resolver 1 signal description


1 RES1_E_R1 – Positive sinusoidal reference signal for resolver Signal output range from 0 V up to +12 V

Output

2 RES1_E_R2 – Negative sinusoidal reference signal for resolver Signal output range from 0 V up to +12 V

Output

3 RES1_E_S2 – SIN input signal Differential analog input

4 RES1_E_S4 – SIN reference input signal Differential analog input

5 RES1_E_S1 – COS input signal Differential analog input

6 RES1_E_S3 – COS reference input signal Differential analog input

7 GNDA – Analog ground –


Table 2-6. Resolver 2 signal description


1 RES2_E_R1 – Positive sinusoidal reference signal for resolver Signal output range from 0 V up to +12 V

Output

2 RES2_E_R2 – Negative sinusoidal reference signal for resolver Signal output range from 0 V up to +12 V

Output

3 RES2_E_S2 – SIN input signal Differential analog input

Table 2-4. Motor 2 — MC33937A signal description (continued)





2.5 Encoder/Hall connector J500 and J501The motor rotor position can be transformed from encoder or Hall rotor position sensor. They can be connected to the board through connector J500 and J501. For proper signal connections, see Table 2-7.

4 RES2_E_S4 – SIN reference input signal Differential analog input

5 RES2_E_S1 – COS input signal Differential analog input

6 RES2_E_S3 – COS reference input signal Differential analog input



Table 2-7. Encoder/Hall signal description

Interface Pin Signal Name MCU Port Description Direction

1 +5 Vdc – +5 V sensor supply voltage –

2 GND – Ground –

3 ENC1_PhaseA / HALL0

ENC2_PhaseA / HALL0

A[0]

C[13]

Digital input signal phase A or Hall 0 input signal Digital input

4 ENC1_PhaseB / HALL1

ENC2_PhaseB / HALL1

A[1]

C[14]

Digital input signals phase B or Hall 1 input signal Digital input

5 ENC1_INDEX / HALL2

ENC2_INDEX / HALL2

C[11]

F[12]

Digital input signals INDEX or Hall 2 input signal Digital input

6 ENC1_HOME ENC2_HOME

C[12]F[13]

Digital input signals HOME Digital input

Table 2-8. J7 Header signal description


1 ENC1_PHA A[0] Encoder 1 digital input signal phase A. Digital input

2 ENC2_PHA C[13] Encoder 2 digital input signal phase A. Digital input

3 ENC1_PHB A[1] Encoder 1 digital input signal phase B. Digital input

4 ENC2_PHB C[14] Encoder 2 digital input signal phase B. Digital input

5 ENC1_INDEX C[11] Encoder 1 digital input signal INDEX. Digital input

Table 2-6. Resolver 2 signal description (continued)





2.6 LIN connector J101The MC33905 LIN transceiver is used as an on-board LIN hardware interface. The LIN node can be configured to either the Master or Slave mode, see Table 1-1.

A Table 2-9 shows the LIN connector pin-out and pin assignment to the MCU

2.7 CAN connector J102The system basis chip MC33905 CAN transceiver is used as the CAN hardware interface. On-board jumpers JP101, JP102 enable node termination, impedance of 120R, see Table 1-1.

Table 2-11 shows the CAN connector pin-out and pin assignment to the MCU.

6 ENC2_INDEX F[12] Encoder 2 digital input signal INDEX. Digital input

7 ENC1_HOME C[12] Encoder 1 digital input signal HOME. Digital input

8 ENC2_HOME F[13] Encoder 2 digital input signal HOME. Digital input

Table 2-9. LIN signal description



2 VSUP – Power Supply –


4 LIN LIN1_RXD / LIN1_TXD

LIN bus Digital bidirectional

Table 2-10. Header J5 signal description


1 LIN0_RXD B[3] LIN module 0 receive input Digital input

2 LIN0_TXD B[2] LIN module 0 transmit output Digital output



5 LIN1_RXD F[15] LIN module 1 receive input Digital input

6 LIN1_TXD F[14] LIN module 1 transmit output Digital output

Table 2-8. J7 Header signal description (continued)





2.8 USB Connector J14The USB line is used for board communication with the PC, when using for example Freescale FreeMASTER tool to control and visualize the user application.

The interface uses an A type connector which is isolated from the board environment. See Table 2-13 for the pin description and pin assignment to the MCU.

2.9 Header J1 and J4Monitoring the PWM signal is possible using J1 or J4. The Table 2-14 summarizes the header pin-out.

Table 2-11. CAN signal description


1 CANH CAN0_RXD / CAN0_TXD

CAN bus H Diff. bidirectional

2 CANL CAN0_RXD / CAN0_TXD

CAN bus L Diff. bidirectional





1 CAN0_RX_PHY – – –

2 CAN0_TX_PHY – – –

3 CAN0_RXD B[1] CAN module 0 receive input Digital input

4 CAN0_TXD B[0] CAN module 0 receive output Digital output

5 CAN1_RX_PHY – – –

6 CAN1_TX_PHY – – –

7 CAN1_RXD A[15] CAN module 1 receive input Digital input

8 CAN1_TXD A[14] CAN module 1 receive output Digital output

Table 2-13. USB signal description


1 VBUS – USB Power Supply –

2 D- LIN0_RXD / LIN0_TXD

Data – Dig. bidirectional

3 D+ LIN0_RXD / LIN0_TXD

Data + Dig. bidirectional

4 GNDB – USB Ground –




Table 2-14. J1 signal description


1 PWM0_A0 D[10] Motor 1 — Phase A top switch control Digital output

2 PWM0_B0 D[11] Motor 1 — Phase A bottom switch control Digital output

3 PWM0_A1 F[0] Motor 1 — Phase B top switch control Digital output

4 PWM0_B1 D[14] Motor 1 — Phase B bottom switch control Digital output

5 PWM0_A2 G[3] Motor 1 — Phase C top switch control Digital output

6 PWM0_B2 G[4] Motor 1 — Phase C bottom switch control Digital output

7 FAULTB0 G[8] PWM module 0 fault input 0 Digital input




11 PWM0_X0 D[9] PWM module 0 auxiliary PWM signal 0 Digital input/output

12 PWM0_X1 D[12] PWM module 0 auxiliary PWM signal 1 Digital input/output

13 PWM0_X2 G[2] PWM module 0 auxiliary PWM signal 2 Digital input/output

14 GND - Ground

Table 2-15. J4 signal description


1 PWM1_A0 H[5] Motor 2 — Phase A top switch control Digital output

2 PWM1_B0 H[6] Motor 2 — Phase A bottom switch control Digital output

3 PWM1_A1 H[8] Motor 2 — Phase B top switch control Digital output

4 PWM1_B1 H[9] Motor 2 — Phase B bottom switch control Digital output

5 PWM1_A2 H[11] Motor 2 — Phase C top switch control Digital output

6 PWM1_B2 H[12] Motor 2 — Phase C bottom switch control Digital output

7 FAULTB4 I[0] PWM module 1 fault input 0 Digital input



10 FAULTB7 I[3 PWM module 1 fault input 3 Digital input

11 PWM1_X0 H[4] PWM module 1 auxiliary PWM signal 0 Digital input/output

12 PWM1_X1 H[7] PWM module 1 auxiliary PWM signal 1 Digital input/output




2.10 Header J3, J6, and J8Headers J3, J6, and J8 allow monitoring the analog-to-digital converter signals, see Table 2-16.

13 PWM1_X2 H[10 PWM module 1 auxiliary PWM signal 2 Digital input/output




1 ADC0_AN0 B[7] ADC module 0 channel 0 input Analog input


3 ADC0_AN2 C[1] ADC module 0 channel 2 input Analog input


5 ADC0_AN4 E[6] ADC module 0 channel 4 input Analog input




9 SWG_OUT D[7] Sinewave generator output1 Analog output


11 +3.3 VA2 – +3.3 V analogue voltage –

12 GNDA – Analogue ground –











9 NC – – –


Table 2-15. J4 signal description (continued)





2.11 Header J11 and J12Headers J11, and J12 allow monitoring the miscellaneous digital signals. See Table 2-19 and Table 2-20.





1 ADC0/1_AN11 B[9] ADC module 0/1 channel 11 input Analog input








1 A12 A[12] Digital input / output Digital I/O


3 FCCU_F0 G[0] FCCU output F[0] Digital output

4 FCCU_F1 G[1] FCCU output F[1] Digital output

5 +3.3 Vdc – +3.3 V voltage –




1 F3 F[3] Digital input / output Digital I/O


3 E13 E[13] Digital input / output Digital I/O


5 C10 C[10] Digital input / output Digital I/O

6 eTimer1_CH5 E[14] Digital input / output Digital I/O


8 NC – – –

Table 2-17. Header J6 signal description (continued)





2.12 Header J13Headers J13 allow monitoring the DSPI module 1 digital signals. See Table 2-21.



1 DSPI1_SOUT A[7] DSPI module 1 serial data output Digital output

2 DSPI1_SIN A[8] DSPI module 1 serial data input Digital input

3 DSPI1_SCK A[6] DSPI module 1 clock Digital output

4 DSPI1_/CS0 A[5] DSPI module 1 chip select 0 Digital output

5 DSPI1_/CS2 D[8] DSPI module 1 chip select 2 Digital output




Design Consideration

Chapter 3 Design ConsiderationThe MPC5643L Dual Motor Controller Board demonstrates the ability of the Freescale MPC5643L device to control various electrical motors and easier development of the motor-control applications. In addition to the hardware needed to run a motor, a variety of feedback signals that facilitate control-algorithm development are provided. A set of schematics for the controller board appears in the following section.

3.1 MPC5643L featuresThe MPC5643L is a member of the family of microcontrollers based on Power ArchitectureTM. It targets electric power steering, chassis and safety market segment, and safety applications that require a high safety integrity level. The MPC5643L devices are built around a dual-core safety platform with an innovative safety concept targeting ISO26262 ASILD and IEC61508 SIL3 integrity levels. To minimize additional software and module level features to reach this target; on-chip redundancy is provided for the critical components of the microcontroller:

• CPU core

• DMA controller

• Interrupt controller

• Crossbar bus system

• Memory protection unit

• Flash-memory controller and RAM controllers

• Peripheral bus bridge

• System timers

• Watchdog timer

Lock step Redundancy Checking Units are implemented at each output of this Sphere of Replication (SoR). ECC is available for on-chip RAM and flash memories. A programmable fault collection and control unit monitors the integrity status of the device and provides flexible safe state control.

The MPC5643L has included two e200z4 cores that can be used in lock-step mode (LSM) or decoupled parallel mode (DPM). The maximal execution speed is 120 MHz.

The peripheral set is compatible with the MPC5604P device family and provides high-end electrical motor control capability with very low CPU load. This is due to special motor control peripherals like cross-triggering unit, flexPWM, eTimer, and ADC modules. The timer functions of MPC5643L are performed by the eTimer — Modular Timer System and FlexPWM. The three eTimer modules implement enhanced timer features (six channels each for a total of 18) including dedicated motor-control quadrature-decode function and DMA support. Two FlexPWM modules provides capability to independent control two 3-phase PMSM/BLDC motors. Each consist of four submodules controlling a pair of PWM channels. Three submodules may be used to control the three phases of a motor and the additional pair to support the DC-DC converter width modulation control. The SWG Sine Wave Generator module generates high-quality sinusoidal voltage in output frequency range 1 – 50 kHz.

Off-chip communication is performed by a suite of serial protocols including FlexRay, CANs, enhanced SPIs (DSPI), and SCIs (LinFlex).




The System Integration Unit Lite (SIUL) performs several chip-wide configuration functions. Pad configuration and General-Purpose Input and Output (GPIO) are controlled from SIUL. External interrupts and reset control are also found in the SIUL. The internal Multiplexer sub-block (IOMUX) provides multiplexing of daisy chaining the DSPIs and external interrupt signal.

You can find a detailed description of the MCU in the data sheet or reference manual.




Figure 3-1. MCPC5643L block diagram




3.2 Clock sourceThe MPC5643L uses an external 8.00 MHz crystal oscillator mounted on the board and internal PLL0 to multiply the input frequency and achieve its 80 MHz maximum operating frequency. The second PLL1 is used to achieve suitable frequency for internal Motor control, SWG, and communication modules. The MPC5643L can also use internal 16 MHz RC oscillator as a clock source. In this mode FlexRAY protocol clock does not support IRCOSC as a clock source.

Figure 3-2. MCPC5643L clock block diagram

3.3 UNI3 interfaces and external fault managementThe motor power stages are controlled by microcontroller boards through two UNI3 and MC33937 connectors. The connector pin description was mentioned in Chapter 2.2, “UNI3 Interface J300, and J304". Analog or digital signals from the power stages M1 and M2 can be processed by the hardware to maintain fault management. The MPC5643L has eight fault inputs, the first four are routed into PWM module 0, the second four into PWM module 1. Switch off PWM output signals for each module.




The FAULT0, resp. FAULT4 signal can be set up as under- or over-voltage. Whether the output signals from Phase A or DCBUS over-current comparator can be asserted to the input FAULT1, resp. FAULT5, depends on jumper position J301, and J302. The FAULT2 and FAULT3, resp. FAULT6 and FAULT7 MCU inputs can be used as over-current signals from phase B and C. The phase OC level is setup by trimmer R300 resp. R301. See Figure 3-3.

Figure 3-3. FAULT management




3.4 Encoder/Hall sensor interfaceThe motor control application can read position or speed from up to two independent encoders or HALL sensors. The on-board interfaces provide the 5 V power supply voltage to supply the sensors. The Hall interface inputs are designed to support an open collector as well as push-pull Hall sensor outputs (see Figure 3-4). A single pole RC low pass filter is present to reduce a signal noise.

Table 3-1. Header J301, J302 — FAULT1, FAULT5 signal assignment

Jumper position Description

1–2 Phase A over-current

2–3 DC-bus over-current




Figure 3-4. Encoder/Hall sensor interface circuit

3.5 Resolver and SinCos sensor interfaceThe resolver or SinCos interfaces on the board observe actual motor rotor position. The board is populated with two independent HW interfaces that allow the independent measurement of two motor rotor positions and speed. Figure 3-5. shows hardware circuitry for one sensor, the second hardware is similar. The




resolver sensor can be connected through J200 and J207 connector. The jumpers J202 and J205. J209 and J212 provide selection of the positive input signal for differential amplifiers. In case a resolver sensor is used, pins two and three must be shortened. The excitation signal output level (terminals RESx_E_R1 and RESx_E_R2) is setup by trimmer R217 and R249. The resolver excitation signal for the first resolver circuitry can be selected by J206. The source signals are outputs from the SWG module and eTimer0, channel5. The resolver excitation signal for the second resolver circuitry is routed to the eTimer1, channel4 output. It is also connected to the M2_HOME signal from encoder2.

For a detailed J200 connector signal description, see Table 2-5 and Table 2-6.




Figure 3-5. Resolver 1 interface schematic




The resolver is an electro-mechanical transformer whose analog output voltages are a function of the shaft angle. It is therefore, an absolute position transducer, providing true angular information at any time. The reference winding (R1 and R2 terminals) is supplied by an alternating signal Vref. Output is taken from the two stator windings, shown in Figure 3-6. The two stator windings fixed at right (90°) angles to each other on the stator produce sine and co-sine feedback voltages Vsin, and Vcos. However, their amplitudes are modulated by sine and cosine as the shaft rotates (see Figure 3-7). That is, the voltages induced into the stator winding will be Vsin=K*sin(?)*sin(t) and Vsin=K*cos(?)*sin(t), where K is the transformation ratio, ? is the shaft rotation from the reference zero-degree position, and f carrier frequency.

Figure 3-6. Resolver basics

These outputs are modified by differential amplifiers and fed to an analog-to-digital converter. The rotor angle ? can be extracted from these voltages using a digital approach. For a detailed description, see the application note titled 56F80x Resolver Driver and Hardware Interface (document number AN1942).




Figure 3-7. Resolver excitation signals

3.6 Analog signal sensingThe MPC5643L can sample up to 2 16 analog signals. External 2 9 channels are connected through RC filters directly to ADC converters zero and one. The next four channels are common and can be internally switched between both converters. They can be used to sample phase motor currents. The ADC0 channel 15 is dedicated to temperature sensor 0, ADC1 channel 15 for temperature sensor 1, and ADC0/1 channel 10 for measure Vreg 1.2 V.

The time constant of the RC filter must be set according to system requirements. The default time constant was set to approximately 1.2 s on the inputs zero to ten, and inputs that sample motor currents are set to approximately 50 ns.

Figure 3-8. Analog sensing circuit

3.7 Power supplies and voltage referenceThe MPC5643L Dual Motor Controller Board can be supplied from three main power supply inputs. The first one uses a 2.1 mm coaxial power jack and the others use UNI-3 connectors. The more suitable one depends on the application type. The controller board provides a +5 V DC-voltage regulation for the resolver, encoder, FlexRAY driver, a +3.3 V DC-voltage regulation for MCU and supporting logic, and




provides a reference voltage for the ADC module. Power applied to the MPC5643L Dual Motor Controller Board is indicated by a power-on LED D112. +3.3 V for the MCU and peripherals are signalized by LEDs D113 and D114. The block diagram is shown in Figure 3-9.

Figure 3-9. Power supply

3.8 UNI-3 PFC-PWM signal (power factor correction)The PFC-PWM signal is used to additionally control the power stage circuit like PFC or power DC-DC converter. These signals are connected to the MPC5643L controller pins GPIO G[7], and H[15].

3.9 UNI-3 brake signalsThe brake signals are used to control the DC-bus resistor switches on each connected power stage. It is accessible via the GPIO G[6] for motor M1, and H[14] for motor M2.

3.10 CAN BusThe FlexCAN module is a communication controller that implements the CAN protocol according to the CAN 2.0B protocol specification, which supports both standard and extended message frames. A number of Message Buffers (32) are also supported. For a detailed description refer to the reference manual titled Qorivva MPC5643L Microcontroller Reference Manual (document number MPC5643LRM). Freescale system basis chip MC33905S with one CAN and one LIN interface is used as the hardware interface for flexCAN module 0. Jumpers JP100 and JP101 define the middle or end node. The flexCAN module 1 does not have a physical interface populated on the board, but the signals are accessible via header J2.

3.11 FlexRAY interfaceThe FlexRAY module implements the FlexRay Communications System Protocol Specification, Version 2.1 Rev A. The hardware interface consists of two TJA1080 ICs, see Figure 6-9.



Electrical Characteristics

Chapter 4 Electrical CharacteristicsThe electrical characteristics in Table 4-1 apply to an operation at 25 °C.

Table 4-1. Electrical characteristics

1—12 V power supply, MCU without software

Characteristic Symbol Min Typ Max Units

Power supply Voltage VDC 8 12 18 V

Current consumption(1) ICC TBD mA

Minimum Logic one Input Voltage VIH mA

Maximum Logic zero Input Voltage VIL mA

Input Logic Resistance RIN – 4.7 – k

Analog Input Range VIN 0 – 3.3 V



Electrical Characteristics



Board Setup Guide

Chapter 5 Board Setup GuideThe board uses either the UNI-3 interface or the on-board J1 connector with a power supply voltage from 8 to 18 V. While using the board as a standalone EVB, connect the power supply to J1. In the case of board operation with the power stage it is recommended to use on the board the UNI-3 interface.

The MPC5643L controller board (blue board) is designed for operation with the FSL MC33937A based 3-Phase low voltage power stage (green board), see Figure 5-1. The complete 3-phase BLDC/PMSM Sensor/Sensorless Development Kit can be ordered at http://www.freescale.com.

Figure 5-1. 3-Phase dual PMSM development kit





Board Setup Guide



MPC5643L Dual Motor Controller Board Schematics

Chapter 6 MPC5643L Dual Motor Controller Board Schematics




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doc

umen

t con

tain

s in

form

atio

n pr

oprie

tary

to F

rees

cale

Sem

icon

duct

or a

nd s

hall

not b

e us

ed fo

ren

gine

erin

g de

sign

, pro

cure

men

t or m

anuf

actu

re in

who

le o

r in

part

with

out t

he e

xpre

ss w

ritte

n pe

rmis

sion

of F

rees

cale

Sem

icon

duct

or.

ICA

P C

lass

ifica

tion:

FCP

:FI

UO

:P

UB

I:

SC

H-2

7473

PD

F: S

PF-

2747

3B

1

MPC

5643

L D

ual M

otor

Con

trol

ler B

oard

A3

Tues

day,

Jul

y 17

, 201

2

Hier

arch

ical

vie

w

P.K

onvi

cny

<App

rove

r>

P.K

onvi

cny

214

X__

___

__D

raw

ing

Title

:

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

Pag

e Ti

tle:

Des

igne

r:

Dra

wn

by:

App

rove

d:

Free

scal

e Se

mic

ondu

ctor

RCS

C1.

maj

e 10

0976

5 61

Roz

nov

p. R

. Cze

ch re

publ

ic, E

urop

e

This

doc

umen

t con

tain

s in

form

atio

n pr

oprie

tary

to F

rees

cale

Sem

icon

duct

or a

nd s

hall

not b

e us

ed fo

ren

gine

erin

g de

sign

, pro

cure

men

t or m

anuf

actu

re in

who

le o

r in

part

with

out t

he e

xpre

ss w

ritte

n pe

rmis

sion

of F

rees

cale

Sem

icon

duct

or.

ICA

P C

lass

ifica

tion:

FCP

:FI

UO

:P

UB

I:

SC

H-2

7473

PD

F: S

PF-

2747

3B

1

MPC

5643

L D

ual M

otor

Con

trol

ler B

oard

A3

Tues

day,

Jul

y 17

, 201

2

Hier

arch

ical

vie

w

P.K

onvi

cny

<App

rove

r>

P.K

onvi

cny

214

X__

___

__

HB

1

1 - M

CU

FR_A

_TX

FR_B

_TX

FR_A

_RX

FR_B

_RX

/FR

_B_T

X_E

N

/FR

_A_T

X_E

N

AN

A_0

AN

A_1

AN

A_2

AN

A_3

AN

A_4

AN

A_5

AN

A_6

AN

A_7

AN

B_0

AN

B_1

AN

B_2

AN

B_3

AN

B_4

AN

B_5

AN

B_6

AN

B_7

FAU

LTB

0FA

ULT

B1

FAU

LTB

2FA

ULT

B3

AN

A_8

AN

_11

AN

_12

AN

_13

AN

_14

AN

B_8

+3.3Vdc

VREF

GND

GNDA

+3.3VA2

+12V

MCU_3.3V

DS

PI1

_SO

UT

DS

PI0

_SO

UT

PW

M1_

B0

PW

M1_

A0

PW

M1_

B1

PW

M0_

B0

DS

PI0

_SC

K

DS

PI1

_/C

S0

DS

PI1

_SC

K

SW

G_O

UT

PW

M1_

B2

PW

M1_

A1

PW

M0_

B1

PW

M0_

A0

PW

M1_

B3

PW

M1_

A2

PW

M0_

B2

PW

M1_

X0

PW

M1_

X1

PW

M0_

X0

E13

EN

C2_

HO

ME

PW

M1_

X2

PW

M0_

X1

EN

C1_

HO

ME

PW

M1_

X3

PW

M0_

X2

DS

PI0

_SIN

DS

PI1

_SIN

PW

M0_

X3

LIN

1_R

XD

EN

C1_

IND

EX

CA

N1_

RX

D_P

HY

CA

N1_

TXD

_PH

Y

CA

N0_

RX

D_P

HY

CA

N0_

TXD

_PH

Y

DS

PI0

_/C

S0

EN

C1_

PH

A

PW

M0_

A1

DS

PI1

_/C

S2

DS

PI0

_/C

S1

EN

C1_

PH

B

EN

C2_

IND

EX

EN

C2_

PH

A

PW

M0_

B3

PW

M1_

A3

PW

M0_

A2

LIN

1_TX

D

EN

C2_

PH

B

FAU

LTB

4

A10

FAU

LTB

5

A11

DS

PI0

_/C

S2

PW

M0_

A3

DS

PI0

_/C

S3

FAU

LTB

6

C10

F3

A12

FAU

LTB

7

A13

eTim

er1_

CH

5

/RS

T

A9

HB

25

- PO

WE

R S

UP

PLY

+3.3

VA

1

+3.3

VA

2

+5V

dc

+5V

A

Vre

f

GNDP

GNDA

UN

I3_1

5V

GNDUN

I3_5

V

+12V

LIN

_TX

3390

5_S

CLK

MC

U_3

.3V

3390

5_/C

S33

905_

/INT

MU

X_O

UT

3390

5_/R

ST

3390

5_M

OS

I33

905_

MIS

O

PE

R_3

.3V

LIN

_RX

CA

N0_

TXD

CA

N0_

RX

D

HB

4

6 - R

esol

vers

+3.3

VA

PO

S_S

INP

OS

_CO

S

PH

AS

E_A

PH

AS

E_B

V_s

up

GNDA

Vre

f

GNDP

+5V

A

SIN

_RE

F

PW

M_R

EF

PO

S_C

OS

_1P

OS

_SIN

_1

PW

M_R

EF_

1

PH

AS

E_A

_1P

HA

SE

_B_1

HB

3

4 - 0

8_U

NI3

UN

I-3 +

5V

UN

I-3 +

15V

A

FAU

LTB

0FA

ULT

B1

FAU

LTB

2FA

ULT

B3

GN

DA

GN

D

+3.3

Vdc

+5V

dc

3393

7_S

IN33

937_

SO

UT

3393

7_S

CK

3393

7_/R

ST

3393

7_O

C33

937_

INT

M2_

PH

CIS

M1_

SE

RIA

L

M2_

CB

M2_

CT

M2_

BB

M1_

CB

M2_

BT

M2_

AB

M1_

CT

M1_

BB

M2_

AT

M1_

PFC

M1_

BT

M1_

AB

M1_

DC

BV

M2_

TEM

PM

2_D

CB

IM

1_TE

MP

M1_

DC

BI

M2_

PFC

M1_

PFC

_EN

M1_

AT

M2_

SE

RIA

LM

1_P

FC_Z

C

M1_

BR

AK

EM

2_B

RA

KE

M2_

BE

MFZ

CA

M2_

BE

MFZ

CB

M2_

PFC

_EN

FAU

LTB

4

M2_

BE

MFZ

CC

FAU

LTB

5

3393

7_C

S0

3393

7_C

S1

M2_

PFC

_ZC

FAU

LTB

6

M1_

BE

MFZ

CA

M1_

PH

AIS

M2_

PH

AIS

FAU

LTB

7

M1_

BE

MFZ

CB

M1_

PH

BIS

M2_

PH

BIS

M2_

DC

BV

M1_

BE

MFZ

CC

M1_

PH

CIS

3393

7_E

N1

3393

7_E

N2

HB

53-

EN

CO

DE

RS

+5V

dc

GN

D

M2_

BE

MFZ

CA

M2_

PH

_AM

2_P

H_B

M1_

PH

_AM

1_P

H_B

M2_

HO

ME

M1_

IND

EX

M2_

IND

EX

M1_

HO

ME

M2_

BE

MFZ

CB

M2_

BE

MFZ

CC

M1_

BE

MFZ

CA

M1_

BE

MFZ

CB

M1_

BE

MFZ

CC

HB

6

2- F

lexR

ay_D

RV

GN

D

V_s

up

+5V

dc

FR_A

_TX

FR_B

_TX

/FR

_A_T

X_E

N

/FR

_B_T

X_E

NFR

_B_R

X

FR_A

_RX




Figure 6-3. MPC5643L signals

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

NEX

US

IN

TER

FAC

E

JTA

G I

NTE

RFA

CE

CO

RE

SU

PP

LY C

IRC

UIT

BO

OT

SEL

ECTI

ONC

LOC

K C

IRC

UIT

+3.3

Vdc

DS

PI1

_SIN

MD

O5

DS

PI0

_/C

S0

eTim

er0_

CH

5

LIN

0_TX

D

AB

S2

FR_B

_RX

XTA

L

PW

M0_

B2

MD

O1

DS

PI1

_/C

S2

+12V

AD

C1_

AN

0

FAB

EX

TAL

PW

M1_

X2

PW

M1_

A2

PW

M1_

B2

PW

M1_

X3

PW

M1_

A1

PW

M1_

A3

PW

M1_

B1

PW

M1_

B3

A9

MC

K0

LIN

0_R

XD

UP

FAU

LTB

5

DS

PI0

_SC

K

MS

EO

1

AD

C1_

AN

1

TDO

eTim

er1_

CH

1

MD

O4

FR_B

_TX

BC

TRL

PW

M0_

X0

A10

PW

M0_

X3

AD

C0_

AN

0

/RE

SE

T

MS

EO

0

Vre

f

PW

M0_

A1

MC

U_3

.3V

EV

TI

TDI

AD

C1_

AN

2

FCC

U_F

0

EV

TO

A11

DS

PI0

_SO

UT

FAU

LTB

6

DO

WN

AD

C0_

AN

1

eTim

er1_

CH

2

TCK

PW

M1_

X0

/FR

_B_T

X_E

N

PW

M0_

A0

PW

M0_

A3

CLK

OU

T

TDO

A12

F3

AD

C0/

1_A

N11

TDI

FCC

U_F

1

MC

U_3

.3V

AD

C1_

AN

3

DS

PI0

_SIN

/FR

_A_T

X_E

N

FAU

LTB

7

ON

/OFF

DS

PI1

_/C

S0

DS

PI0

_/C

S3

PW

M1_

A0

PW

M0_

B0

A13

AD

C0/

1_A

N12

PW

M0_

B3

TMS

AD

C0_

AN

7

AD

C1_

AN

4

AD

C0_

AN

8

AD

C1_

AN

6

AD

C0_

AN

4

E13

AD

C0_

AN

6

eTim

er1_

CH

5

AD

C1_

AN

5

AD

C1_

AN

7

DS

PI0

_/C

S1

AD

C0_

AN

5

AD

C1_

AN

8

EV

TI

MD

O7

eTim

er1_

CH

3

AD

C0_

AN

2

PW

M0_

X2

C10

JCO

MP

BC

TRL

FR_A

_TX

AD

C0/

1_A

N13

DS

PI0

_/C

S2

PW

M1_

B0

PW

M0_

X1

JCO

MP

DS

PI1

_SC

K

CA

N0_

TXD

MD

O0

+3.3

VA

2

eTim

er0_

CH

0

MD

O6

eTim

er1_

CH

4

AD

C0_

AN

3

eTim

er0_

CH

4

PW

M0_

A2

FR_A

_RX

TMS

DS

PI1

_SO

UT

SW

G_A

NO

UT

PW

M0_

B1

PW

M1_

X1

MD

O3

eTim

er0_

CH

1

LIN

1_R

XD

AD

C0/

1_A

N14

AB

S0

FAU

LTB

0FA

ULT

B1

MD

O8

FAU

LTB

2FA

ULT

B3

VD

D_C

OR

E

TCK

MD

O2

FAU

LTB

4

CA

N0_

RX

D

CA

N1_

TXD

CA

N1_

RX

D

LIN

1_TX

D

AB

S2

FAB

AB

S0

/RE

SE

T

CLK

OU

TM

DO

8/R

ES

ET

EV

TITD

O

TCK

MD

O7

TMS

MD

O6

TDI

MD

O5

MD

O4

MD

O3

MD

O2

MD

O1

MD

O0

EV

TOM

CK

0

MS

EO

0M

SE

O1

JCO

MP

GN

DA

+12V

+3.3

Vdc

SW

G_O

UT

LIN

1_R

XD

LIN

1_TX

D

A10

/FR

_A_T

X_E

N

/FR

_B_T

X_E

N

C10

MC

U_3

.3V

A11

FR_A

_TX

FR_B

_TX

A12

FR_A

_RX

+3.3

VA

2

A13

FR_B

_RX

VR

EF

GN

D

PW

M1_

A1

PW

M1_

B1

PW

M1_

A2

PW

M1_

B2

PW

M1_

A3

PW

M1_

B3

PW

M1_

X3

PW

M1_

X1

PW

M1_

X2

PW

M1_

X0

PW

M1_

A0

PW

M1_

B0

FAU

LTB

2

PW

M0_

A1

PW

M0_

B1

FAU

LTB

3

PW

M0_

A2

PW

M0_

B2

FAU

LTB

6FA

ULT

B7

FAU

LTB

4FA

ULT

B5

PW

M0_

A3

PW

M0_

B3

PW

M0_

X3

PW

M0_

X1

PW

M0_

X2

PW

M0_

X0

FAU

LTB

0

PW

M0_

A0

PW

M0_

B0

FAU

LTB

1

E13

F3

DS

PI1

_SIN

DS

PI1

_/C

S2

DS

PI1

_SC

KD

SP

I1_S

OU

T

DS

PI1

_/C

S0

DS

PI0

_/C

S2

DS

PI0

_/C

S3

DS

PI0

_SIN

DS

PI0

_/C

S1

DS

PI0

_SC

KD

SP

I0_S

OU

T

DS

PI0

_/C

S0

/RS

T

eTim

er1_

CH

5

EN

C2_

PH

AE

NC

2_P

HB

EN

C2_

IND

EX

EN

C2_

HO

ME

EN

C1_

PH

AE

NC

1_P

HB

EN

C1_

IND

EX

EN

C1_

HO

ME

A9

GN

DG

ND

AG

ND

GN

DG

ND

GN

D

GN

DG

ND

MC

U_3

.3V

GN

D

GN

D

MC

U_3

.3V

MC

U_3

.3V

GN

D

UP

DO

WN

ON

/OFF

Vre

f

+12V

+3.3

VA

2

LIN

1_TX

D

+3.3

Vdc

MC

U_3

.3V

VD

D_L

V_P

LL

VD

D_C

OR

E

LIN

1_R

XD

LIN

0_R

XD

LIN

0_TX

DC

AN

0_R

XD

CA

N0_

TXD

CA

N1_

RX

DC

AN

1_TX

D

FCC

U_F

1FC

CU

_F0

AD

C0_

AN

2

AD

C0/

1_A

N12

AD

C0_

AN

8

AD

C1_

AN

5

AD

C0_

AN

3

AD

C0/

1_A

N13

AD

C1_

AN

0

AD

C1_

AN

6

AD

C0_

AN

4

AD

C0/

1_A

N14

AD

C1_

AN

1

AD

C1_

AN

7

AD

C0_

AN

5

AD

C1_

AN

2

AD

C0_

AN

0

AD

C1_

AN

8

AD

C0_

AN

6

AD

C1_

AN

3

AD

C0_

AN

1A

DC

0/1_

AN

11

AD

C0_

AN

7

AD

C1_

AN

4

RE

SE

T

eTim

er1_

CH

5

+12V

Dra

win

g Ti

tle:

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

Pag

e Ti

tle:

Des

igne

r:

Dra

wn

by:

App

rove

d:

Free

scal

e Se

mic

ondu

ctor

RCS

C1.

maj

e 10

0976

5 61

Roz

nov

p. R

. Cze

ch re

publ

ic, E

urop

e

This

doc

umen

t con

tain

s in

form

atio

n pr

oprie

tary

to F

rees

cale

Sem

icon

duct

or a

nd s

hall

not b

e us

ed fo

ren

gine

erin

g de

sign

, pro

cure

men

t or m

anuf

actu

re in

who

le o

r in

part

with

out t

he e

xpre

ss w

ritte

n pe

rmis

sion

of F

rees

cale

Sem

icon

duct

or.

ICA

P C

lass

ifica

tion:

FCP

:FI

UO

:P

UB

I:

SC

H-2

7473

PD

F: S

PF-

2747

3B

1

MPC

5643

L D

ual M

otor

Con

trol

ler B

oard

A3

Tues

day,

Jul

y 17

, 201

2

MCU

_Sig

nals

P.K

onvi

cny

<App

rove

r>

P.K

onvi

cny

314

X__

___

__D

raw

ing

Title

:

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

Pag

e Ti

tle:

Des

igne

r:

Dra

wn

by:

App

rove

d:

Free

scal

e Se

mic

ondu

ctor

RCS

C1.

maj

e 10

0976

5 61

Roz

nov

p. R

. Cze

ch re

publ

ic, E

urop

e

This

doc

umen

t con

tain

s in

form

atio

n pr

oprie

tary

to F

rees

cale

Sem

icon

duct

or a

nd s

hall

not b

e us

ed fo

ren

gine

erin

g de

sign

, pro

cure

men

t or m

anuf

actu

re in

who

le o

r in

part

with

out t

he e

xpre

ss w

ritte

n pe

rmis

sion

of F

rees

cale

Sem

icon

duct

or.

ICA

P C

lass

ifica

tion:

FCP

:FI

UO

:P

UB

I:

SC

H-2

7473

PD

F: S

PF-

2747

3B

1

MPC

5643

L D

ual M

otor

Con

trol

ler B

oard

A3

Tues

day,

Jul

y 17

, 201

2

MCU

_Sig

nals

P.K

onvi

cny

<App

rove

r>

P.K

onvi

cny

314

X__

___

__D

raw

ing

Title

:

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

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C1.

maj

e 10

0976

5 61

Roz

nov

p. R

. Cze

ch re

publ

ic, E

urop

e

This

doc

umen

t con

tain

s in

form

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n pr

oprie

tary

to F

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hall

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Figure 6-4. User interface

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maj

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Pow

er

P.K

onvi

cny

<App

rove

r>

P.K

onvi

cny

514

X__

___

__

PPC5643L

U7B

MP

C56

43L

VS

S_H

V_A

DR

0T7

VS

S_H

V_A

DR

1T9

VS

S_H

V_A

DV

0_A

DV

1U

10V

SS

_HV

_OS

C0

P1

VS

S_H

V_F

LA0

J16

VS

SD

15V

SS

_LV

_PLL

0_P

LL1

N4

VS

S_H

V_I

O_R

ING

0A

1V

SS

_HV

_IO

_RIN

G1

A2

VS

S_H

V_I

O_R

ING

2A

16V

SS

_HV

_IO

_RIN

G3

A17

VS

S_H

V_I

O_R

ING

4B

1V

SS

_HV

_IO

_RIN

G5

B2

VS

S_H

V_I

O_R

ING

6B

9V

SS

_HV

_IO

_RIN

G7

B17

VS

S_H

V_I

O_R

ING

8C

3V

SS

_HV

_IO

_RIN

G9

C15

VS

S_H

V_I

O_R

ING

10D

9V

SS

_HV

_IO

_RIN

G11

H2

VS

S_H

V_I

O_R

ING

12N

2V

SS

_HV

_IO

_RIN

G13

P9

VS

S_H

V_I

O_R

ING

14R

3V

SS

_HV

_IO

_RIN

G15

R15

VS

S_H

V_I

O_R

ING

16T1

VS

S_H

V_I

O_R

ING

17T1

7V

SS

_HV

_IO

_RIN

G18

U1

VS

S_H

V_I

O_R

ING

19U

2V

SS

_HV

_IO

_RIN

G20

U16

VS

S_H

V_I

O_R

ING

21U

17

NC_E14E14

NC_K3K3

NC_K14K14

NC_L14L14

NC_L4L4

NC_M4M4

NC_N14N14

NC_P8P8

NC_T3T3

NC_U3U3

NC_U12U12

NC_U13U13

NC_C2C2

NC_D10D10

NC_F14F14

VD

D_H

V_A

DR

0R

7V

DD

_HV

_AD

R1

R9

VD

D_H

V_A

DV

0_A

DV

1U

9V

DD

_HV

_RE

G0_

1J3

VD

D_H

V_R

EG

0_2

J4V

DD

_HV

_OS

C0

M1

VD

D_H

V_P

MU

U14

VD

D_H

V_R

EG

1_1

H15

VD

D_H

V_R

EG

1_2

J15

VD

D_H

V_F

LA0

H16

VD

D_H

V_R

EG

2_1

C7

VD

D_H

V_R

EG

2_2

C8

VD

D_L

V_P

LL0_

PLL

1P

4

VD

D_H

V_I

O_R

ING

0A

3V

DD

_HV

_IO

_RIN

G1

A9

VD

D_H

V_I

O_R

ING

2B

16V

DD

_HV

_IO

_RIN

G3

C1

VD

D_H

V_I

O_R

ING

4D

8V

DD

_HV

_IO

_RIN

G5

D14

VD

D_H

V_I

O_R

ING

6G

2V

DD

_HV

_IO

_RIN

G7

M2

VD

D_H

V_I

O_R

ING

8P

10V

DD

_HV

_IO

_RIN

G9

T2V

DD

_HV

_IO

_RIN

G10

P14

VD

D_H

V_I

O_R

ING

11T1

6V

DD

_LV

_CO

RE

_RIN

G0

D6

VD

D_L

V_C

OR

E_R

ING

1F6

VD

D_L

V_C

OR

E_R

ING

2F7

VD

D_L

V_C

OR

E_R

ING

3F8

VD

D_L

V_C

OR

E_R

ING

4F9

VD

D_L

V_C

OR

E_R

ING

5F1

0V

DD

_LV

_CO

RE

_RIN

G6

F11

VD

D_L

V_C

OR

E_R

ING

7F1

2V

DD

_LV

_CO

RE

_RIN

G8

G6

VD

D_L

V_C

OR

E_R

ING

9G

12V

DD

_LV

_CO

RE

_RIN

G10

H12

VD

D_L

V_C

OR

E_R

ING

11H

6V

DD

_LV

_CO

RE

_RIN

G12

J6V

DD

_LV

_CO

RE

_RIN

G13

J12

VD

D_L

V_C

OR

E_R

ING

14J1

4V

DD

_LV

_CO

RE

_RIN

G15

K6

VD

D_L

V_C

OR

E_R

ING

16K

12V

DD

_LV

_CO

RE

_RIN

G17

L6V

DD

_LV

_CO

RE

_RIN

G18

L12

VD

D_L

V_C

OR

E_R

ING

19M

6V

DD

_LV

_CO

RE

_RIN

G20

M7

VD

D_L

V_C

OR

E_R

ING

21M

8V

DD

_LV

_CO

RE

_RIN

G22

M9

VD

D_L

V_C

OR

E_R

ING

23M

10V

DD

_LV

_CO

RE

_RIN

G24

M11

VD

D_L

V_C

OR

E_R

ING

25M

12V

DD

_LV

_CO

RE

_RIN

G26

P5

VD

D_L

V_C

OR

E_R

ING

27P

12

VS

S_L

V_C

OR

E_R

ING

0D

5V

SS

_LV

_CO

RE

_RIN

G1

G7

VS

S_L

V_C

OR

E_R

ING

2G

8V

SS

_LV

_CO

RE

_RIN

G3

G9

VS

S_L

V_C

OR

E_R

ING

4G

10V

SS

_LV

_CO

RE

_RIN

G5

G11

VS

S_L

V_C

OR

E_R

ING

6H

7V

SS

_LV

_CO

RE

_RIN

G7

H8

VS

S_L

V_C

OR

E_R

ING

8H

9V

SS

_LV

_CO

RE

_RIN

G9

H10

VS

S_L

V_C

OR

E_R

ING

10H

11V

SS

_LV

_CO

RE

_RIN

G11

H14

VS

S_L

V_C

OR

E_R

ING

12K

7V

SS

_LV

_CO

RE

_RIN

G13

K8

VS

S_L

V_C

OR

E_R

ING

14K

9V

SS

_LV

_CO

RE

_RIN

G15

K10

VS

S_L

V_C

OR

E_R

ING

16K

11V

SS

_LV

_CO

RE

_RIN

G17

J7V

SS

_LV

_CO

RE

_RIN

G18

J8V

SS

_LV

_CO

RE

_RIN

G19

J9V

SS

_LV

_CO

RE

_RIN

G20

J10

VS

S_L

V_C

OR

E_R

ING

21J1

1V

SS

_LV

_CO

RE

_RIN

G22

L10

VS

S_L

V_C

OR

E_R

ING

23L1

1V

SS

_LV

_CO

RE

_RIN

G24

L7V

SS

_LV

_CO

RE

_RIN

G25

L8V

SS

_LV

_CO

RE

_RIN

G26

L9V

SS

_LV

_CO

RE

_RIN

G27

P6

VS

S_L

V_C

OR

E_R

ING

28P

13




Figure 6-6. LEDs

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

74HC

FAU

LTB

2

PW

M0_

A1

PW

M0_

B1

FAU

LTB

3

PW

M0_

A2

PW

M0_

B2

FAU

LTB

6

PW

M1_

A1

PW

M1_

B1

FAU

LTB

7

PW

M1_

A2

PW

M1_

B2

FAU

LTB

4

PW

M1_

A0

PW

M1_

B0

FAU

LTB

5FA

ULT

B0

PW

M0_

A0

PW

M0_

B0

FAU

LTB

1

PW

M0_

A3

PW

M0_

B3

A12

A13

+3.3

Vdc

+3.3

Vdc

+3.3

Vdc

+3.3

Vdc

+3.3

Vdc

+3.3

Vdc

+3.3

Vdc

+3.3

Vdc

+3.3

Vdc

+3.3

Vdc

+3.3

Vdc

+3.3

Vdc

+3.3

Vdc

+3.3

Vdc

+3.3

Vdc

+3.3

Vdc

+3.3

Vdc

GN

D

GN

D

GN

D

+3.3

Vdc

+3.3

Vdc

+3.3

Vdc

GN

D

+3.3

Vdc

+3.3

Vdc

+3.3

Vdc

+3.3

Vdc

+3.3

Vdc

GN

D

+3.3

Vdc

+3.3

Vdc

+3.3

Vdc

+3.3

Vdc

+3.3

Vdc

Dra

win

g Ti

tle:

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

Pag

e Ti

tle:

Des

igne

r:

Dra

wn

by:

App

rove

d:

Free

scal

e Se

mic

ondu

ctor

RCS

C1.

maj

e 10

0976

5 61

Roz

nov

p. R

. Cze

ch re

publ

ic, E

urop

e

This

doc

umen

t con

tain

s in

form

atio

n pr

oprie

tary

to F

rees

cale

Sem

icon

duct

or a

nd s

hall

not b

e us

ed fo

ren

gine

erin

g de

sign

, pro

cure

men

t or m

anuf

actu

re in

who

le o

r in

part

with

out t

he e

xpre

ss w

ritte

n pe

rmis

sion

of F

rees

cale

Sem

icon

duct

or.

ICA

P C

lass

ifica

tion:

FCP

:FI

UO

:P

UB

I:

SC

H-2

7473

PD

F: S

PF-

2747

3B

1

MPC

5643

L D

ual M

otor

Con

trol

ler B

oard

A3

Tues

day,

Jul

y 17

, 201

2

LEDs

P.K

onvi

cny

<App

rove

r>

P.K

onvi

cny

614

X__

___

__D

raw

ing

Title

:

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

Pag

e Ti

tle:

Des

igne

r:

Dra

wn

by:

App

rove

d:

Free

scal

e Se

mic

ondu

ctor

RCS

C1.

maj

e 10

0976

5 61

Roz

nov

p. R

. Cze

ch re

publ

ic, E

urop

e

This

doc

umen

t con

tain

s in

form

atio

n pr

oprie

tary

to F

rees

cale

Sem

icon

duct

or a

nd s

hall

not b

e us

ed fo

ren

gine

erin

g de

sign

, pro

cure

men

t or m

anuf

actu

re in

who

le o

r in

part

with

out t

he e

xpre

ss w

ritte

n pe

rmis

sion

of F

rees

cale

Sem

icon

duct

or.

ICA

P C

lass

ifica

tion:

FCP

:FI

UO

:P

UB

I:

SC

H-2

7473

PD

F: S

PF-

2747

3B

1

MPC

5643

L D

ual M

otor

Con

trol

ler B

oard

A3

Tues

day,

Jul

y 17

, 201

2

LEDs

P.K

onvi

cny

<App

rove

r>

P.K

onvi

cny

614

X__

___

__D

raw

ing

Title

:

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

Pag

e Ti

tle:

Des

igne

r:

Dra

wn

by:

App

rove

d:

Free

scal

e Se

mic

ondu

ctor

RCS

C1.

maj

e 10

0976

5 61

Roz

nov

p. R

. Cze

ch re

publ

ic, E

urop

e

This

doc

umen

t con

tain

s in

form

atio

n pr

oprie

tary

to F

rees

cale

Sem

icon

duct

or a

nd s

hall

not b

e us

ed fo

ren

gine

erin

g de

sign

, pro

cure

men

t or m

anuf

actu

re in

who

le o

r in

part

with

out t

he e

xpre

ss w

ritte

n pe

rmis

sion

of F

rees

cale

Sem

icon

duct

or.

ICA

P C

lass

ifica

tion:

FCP

:FI

UO

:P

UB

I:

SC

H-2

7473

PD

F: S

PF-

2747

3B

1

MPC

5643

L D

ual M

otor

Con

trol

ler B

oard

A3

Tues

day,

Jul

y 17

, 201

2

LEDs

P.K

onvi

cny

<App

rove

r>

P.K

onvi

cny

614

X__

___

__

R27

270

D20

HS

MS

-C17

0AC

R32

270

D13

HS

MS

-C17

0AC

U3C

MC

74H

C04

AD

G

56

U1C

MC

74H

C04

AD

G

56

D1

HS

MG

-C17

0AC

U1E

MC

74H

C04

AD

G

1110

D2

HS

MG

-C17

0AC

U4C

MC

74H

C04

AD

G

56

U2C

MC

74H

C04

AD

G

56

R24

270

D18

HS

MS

-C17

0AC

D12

SM

L-LX

0805

YC

-TR

AC

D3

HS

MG

-C17

0AC

R35

270

R23

270

R38

270

R41

270

U2E

MC

74H

C04

AD

G

1110

R29

270

R45

270

U1D

MC

74H

C04

AD

G

98

C23

0.1

UF

R25

270

D8

HS

MG

-C17

0AC

R33

270

U3D

MC

74H

C04

AD

G

98

R44

270

U1B

MC

74H

C04

AD

G

34

U4F

MC

74H

C04

AD

G

1312

D10

SM

L-LX

0805

YC

-TR

AC

U4E

MC

74H

C04

AD

G

1110

U2B

MC

74H

C04

AD

G

34

U4D

MC

74H

C04

AD

G

98

D24

HS

MG

-C17

0AC

R46

270

R36

270

D7

HS

MG

-C17

0AC

R26

270

VC

C

GN

D

U4A

MC

74H

C04

AD

G

12

14 7

R43

270

D9

HS

MG

-C17

0AC

D5

SM

L-LX

0805

YC

-TR

AC

D17

HS

MS

-C17

0AC

R34

270

D22

HS

MG

-C17

0AC

D16

SM

L-LX

0805

YC

-TR

AC

D19

HS

MG

-C17

0AC

U2D

MC

74H

C04

AD

G

98

U3B

MC

74H

C04

AD

G

34

D23

SM

L-LX

0805

YC

-TR

AC

R40

270

U1F

MC

74H

C04

AD

G

1312

R28

270

VC

C

GN

D

U2A

MC

74H

C04

AD

G

12

14 7

R31

270

D4

SM

L-LX

0805

YC

-TR

AC

R39

270

C24

0.1

UF

VC

C

GN

DU3A

MC

74H

C04

AD

G

12

14 7

R42

270

VC

C

GN

D

U1A

MC

74H

C04

AD

G

12

14 7

D11

SM

L-LX

0805

YC

-TR

AC

D14

HS

MS

-C17

0AC

U3E

MC

74H

C04

AD

G

1110

R37

270

D21

HS

MG

-C17

0AC

D15

HS

MS

-C17

0AC

U2F

MC

74H

C04

AD

G

1312

R30

270

U4B

MC

74H

C04

AD

G

34

U3F

MC

74H

C04

AD

G

1312

D6

SM

L-LX

0805

YC

-TR

AC

C25

0.1

UF




Figure 6-7. Headers

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

Pla

ce a

ll he

ader

s &

jum

pers

into

100

mil

rast

er

TOP

BO

TTO

M

TOP

BO

TTO

M

AN

ALO

G IN

PUTs

CA

N0_

TXD

_PH

YC

AN

0_R

XD

_PH

Y

PW

M0_

X2

PW

M0_

X0

PW

M0_

X1

PW

M0_

A0

PW

M0_

B0

PW

M0_

A1

PW

M0_

A2

PW

M0_

B1

PW

M0_

B2

FAU

LTB

0FA

ULT

B2

FAU

LTB

1FA

ULT

B3

EN

C1_

PH

A

FAU

LTB

5FA

ULT

B7

PW

M1_

A0

PW

M1_

B0

PW

M1_

A1

PW

M1_

A2

PW

M1_

B1

PW

M1_

B2

PW

M1_

X2

PW

M1_

X0

PW

M1_

X1

FAU

LTB

4FA

ULT

B6

PW

M1_

A3

PW

M1_

B3

PW

M0_

A3

PW

M0_

B3

PW

M0_

X3

PW

M1_

X3

A12

A13

EN

C2_

PH

AE

NC

2_P

HB

EN

C2_

IND

EX

EN

C2_

HO

ME

EN

C1_

PH

BE

NC

1_IN

DE

XE

NC

1_H

OM

E

CA

N1_

TXD

_PH

YC

AN

1_R

XD

_PH

Y

SW

G_O

UT

F3A

10

C10

A11

E13

DS

PI1

_SIN

DS

PI1

_/C

S2

DS

PI1

_SC

KD

SP

I1_S

OU

TD

SP

I1_/

CS

0

GN

DA

GN

DG

ND

GN

D

GN

D

GN

D

+3.3

Vdc

GN

D

+3.3

Vdc

GN

DA

+3.3

Vdc

MC

U_3

.3V

GN

D

GN

DA

GN

D

CA

N0_

TXD

CA

N0_

RX

D

LIN

1_TX

DLI

N1_

RX

D

+3.3

VA

2

+3.3

VA

2

+3.3

Vdc

MC

U_3

.3V

AD

C0_

AN

0A

DC

0_A

N1

AD

C0_

AN

2A

DC

0_A

N3

AD

C0_

AN

4A

DC

0_A

N5

AD

C0_

AN

6A

DC

0_A

N7

AD

C0_

AN

8

+3.3

VA

2

AD

C1_

AN

0A

DC

1_A

N1

AD

C1_

AN

2A

DC

1_A

N3

AD

C1_

AN

4A

DC

1_A

N5

AD

C1_

AN

6A

DC

1_A

N7

AD

C1_

AN

8

AD

C0/

1_A

N11

AD

C0/

1_A

N12

AD

C0/

1_A

N13

AD

C0/

1_A

N14

CA

N1_

TXD

CA

N1_

RX

D

LIN

0_R

XD

LIN

0_TX

D

FCC

U_F

0FC

CU

_F1

eTim

er1_

CH

5

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tle:

Siz

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igne

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App

rove

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RCS

C1.

maj

e 10

0976

5 61

Roz

nov

p. R

. Cze

ch re

publ

ic, E

urop

e

This

doc

umen

t con

tain

s in

form

atio

n pr

oprie

tary

to F

rees

cale

Sem

icon

duct

or a

nd s

hall

not b

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gine

erin

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sign

, pro

cure

men

t or m

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re in

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part

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cale

Sem

icon

duct

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ICA

P C

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UB

I:

SC

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PF-

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Head

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P.K

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714

X__

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ev

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e:S

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of

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rove

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ondu

ctor

RCS

C1.

maj

e 10

0976

5 61

Roz

nov

p. R

. Cze

ch re

publ

ic, E

urop

e

This

doc

umen

t con

tain

s in

form

atio

n pr

oprie

tary

to F

rees

cale

Sem

icon

duct

or a

nd s

hall

not b

e us

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gine

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sign

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cure

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icon

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:P

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I:

SC

H-2

7473

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PF-

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L D

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2

Head

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P.K

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714

X__

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C1.

maj

e 10

0976

5 61

Roz

nov

p. R

. Cze

ch re

publ

ic, E

urop

e

This

doc

umen

t con

tain

s in

form

atio

n pr

oprie

tary

to F

rees

cale

Sem

icon

duct

or a

nd s

hall

not b

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gine

erin

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sign

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cure

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part

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icon

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ifica

tion:

FCP

:FI

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:P

UB

I:

SC

H-2

7473

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F: S

PF-

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1

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L D

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2

Head

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P.K

onvi

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rove

r>

P.K

onvi

cny

714

X__

___

__

J9

HD

R_2

X4

12

34 6

5 78

J6

HD

R_2

X6

12

34 6

5 78

910

1112

J4

HD

R_2

X71

23

45

67

89

1011

1213

14

J5

HD

R 2

X3

12

34 6

5

J2

HD

R_2

X4

12

34 6

5 78

J3

HD

R_2

X6

12

34 6

5 78

910

1112

J11

HD

R 2

X31

23

4 65

J13

HD

R 2

X31

23

4 65

J12

HD

R_2

X41

23

4 65 7

8

J1

HD

R_2

X71

23

45

67

89

1011

1213

14

J7

HD

R_2

X4

12

34 6

5 78

J8

HD

R 2

X3

12

34 6

5




Figure 6-8. Analog input filters

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

Pla

ce fi

lters

as

clos

e as

pos

sibl

e to

the

MC

U c

hip

AN

A_0

AN

A_1

AN

A_2

AN

A_3

AN

A_4

AN

A_5

AN

A_6

AN

A_7

AN

B_0

AN

B_1

AN

B_2

AN

B_3

AN

B_4

AN

B_5

AN

B_6

AN

B_7

AN

B_8

AN

A_8

AN

_12

AN

_11

AN

_14

AN

_13

GN

DA

GN

DA

GN

DA

GN

DA

GN

DA

GN

DA

GN

DA

GN

DA

GN

DA

GN

DA

GN

DA

GN

DA

GN

DA

GN

DA

GN

DA

GN

DA

GN

DA

GN

DA

GN

DA

GN

DA

GN

DA

GN

DA

AD

C0_

AN

0

AD

C0_

AN

1

AD

C0_

AN

2

AD

C0_

AN

3

AD

C0_

AN

4

AD

C0_

AN

5

AD

C0_

AN

6

AD

C0_

AN

7

AD

C0_

AN

8

AD

C1_

AN

0

AD

C1_

AN

1

AD

C1_

AN

2

AD

C1_

AN

3

AD

C1_

AN

4

AD

C1_

AN

5

AD

C1_

AN

6

AD

C1_

AN

7

AD

C1_

AN

8

AD

C0/

1_A

N11

AD

C0/

1_A

N12

AD

C0/

1_A

N13

AD

C0/

1_A

N14

Dra

win

g Ti

tle:

Siz

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ent N

umbe

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ev

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heet

of

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e Ti

tle:

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igne

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rove

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Free

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mic

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ctor

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C1.

maj

e 10

0976

5 61

Roz

nov

p. R

. Cze

ch re

publ

ic, E

urop

e

This

doc

umen

t con

tain

s in

form

atio

n pr

oprie

tary

to F

rees

cale

Sem

icon

duct

or a

nd s

hall

not b

e us

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gine

erin

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sign

, pro

cure

men

t or m

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re in

who

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r in

part

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n pe

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cale

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icon

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ICA

P C

lass

ifica

tion:

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P.K

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814

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rove

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C1.

maj

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0976

5 61

Roz

nov

p. R

. Cze

ch re

publ

ic, E

urop

e

This

doc

umen

t con

tain

s in

form

atio

n pr

oprie

tary

to F

rees

cale

Sem

icon

duct

or a

nd s

hall

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sign

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7473

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814

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maj

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0976

5 61

Roz

nov

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. Cze

ch re

publ

ic, E

urop

e

This

doc

umen

t con

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form

atio

n pr

oprie

tary

to F

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cale

Sem

icon

duct

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nd s

hall

not b

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sign

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re in

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7473

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PF-

2747

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5643

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P.K

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P.K

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814

X__

___

__

R17

120

R22

120

C7

82P

F

C22

82P

F

C16

2200

PF

R15

120

C13

2200

PF

C9

82P

F

R4

120

C17

2200

PF

C11

82P

FC

1022

00P

F

R11

120

R9

120

R20

120

C19

2200

PF

C21

82P

F

R1

120

R10

120

C14

2200

PF

C2

2200

PF

R13

120

C6

82P

F

C18

2200

PF

C3

82P

F

R7

120

C20

2200

PF

R12

120

R8

120

R14

120

R6

120

R19

120

R18

120

R16

120

R2

120

C15

2200

PF

C4

2200

PF

C12

82P

F

R5

120

R3

120

R21

120

C8

82P

F

C1

2200

PF

C5

82P

F




Figure 6-9. FlexRAY interface

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

Flex

Ray

A C

IRC

UIT

Flex

Ray

B C

IRC

UIT

V_s

up

VS

UP

+5V

dc

+5V

dc

+5V

dcV

_sup

FR_B

_RX

FR_B

_TX

/FR

_B_T

X_E

N

/FR

_A_T

X_E

N

FR_A

_RX

FR_A

_TX

V_s

up

+5V

dc

GN

D

GN

DG

ND

GN

D

GN

D

GN

DG

ND

GN

D

GN

D

GN

D

Dra

win

g Ti

tle:

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

Pag

e Ti

tle:

Des

igne

r:

Dra

wn

by:

App

rove

d:

Free

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e Se

mic

ondu

ctor

RCS

C1.

maj

e 10

0976

5 61

Roz

nov

p. R

. Cze

ch re

publ

ic, E

urop

e

This

doc

umen

t con

tain

s in

form

atio

n pr

oprie

tary

to F

rees

cale

Sem

icon

duct

or a

nd s

hall

not b

e us

ed fo

ren

gine

erin

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sign

, pro

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re in

who

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part

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7473

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PF-

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Tues

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flexR

AY In

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RCS

C1.

maj

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0976

5 61

Roz

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. Cze

ch re

publ

ic, E

urop

e

This

doc

umen

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form

atio

n pr

oprie

tary

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cale

Sem

icon

duct

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hall

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sign

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who

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icon

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P C

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SC

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7473

PD

F: S

PF-

2747

3B

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5643

L D

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flexR

AY In

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C1.

maj

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0976

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Roz

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. Cze

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publ

ic, E

urop

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This

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umen

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atio

n pr

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cale

Sem

icon

duct

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914

X__

___

__

C60

50.

1 U

F

R60

0

3.3K

C60

9

47P

F

C60

00.

1 U

F

J601

5326

1-02

19

12L6

01

AC

M45

32-8

01-2

P-T

001

41 2

3

U60

1

TJA

1080

TS/N

TRX

D0

11

TRX

D1

10

TXD

5

TXE

N6

BG

E8

STB

N9

EN

3

WA

KE

15

INH

21

INH

12

BP

18

BM

17

RX

D7

ER

RN

13

RX

EN

12VIO

4

VCC19

VBUF20

VBAT14 GND

16

L600

AC

M45

32-8

01-2

P-T

001

41 2

3

C60

8

33P

F

R60

1

47

C60

6

47P

F

C60

3

33P

F

R60

5

47C

607

0.04

7UF

C60

4

47P

F

J600

5326

1-02

19

12

R60

3

47

C60

1

47P

F

R60

6

10R

607

47

U60

0

TJA

1080

TS/N

TRX

D0

11

TRX

D1

10

TXD

5

TXE

N6

BG

E8

STB

N9

EN

3

WA

KE

15

INH

21

INH

12

BP

18

BM

17

RX

D7

ER

RN

13

RX

EN

12

VIO4

VCC19

VBUF20

VBAT14 GND

16

C60

2

0.04

7UF

R60

4

3.3K

R60

2

10




Figure 6-10. Encoders

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

+5V

dc

+5V

dc +5V

dc

M1_

PH

_A

M1_

PH

_B

M1_

IND

EX

M1_

HO

ME

M1_

BE

MFZ

CA

M1_

BE

MFZ

CB

M1_

BE

MFZ

CC

+5V

dc

GN

D

M2_

PH

_A

M2_

PH

_B

M2_

IND

EX

M2_

HO

ME

M2_

BE

MFZ

CA

M2_

BE

MFZ

CB

M2_

BE

MFZ

CC

+5V

dc

+5V

dc

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

+5V

dc

+5V

dc

+5V

dc

+5V

dc

+5V

dc

+5V

dc

+5V

dc

GN

D

GN

D GN

D

GN

D

+5V

dc

Dra

win

g Ti

tle:

Siz

eD

ocum

ent N

umbe

rR

ev

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C1.

maj

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0976

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Roz

nov

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. Cze

ch re

publ

ic, E

urop

e

This

doc

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t con

tain

s in

form

atio

n pr

oprie

tary

to F

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cale

Sem

icon

duct

or a

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hall

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cure

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icon

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C1.

maj

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0976

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. Cze

ch re

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urop

e

This

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form

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n pr

oprie

tary

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cale

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duct

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maj

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0976

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. Cze

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Figure 6-11. Dual motor interfaces

5 5

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maj

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0976

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nov

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. Cze

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publ

ic, E

urop

e

This

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t con

tain

s in

form

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n pr

oprie

tary

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rees

cale

Sem

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maj

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0976

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. Cze

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3M_N

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3 21

8 4

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2 4 6 8 10

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1

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0

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K




Figure 6-12. Power supply unit

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

LM39

3

Vref

dec

oupl

ing

MPC5

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3.24

6V

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dec

pl

TERMINATE

CA

NL

MC

U_3

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CA

NH

+3.3

VA

2

+3.3

VA

1

Vre

f

MC

U_3

.3V

+5V

dc

+5V

A

UN

I3_1

5V

UN

I3_5

V

GN

D

GN

DA

GN

DP

+12V

PE

R_3

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CA

N0_

TXD

CA

N0_

RX

D

LIN

_RX

LIN

_TX

3390

5_M

ISO

3390

5_M

OS

I33

905_

SC

LK

3390

5_/C

S

MU

X_O

UT

3390

5_/IN

T33

905_

/RS

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MC

U_3

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+12V

+5V

dcM

CU

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V

GN

DG

ND

GN

DG

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GN

D

GN

D

GN

D

GN

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GN

D

GN

D

GN

D

GN

DA

GN

DA

GN

DA

GN

DA

GN

DA

GN

DA

GN

DA

GN

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GN

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GN

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Figure 6-13. First resolver / SinCos interface

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

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S1_

E_S

2R

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1_E

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+3.3

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ref

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C1.

maj

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0976

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. Cze

ch re

publ

ic, E

urop

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n pr

oprie

tary

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icon

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2747

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L D

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Tues

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1314

X__

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:

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maj

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0976

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Roz

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. Cze

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publ

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n pr

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icon

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1314

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maj

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0976

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Roz

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. Cze

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1314

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2

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Document Number: MPC5643LDMCBUGRev.07/2012

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