MPA-LIGHT: Design and results of a 65 nm digital readout Macro Pixel ASIC prototype with on- chip...

MPA-LIGHT:Design and results of a 65 nm digital readout Macro Pixel ASIC prototype with on-chip particle recognition for the Phase II CMS outer tracker upgrade

A. Caratelli, D. Ceresa, R. Francisco, J. Kaplon, K. Kloukinas and A. Marchioro.

PH-ESE, CERN

TWEPP ‘15, Wednesday the 30th September, 2015

2

CMS was originally designed to run atLuminosity = 1 x 1034 cm-2 s-1

HL-LHC will improve up toLuminosity = 7.5 x 1034 cm-2 s-1

Phase II upgrades prepares CMS for HL-LHCTechnical Proposal for the Phase-II Upgrade of the CMS Detector: http://cds.cern.ch/record/2020886

http://cds.cern.ch/record/2020886



3

Main Outer Tracker requirements:

Up to pile up = 200

Contribution to Level 1 decision

L1 rate = 750 KHz

L1 Latency = 12.8 us

Reduce Material

Pixelated sensor

Larger bandwidth

Larger buffers

PT modules

New technologies

+ POWER

- POWER

4

PT module discriminates particlePass Fail

Stub

Particle are discriminated according to their transverse momentum

The module is composedby two sensor layers

5

Outer Tracker working principle:

Stub Finding

Outer Tracker Front-EndStubs only

Trigger-less readout: The electronics provides the stubs found at each event.

Triggered readout: The electronics stores the full frame at each event.

6

Stub Finding

TrackFind

Readout

Outer Tracker Front-End Tracker Back-EndStubs only


Dedicated talk: “Track Finding in CMS for the Level-1 Trigger at the HL-LHC”, M. Pesaresi

7

Stub Finding

TrackFind

CMS Level

1

CMS DAQ

Outer Tracker Front-End Tracker Back-End CMS

Level 1accept

Stubs only

L1 accept rate = 750 KHzLatency = 12.8 us

Full Frame


Readout

8

2 x PT modules:

140 mm70 mm

130 mm

130 mm

Z

Ф

2 Strip moduleStrips ~ 5 cm x 90 umr > 40 cmTID ~ 40 Mrad

Inner Tracker (RD53)Pixel Detector

Pixel + Strip modulePixels ~ 1.5mm x 100um Strip ~ 2.5cm x 100um 20 cm < r < 40 cmTID ~ 100 Mrad

9

Pixel + Strip module exploded view

ShortStripASIC x 8

Concentrator IC (CIC)Data aggregation

MacroPixelASIC x 16

Pixelated Layer

~ 32k pixel

LP-GBT and VTRx+Data transmission through the optical link

DC-DC convertersPS module is fully integrate entity

Strip Layer~ 2k strips

10

Pixel Strip module Front-End ASICs

MPA (1.2 cm x 2.5 cm)

FE

SRAMData

Formatting

I/OBinary Readou

t

Stub Finding Logic I/O

FE

Binary Readout

I/O

I/O

SHORT STRIP ASIC

FullFrame

Stubsonly

Strips

Pixels Level-1 accept

Power budget < 100 mW / cm2

(Total for both Front-End ASICs)

11

MPA-Light: the MPA prototype

Analog FE circuitry in 65 nm

Development of the sensor

Module assembly

MaPSA-Light

MPA-Light

12

MPA-Light ASIC floorplan16 * 100 μm

6.3

38

mm

2 m

m3

x 1

44

6 μ

m

z

X

Analog Pixel FE

Digital Pixel Logic

Analog Bias

Digital Periphery Logic

Bump Bonding Pads

I/O Driver

Row 1

Row 2

BB connectionto PCB/hybrid/detectorperiphery

WB connectionto PCB/Hybrid(staggered)

BB connection to detector pixels

BB connectionto detector GND

1.7 mm

13

MPA-Light functional description

FE

Hit Counter

Binary ReadoutSample Clock

(40 MHz)

3 modes of operation available

Stub finding

Digital-to-analog

Converters (DACs)

Calibration pulsesThresholdTrimming (per pixel)

Input

Test results are obtained without sensor i.e the input are from calibration capacitances

Memory

Components for testing

14

Analog Front-End schematicdesigned by J. Kaplon

Preamplifier Shaper Discriminator

Current consumption < 30 uA / channel

15

Calibration DAC measurement

Calibration pulse[fC]

8.7 fC

0 fC

0 255DAC code

Nominal step = 0.035 fCMeasured step = 0.034 fC

Offset = 0.044 fC

On purpose for Radiation hardness

16

Pixel Threshold spread

100 250

Nominal Step ~ 1.5 mV

Threshold DAC

HitCounter

1000

1000

0

0

2 Trimming DAC steps = 7.5 mV

Best trimming withthe 5-bits trimming DAC

Pulse Injected ~ 3 fC

HitCounter

17

Gain and Noise from S-curves (1)

0.35 fC … 1.05 fC

60 200

Nominal Step ~ 1.5 mVThreshold DAC

1000

0

Optimization region

Calibration pulse amplitudes

HitCounter

2.45 fC

18

Gain and Noise from S-curves (2)

Equivalent Noise Charge = (sim. value < 200 e-)

SNR >> 20

0.35 fC 2.25 fCCalibration pulse

amplitude

Threshold[mV]

Gain =

30 mV

190 mV

HitCounter

1000

120 140

Threshold DAC

0

80

sigma(cerf) = ENC

mean(cerf) = Threshold

Complementary error function fitting

(sim. value: 85 )

19

MPA-Light functional description

FE

Hit Counter

Binary ReadoutSample Clock

(40 MHz)

3 modes of operation available

Stub finding

Digital-to-analog

Converters (DACs)

Calibration pulsesThresholdTrimming (per pixel)

Input

Test results are obtained without sensor i.e the input are from calibration capacitances

Memory

Components for testing

20

Binary readout allows FE studies:

3.4 fC

2.2 fC

1.1 fC

Peakingtime

~ 24 ns

0 ns 140 ns 0 mV

310 mV Peak Gain~ 91 mV/fC

ShaperOutput[mV]

Injectiontime [ns]

Shaper outputfor different charge

1 fC 9 fC

ΔWalkTime[ns]

Max delay < 10 ns

Injected

Pulse [fC]

FE walk time (Threshold = 0.5 fC)

0 ns

Simulations value:• Time walk: < 14 ns from 0.5 fC to 12

fC• Peaking time = 24 ns

21

0 0 00 0 01 1 0

0 1 0

1 0 0

1 1 0

Z

X

FromBinary readout

MPA-Light digital logic testing

1. No Processing mode:

Used to test Binary readout

and Pixel Clustering

22

0 0 00 0 00 0 0

0 1 0

1 0 0

0 0 0

Z

X

FromBinary readout

+Pixel Clustering





23

0 0 00 0 00 0 0

0 1 0

1 0 0

0 0 0

Z

X

FromBinary readout

+Pixel Clustering

Centroid ListX = 3, Z = 1X = 2, Z = 3





2. Data Processing mode:

Used to test Encodingand Stub Finding Logic

24

0 0 00 0 00 0 0

0 1 0

1 0 0

0 0 0

Z

X

FromBinary readout

+Pixel Clustering


Stub ListX=3, Z=1, B=0X=2, Z=3, B=-1

or

0 1 00 0 0


Tested with patternfrom FPGA






Further details on the Stub finding logic: http://iopscience.iop.org/article/10.1088/1748-0221/9/11/C11012

http://iopscience.iop.org/article/10.1088/1748-0221/9/11/C11012

http://iopscience.iop.org/article/10.1088/1748-0221/9/11/C11012

25

0 0 00 0 00 0 0

0 1 0

1 0 0

0 0 0

Z

X

FromBinary readout

+Pixel Clustering

0 1 01 0 0


Stub ListX=3, Z=1, B=0X=2, Z=3, B=-1

or

0 1 00 0 0


Tested with patternfrom FPGA






3. Strip Emulator mode:

Tested with oscilloscope

26

Total Ionizing Dose (TID) with X-ray

PS module TID < 100 Mrad

0

Pre radvalue

-15 %

Total Ionizing dose [log TID]

150 Mrad

Annealing- 11 %

Threshold DAC variation with TID

0

100 Mrad

∆ ThresholdStep [%]

27

Conclusion and future plans

MPA-Light fully functional

MaPSA-Light ready

MaPSA-Light Testing

MPA & SSA design

Final size MPA and SSA

28

Thanks to all theCMS TRACKER PHASE II ELECTRONICS TEAM

Davide Ceresa, A. Caratelli, R. Francisco, J. Kaplon, K. Kloukinas and A.

Marchioro.PH-ESE-ME, CERN


29

Backup slidesDavide Ceresa, PH-ESE-ME, CERN


30

Reduced thanks to:Bend bits reductionTight Stub thresholdDifferent LP-GBT transmission mode

Good stub losses lower than 0.5% in all the

tracker at Pile Up 200

Stub transmission to tracker back-end is clearly critical for the first barrel layer

simulation and studies by S.Viret

Tracker Back-end data transmission

31

Tracker power budget is limited

Working temperature cooling: ~ -30C

Total Power Allocated per 16 MPAs and SSAs:

4WTotal Power Allocated per MPA + SSA: 250 mWRough Power Estimation:

Analog 70 mWL1 Memory 70 mWSSA 40 mW

Remaining 70 mW

I/OClock DistributionData TransportStub Finding LogicL1 Data LogicOutput Interface

32

Powering reference scheme

0.8 – 1V used to power digital logic which can work also at low voltage

slide and studies from G. Blanchot, F. Faccio and S.Michelis

33

Stub Finding logic efficiency results

0 20 40 60 80 100 120

0.4

0.5

0.6

0.7

0.8

0.9

1

Module # ( 1 - 125)

Eff

icie

ncy

(%)

MPA efficiency per moduleMPA efficiency per layerMPA efficiency per layer with Z communication

Module efficiency

Layer Efficiency

Layer efficiency with interconnection

Vertex Z-Z

34


XV

Module A

Module B

Vertex Z

Recovered

Without an interconnect technology (ex: TSV) between the two sides of the module, tracks crossing the middle will not be identified as stubs

35


VV

Module A

Vertex Z

VTilted layout solves the problem and decrease the number of modules, but complicates mechanics

36

Flipped MaPSA concept

• Only bump bonding in MPA design• No extra material between sensors• Better cooling of MPA

• Digital IO through sensor periphery• Temperature gradient across the sensor surface • Larger sensor can create problem in final production

STRIP SENSOR

MPA

SSA

MPA

SSA

EXTENDED PIXEL SENSOR

Cooling

BASELINE

STRIP SENSOR

PIXEL SENSOR

SSASSA

MPAMPA

Cooling

PROPOSAL

37

MPA-Light test system overview

PowerSupply

Ethernet Cable

MPA-Light

Test system controlled by Python routines Communicates

with IP bus

Interface BoardVoltage and Current

generator and monitorsdesigned for the CLICpix readout

by Szymon Kulis

FPGAHandle configuration,

readoutand control the interface board

Load boardExchangeable board for the

ASIC wire bonding and decoupling

developed by A. Caratelli

38

Analog Front-End simulation resultsdesigned by J. Kaplon

Other simulation results:Gain from S curves: 85 mV/fCTime walk : < 14 ns with threshold at 0.5 fC and signal from 0.75

to 12 fCNoise(Worst case): < 200 e- (SNR >> 20)

Spread90 mV pk-pk

Peaking time24 ns

Montecarlo simulations 100 runs for 2.5 fC

39

Binary readout allows FE studies

40 MHz Clock

Hit detector output

27 28

Discriminator Output

Shaper Output

Changing the calibration injection point and using the synchronous readout we can characterize the shaper of the

analog FE

Observing when the time stamp change we canextract the rising time of the shaper from zero

to the set threshold

Threshold

G. Blanchot, F. Faccio, S. Michelis - 2S and PS Powering Meeting

Service Board with Staged DCDC scheme

30/SEP/2014

Input power: low profile Molex Picoblade 2 poles connector (stands our current rating).

The filters will stay out of the shield area, must be on sides.

Wirebond based IO implemented so far.

The same low mass ECCA based coil is used for the 3 converters.

The new LV DCDCs still based on teh FEASTMP geometry. However we can consider a smaller package for this chip.

The 3 DCDC stages can be fitted in the available board space without excessive compromise.

Wir

ebonds

Input

Filters

16V caps

FEASTMP

LV caps

New DCDCs

Filters

Wir

ebonds

PS module

Forum 2014: Tilted Barrel for CMS Phase 2 Upgrade

11

129

1

2

34

5

8

1. Silicon strip sensor2. Silicon pixel sensor3. Macro-Pixel ASIC

(MPA)4. Al-CF sensor spacer5. CFRP base plate6. FE Hybrid7. Opto-Link Hybrid8. Power Hybrid9. Short-strip ASIC (SSA)10. Concentrator IC (CIC)11. Hybrid CF support12. Al-CF Hybrid spacer6

710

1111

11

12

Support and cooling via a large-area base plate

42

More realistic tilted geometry


Z = 0

• Short cylindrical section in the center• Constant tilt angle in several successive rings

o Helps avoiding clasheso Also, reduces support structure variants.

43

Material budget full tracker


S. Mersi at al., Performance of Tilted Inner Barrel, CMS Upgrade Workshop 1 April 2014

MPA-LIGHT: Design and results of a 65 nm digital readout Macro Pixel ASIC prototype with on- chip...

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