Mosfet Operation

MOSFET Operation

Day 11-12

ECE3030

Jeff Davis

2CMOS Transistors!

z

a

b

ab

GRD

VDD

z

(Complementary MOSFET)

p-channel MOSFET

acts like normally

closed switches

n-channel MOSFET

acts like normally

open switches

3nMOS (or nFET) Transistor!

(Switch level model)

n-channel MOSFET acts like normally open switches

gate

drain

source

gate voltage = LOW

drain source

gate voltage = HIGH

drain source

4pMOS (or pFET) Transistor!

(Switch level model)

p-channel MOSFET acts like normally closed switches

gate

drain

source

gate voltage = LOW

drainsource

gate voltage = HIGH

drain source

5A new device: MOSFET!

silicon wafer surface

Add lots phosphorus to

source and drain junctions.n+ n+

Source Drain

S(emiconductor)

Gate

M(etal)

O(xide)

glass (silicon dioxide)

p

channel

Band Diagram ACROSS the Channel

(in equilibrium)

x

x

Source

Gate

Drain

SourceDrain

channel

channel

EF

EC

Ev

Apply Voltage Across Drain and Source

Vdd

gate voltage = LOW

Vdd

Source

Gate

Drain

VDS

+

-

Band Diagram Long Channel Device

VDS = 0 Ec

Ev

VG

= 0

Unbiased JunctionUnbiased Bias Junction


VDS = 0 Ec

Ev

VG

= 0

VDS = small voltage



VDS = 0 Ec

Ev

VG

= 0

VDS = large voltage


VDS = small voltage

Leakage Currents

VDS = 0 Ec

Ev

VG

= 0

VDS = large voltage


VDS = small voltage

pn junction

leakage at reverse

bias drain junction

Drain-Induce Barrier Lowering

(DIBL) can occur on the source

junction as the drain junction

gets closer to the source!

-

DIBL with 45nm Devices

Lau,Drain current saturation at high drain voltage due to pinch off instead of velocity saturation in sub-100nm metal-

oxide-semiconductor transistors, Microelectronics Reliability, vol. 49 (2009)p. 1-7.

Band Diagrams for MOSFET

Simultaneous View of Both Directions

15

2 things we must understand!

n+ n+

M(etal)

O(xide)

S(emiconductor)

1. MOS Capacitor

2. MOSFET Channel Conduction

16

MOS Capacitor

Metal Gate

Insulator

Semiconductor

Substrate grounded!

Gate voltage VG

Example CalculationAssuming for the moment that the semiconductor acts like a good conductor,

what is the capacitance of a MOS capacitor that has a gate length of 180nm and a

transistor width that is 10x the length. Assume that the oxide thickness is 5nm.

M(etal)

O(xide)

S(emiconductor)

180nm Technology

VDD = 1.8V

L = 180nm

xox = 5nm

xox = 5nm

L = 180nm

Special Parameter, Cox

capacitance per unit area!

Cox=

KSiO

2o

xox

=

(3.9)(8.85e14[F /cm])

5e 7[cm]

Cox= 6.903e 7[F /cm

2]

Total Capacitance, Cgate

gate capacitance estimation

)7180)(7180(*10*)7903.6( cmecmeeZLCCoxgate

==

Cgate = 2.236e15[F ] = 2.236[ fF ]

Z = width

18

Work Function/Affinity

M = work function of the metal

S = work function of the semiconductor

Electron Affinity

Vacuum Level

19

MOS Materials Capacitor

20

MOS Capacitor

M = SAssumption of this discussion

21

MOS Capacitor Under Bias

22

VG > 0 with n-type substrate

VG

Accumulation of MAJORITY carriers!

Accumulation

n

These are referred to

as quasi-fermi levels!

n = e(Fn Ei )/kT

p = e(Ei Fp )/kT

M(etal)

O(xide)

e- e- e- e- e- e- e- e- e- e- e- e- e- e-

23

VG < 0 for n-type substrate

Depletion

Depletion region forms at surface of semiconductor!

24

VG < VT for n-type substrate

Inversion

Inversion layer of minority carriers (holes) is created

at surface!

Note that VT

is negative for this case!

n = e(Fn Ei )/kT

p = e(Ei Fp )/kT

pinterface

= ND

25

VG

26

Bias Types for P-type Material

ACCUMULATION DEPLETION INVERSION

27

electrostatic potential inside the

semiconductor at a depth x

( ) ( )[ ]

[ ]

[ ]FBULKiF

INTERFACEiBULKiS

iBULKi

EEq

withalong

potentialsurfaceEEq

xEEq

x

=

=

=

1

,

1

and

potential ticelectrosta 1

Surface Potential

P-type Example

Reference taken at the bulk!

(x) =

28

Condition for Threshold Voltage

s= 2

F

Surface potential that gives a concentration at the Si/SiO2 interface that is

the same as the concentration in the bulk.

29

Condition for Threshold Voltage

pBULK

= nie

EiBULK

EF( )

kT = NA

and nBULK

= nie

EFE

iBULK( )kT = N

D

F=

kT

qln

NA

ni

for a p-type semiconductor

kT

qln

ND

ni

for a n-type semiconductor

Example CalculationFind the Fermi potential in the body of the n-channel transistor assuming that

the channel doping concentration is 1015 cm-3. Assume the room temperature

intrinsic carrier concentration is given by 1.45e10 cm-3.

NA= 10

15cm

3

We know by definition that the channel is p doped because it is an nFET.

F=

kT

qln(

NA

ni

)

Solving for the Fermi potential gives the following:

F=

(1.38e 23 J/K)(300 K)

1.6e19Cln(

1015 cm-3

1.45e10cm-3)

F= 0.2885V

Example CalculationFor the previous example how much band bending do we need to have to

reach the threshold condition? More specifically what is the surface potential

at threshold?

We know the threshold condition is set when the surface potential is

twice the Fermi potential in the body of the transistor.

F= 0.2885V

s= 2

F

From the previous example we can know that the Fermi potential in the body is:

s= 2(0.2885) = 0.577 V

What is the GATE voltage that

gives this surface potential!

s= 2

F

33

Surface Potential and Gate Voltage

Relationship

VG=

oxide+

S

Potential drop across

oxide

Potential drop across the

bulk (which is surface

potential)

34

What about voltage drop across the

oxide?

M(etal)

O(xide)

Q=CV

Depletion region is formed first!

Z = transistor width

L = transistor length

VG=

oxide+

S oxide =Q

BZL

CoxZL

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

35

What is the relationship between surface

potential and gate voltage!

W =2K

Sos

qNA

oxide

=

QB

Cox

=

qNAW

Cox

VG=

s+

oxide

This is an expression for the

width of the depletion region!

Cox=

KSiO2

o

xox

Remember this is the surface

potential!

W

(Note that this assumes FREE inversion charge is much less than FIXED charge in channel.)

xox

M(etal)

O(xide)

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Q=CV

Example CalculationWhat is the width of the depletion region when the surface potential is at the

threshold condition? Assume the doping in the channel is 1015 cm-3 Assume that

the KSiO2

= 3.9, KS

= 11.9, and o

= 8.85e-14 F/cm.

W =2K

Sos

qNA

W =2*11.9 *8.85e14 * 0.577

1.6e19*1015

From the previous example we can know that the surface potential at threshold is:

s= 2(0.2885) = 0.577 V

The width of the depletion region at threshold is given by:

W = 8.715e 5 cm = 0.8715 microns

37

What is the relationship between

surface potential and gate voltage!

38

What is the relationship between surface

potential and gate voltage!

VG=

s+

2qNAK

sos

KSiO2

o

xo

VG

s=2

F

= VT= 2

F+

2qNAK

so2

F

KSiO2

o

xo

Threshold voltage!!!

2F=

2kT

qln

NA

ni

p-type

xox

xox

Example CalculationCalculate the threshold voltage for an nFET. Assume the doping in the channel is

1015 cm-3 Assume that the KSiO2

= 3.9, KS

= 11.9, and o

= 8.85e-14 F/cm. Assume

180nm technology specifications that have been outlined in previous graphs.

We have already calculated the Fermi potential for this doping to be:

The estimation of the threshold voltage for this case is:

F= 0.2885V

VT= 2

F+

2qNAK

so2

F

KSiO

2

o

xox

VT= 2(0.2885)+

2(1.6e19)(1015)(11.8)(8.85e14)2(0.2885)

(3.9)(8.85e14)5e 7[cm]

VT= 0.576+ 0.02011= 0.596[V ]

40

Threshold Voltage Expressions for nFET and pFET

( )

( )

areaunit per ecapacitanc oxide theis

where,

devices) channel-p(for 22

2

devices) channel-n(for 22

2

ox

ox

ox

F

S

D

ox

S

FT

F

S

A

ox

S

FT

xC

qN

CV

qN

CV

=

=

+=

oSSK = ox = KSiO

2

o

Qualitative Description MOSFET

Current

41

42

Electron flow from Source to Drain is controlled by the Gate voltage.

Control by the GATE voltage is achieved by modulating the CONDUCTIVITY of

the semiconductor region just below the gate.

MOS Transistor

Qualitative Description

n-channel MOSFET =

nFET or nMOS

transistor

Change

conductivity of

channel region

The source to drain path consists of two back to back diodes.

One of these diodes is always reverse biased regardless of the

drain voltage (I.E. VDS) polarity holes wont flow!

P-type

N-channel MOS Transistor


MOSFETsWONT WORK

IN ACCUMULATION!

VGS< 0

(accumulation)

44

There is a deficit of electrons and holes making the channel very

highly resistive. => No Drain current can flow.

High due

to Depletion



For ANY value of VDS:

0

45

An induced n- type region, an inversion layer, forms in the channel and

electrically connects the source and drain.

P-type

Inversion layer (n-type)



VDS= 0

VGS> V

T

46

The induced n- type region allows current to flow between the source and drain.

The induced channel acts like a simple resistor. Thus, this current, ID, depends

linearly on the DRAIN voltage VD. This mode of operation is called the linear or

triode* region.

P-type

Inversion layer (n-type)

Small positive VDS



VGS> V

T(continued):

47

Drain current verses drain voltage when in the linear or triode* region.



Linear region

Small positive VDS

VGS> V

T(continued):

48

VGS> V

T



P-type

Reduced electron concentration in the

Inversion layer near the drain

Leads to current

starting to roll off

for larger VDS

.

49

IDsat



Saturation region

Linear Region

VDsat = saturation voltage = VGS-VT

Channel Conductivity starts to pinch off near the drain!

This occurs when

VG

- VD

= VT

VDS = 0

VDS < VD,SAT

VDS =VD,SAT

VDS > VD,SAT

Channel changes as we increase VDS!

(Assume VG is greater than the threshold voltage)

51

MOS Transistor


Finally,

ID-V

DScurves for various V

GS:

VDsat

depends on VG

Quantitative Current Model!

52

53

Effective Surface Mobility

Surface scattering REDUCES Mobility!

n= 1350

n= 200

BULK VALUE Average Surface VALUE

Quick Estimation

Inversion Charge Estimation

QI= C

ox(V

GSV

T)

L

Below threshold applied voltage produces BULK charge NOT free charge!

QI= C

ox(V

GSV

T)

I =Charge in Channel

time to move charge out of channel

I =Cox

VGS

VT( )ZL

t

vd =L

t= E field

I = Z

LCox

VGS

VT( )VDS

E field Vdd

L

t =L2

Vdd

L

57

Zeroth Order Capacitor Current Model

IDS

VDSV

DS= V

GS- V

T

I CoxZ

L(V

GSV

T)V

DS

I CoxZ

L(V

GSV

T)2

Linear region

Saturation region

Is there a better model?

58

VDS = 0

VDS < VD,SAT

VDS =VD,SAT

Observation: Inversion Charge is not

always UNIFORM in Channel

Inversion Charge is not Uniform!

60

MOS Capacitor MOS Transistor

QNC

oxVGS

VT( ) for VGS VT

QNC

oxVGS

VT( )

for VGS

VT

Source Drain

Neglect the depletion region charge

61

ID=Z

n

LQ

Nd

= 0

=VDS

ID=Z

n

LC

oxVGV

T ( )d

= 0

=VDS

ID=Z

nC

ox

LVGS

VT( )VDS

VDS

2

2

0 VDS VDsat and VGS VT

This is known as the square law describing the Current-Voltage

characteristics in the Linear or Triode region.

First Order Square Law Model LINEAR REGION

62

For VDS>V

Dsat

ID= I

Dsat=Z

nC

ox

LVGS

VT( )VDsat

VDsat

2

2

VDsat VDS

But,

QN(y = L) C

oxVGS

VTV

Dsat( )= 0or

VGS

VT=V

Dsat

Thus,

ID= I

Dsat=Z

nC

ox

2LVGS

VT( )

2

VDsat

VDS

First Order Square Law Model SATURATION REGION

63

MOS Transistor I-V Derivation

TGSDsatVVV =

ID= I

Dsat=Z

nC

ox

2LVGS

VT( )

2

VDsat

VDS

ID=Z

nC

ox

LVGS

VT( )VDS

VDS

2

2

0 VDS

VDsat

and VGS

VT

Example CalculationCalculate the current through the MOSFET assuming that the threshold voltage is

0.6V and the rest of the parameters correspond to 180nm technology. Assume that

the VGS

= VDD

and VDS

= VDD

/2. Also assume that the surface mobility is 200 cm2/Vs,

and the transistor width is 10x the transistor length.

First we must consider the whether the device is in cutoff, linear region, or saturation.

Now we can use the appropriate formula!

VD,SAT

= VGS

VT= 1.8 0.6 = 1.2V

VGS

> VT

1.8 is greater than 0.6 therefore NOT in cutoff!

VDS = 0.9 is less than VD,SAT = linear region!

ID=Z

nC

ox

LVGS

VT( )VDS

VDS

2

2

0 VDS

VDsat

and VGS

VT

ID

= 10* 200* 6.903e 7 1.8 0.6( )0.9(0.9)

2

2

ID= 9.319e 4[A] = 0.9319mA



the VGS

= VDD

and VDS

= 0.8*VDD

. Also assume that the surface mobility is 200

cm2/Vs, and the transistor width is 10x the transistor length.


Now we can use the appropriate formula!

VD,SAT

= VGS

VT= 1.8 0.6 = 1.2V

VGS

> VT

1.8 is greater than 0.6 therefore NOT in cutoff!

VDS = 0.8*1.8 = 1.44 is greater than

VD,SAT = saturation region!

ID= 10* 0.5* 200* 6.903e 7 1.8 0.6( )

2[ ]

ID= I

Dsat=Z

nC

ox

2LVGS

VT( )

2

VDsat

VDS

ID= 9.940e 4[A] = 0.9940[mA]



the VGS

= 0.1 V and VDS

= 0.8*VDD

. Also assume that the surface mobility is 200

cm2/Vs, and the transistor width is 10x the transistor length.


VGS

> VT

0.18 is less than 0.6 therefore in cutoff!

ID 0

ID,sub = Ix (1 e

VDS

kT / q )e

(VGS

VT )

S

VGS

=0

= Ix (1 e

VDS

kT / q )e

VT

S

A more accurate answer is that that there is leakage! Notice dependence below!

S = subthreshold slopeIx= parameter that is proportional to device width (Z)

Subthreshold Leakage Currents

ID,sub = Ix (1 e

VDS

kT / q )e

(VGS

VT )

S

VGS

=0

= Ix (1 e

VDS

kT / q )e

VT

S

A more accurate answer is that that there is leakage! Notice dependence below!

S = subthreshold slope

Ix= parameter that is proportional to device width (Z)

exponential dependence on threshold voltage

Subthreshold current Z

Subthreshold current e

VT

S

Conclusion

68

Channel Length Modulation Effect

For VDS

> Vdsat

= VGS

-VTn

, pinch-off region grows by L !

As VDS

grows, the potential across

channel stays as (VGS

-VTn

)

All excess voltage is across pinch off

region

69

Channel Length Modulation

ID= I

Dsat=Z

nC

ox

2LVGS

VT( )

2

1+ V

DS( ) VDsat VDS

Channel Length Modulation Effect

Channel Length Modulation Parameter

Current Equations

70

NMOS PMOS

Regardless of

Mode

Cutoff

Linear

Saturation

VTfor

Enhancement

Mode

Pierret)in Z W:(Note ' ===L

WC

L

WKK

oxnnn

K

p= K

p

'W

L=

pC

ox

W

L (Note: W = Z in Pierret)

TNGSDSVvfori = 0 i

SD= 0 for v

SG V

TP

iDS

=Z

nC

ox

2LvGS

VTN( )

2

1+ v

DS( )

for vDS

vGS

VTN

0

iSD =Z

pC

ox

2LvSG VTP( )

2

1+ vSD( )

for vSD vSG +VTP 0

iDS

=Z

nC

ox

LvGS

VTN( )vDS

vDS

2

2

vGS

VTN

vDS

0

iSD

=Z

nC

ox

LvSG

VTP( )vSD

vSD

2

2

vSG

+VTP

vSD

0

0>TNV 0

Mosfet Operation

Documents

Transcript of Mosfet Operation