MOS InvertersDigital Electronics - INEL 4207

Prof. Manuel Jiménez

With contributions by: Rafael A. Arce Nazario

Objectives:• Introduce MOS Inverter Styles

•Resistor Load•Enhancement Load – Saturated / Linear•Depletion•Complementary (CMOS)

• Perform DC analysis of the circuits

• Operation regions (Enhancement)– VGS <VT :cutoff ,Vout =VDD

– VGS >VT ,VDS >VGS -VT : saturation– VGS >VT ,VDS <VGS -VT : linear

Ideal Inverter

MOS Devices

• Operation regions

• VGS <VT :cutoff ,Vout =VDD

• VGS >VT ,VDS <(VGS -VT ): linear

• VGS >VT ,VDS >(VGS -VT ): saturation

MOS Devices

0≈DI

2)(2 TGSD VVkI −=

[ ]2)(22 DSDSTGSD VVVVkI −−=

)1()(2

2DSTGSD VVVkI λ+−=

K=device transconductanceλ

= channel-length modulation

• VOH = max output voltage when output is “1”

• VOL = min output voltage when output is “0”

• VIL = max input voltage which can be interpreted as “0”

• VIH = min input voltage which can be interpreted as “1”

Static Parameters

Vin

VOH=VDD

VM

VOL

VM

Vout

VIL VIH

VOH=VDD

VM

VOL

VM

Vout

VIL VIH

VOH =VDD

VM

VOL

VT VM VOH =VDD

Vout

Vin

Vout =Vin

Vout =Vin -VT

VIL VIH

MOS Inverter - Resistor Load

IN

OUT

VDD

RL

|VGS | <VT device is open circuit

| VGS | > VT device conducts with resistance RON

VOH

DDOH VV =

( )

( )TDDL

DDOL

L

OLDDOLOLTDD

RlinD

VVkRVV

RVVVVVVk

II

−+≅⇒

−=⎥

⎦

⎤⎢⎣

⎡−−

=

1

2

2

)(

MOS Inverter - Resistor Load : Parameters

VOL Assumption: Must verify latter

MOS Inverter - Resistor Load : Parameters - VIL

( ) ( )

( )

LTIL

LTinD

out

in

D

in

out

LL

outDD

outout

D

D

out

TinTininin

D

D

out

in

D

in

out

kRVV

RVVkdI

dVdVdI

dVdV

RR

VVdV

ddVdI

dIdV

VVkVVkdV

ddVdI

dIdV

dVdI

dVdV

1

1

2

1

11

2

+=

−=−−=−=

−=⎟⎟⎠

⎞⎜⎜⎝

⎛⎟⎟⎠

⎞⎜⎜⎝

⎛ −=⎟⎟

⎠

⎞⎜⎜⎝

⎛=

−=−=

−=−=

−−

( )

1

22

−=

−=−

in

out

L

outDDTGS

dVdV

RVVVVk

[ ]( )

2

0.1

0.1

Tinout

DSTGS

DS

D

DS

GS

D

in

out

D

out

in

D

in

out

VVV

VVVkkV

dIdV

dVdI

dVdV

dIdV

dVdI

dVdV

−=

−=−−

−=−=

−=−=

( )[ ]L

outDDoutoutoutTIH R

VVVVVVVk −=−− 22

2

( )L

TIH

L

DDTIHTIHTIH R

VVR

VVVVVVVk222

12

2 −−=

⎥⎥⎦

⎤

⎢⎢⎣

⎡⎟⎠⎞

⎜⎝⎛ −

−⎟⎠⎞

⎜⎝⎛ −

−

…solve quadratic expression by VIH

MOS Inverter - Resistor Load : Parameters - VIH

…substitute in (1)

(1)

VM

( )

( )

( ) ( )L

TDDT

L

TDDLTM

L

DDT

LTMM

MDDTM

DSDDRTGSDS

kRVVV

kRVVkR

VV

kRVV

kRVVV

RVVVVk

RVVIVVkI

−+≅

−−++=⇒

=⎟⎟⎠

⎞⎜⎜⎝

⎛−+⎟⎟

⎠

⎞⎜⎜⎝

⎛−−

−=−

−==−=

2121

0212

2

2

22

2

2

MOS Inverter - Resistor Load : Parameters - VM

Effect of RL on VTC

As RL increases

But putting a larger resistance would also mean:• larger resistor length• greater switching delays

main disadvantage of resistor load:• occupies to much chip area (10s or 100s times the area of a single transistor!)

Using enhancement transistors as load devices

• Justification: Since VLSI resistors occupy to much chip space use transistor in either saturation or linear region instead of resistor

VDD

Vin

Vout

VDD

VinVOUT

VGG

VDD

Vin

Vout

• Enhancement NMOS with VGS = VDS

while VOUT < VDD – VTthe transistor will be in saturationbecause VGS > VT & VDS > VGS -VT

If VOUT tries to go above VDD-VT , transistor goes cutoff(because VGS < VT )

Saturated enhancement load

INV

OUTV

= VT

VIL VIH

VOH

VOL

Slope = -1

Slope =

=VDD- VT(VOH)

RK

load

inverterR LW

LWK)/(

)/(=

VDD

Vin

Vout

Saturated enhancement load - VTC

( )FFSBTT VVV φφγ 220 −++=

• Enhancement NMOS with VGG > VDD +VT

since VDS = VDD-VOUTand VGS = VGG -VOUT > VDD +VT –VOUT

VDS < VGS - VT

since VGS > VT : the load is always on linear region

VDD

VinVOUT

VGG

Linear enhancement load

Pro:• VOH = VDD

Disadvantage:• Additional voltage source• KR must be even larger than for saturated load for decent slope

Linear enhancement load - VTC

VDD

Vin

Vout

• Depletion NMOS with VGS = 0

VGS > VT : always conducting

Depletion load

Good: VOH = VDDno additional V source

Bad: addit. fab. process steps

Complementary MOSFET inverter

Features:• Complementary MOS (CMOS) Inverter analysis makes use of both NMOS and PMOS transistors in the same logic gate.+ All static parameters of CMOS inverters are superior to those of NMOS inverters+ CMOS is the most widely used digital circuit technology in comparison to other logic families.· lowest power dissipation · highest packing density -Increased process complexity (to provide isolated transistors of both polarity types)

Complementary MOSFET (CMOS) inverter

S

D

S

D

Intuitively:VIN ≈

0

NMOS open ckt. (VGSn <VTn )PMOS conducting (VGSp > VTp )

VOUT = VDD

VOH = VDD (Good!)

VIN ≈

VDDNMOS conductingPMOS open ckt.

VOUT = 0

VOL = 0 (Great!)

1. PMOS linear, NMOS off

2. PMOS linear, NMOS sat

3. PMOS, NMOS both sat

4. PMOS sat, NMOS linear

5. PMOS off, NMOS linear

CMOS inverter - VTC

12

VOH =VDD

VM

VTn VM VOH =VDDVOL =0

Vout

-VTp

3

45

VDD -VTp

VIN =VTn +

2

PMOS linear, NMOS saturation

RegionCMOS inverter – Region 2

NMOS linear, PMOS saturation

CMOS inverter – Param. Calculation Example Calculate VIH

2|)||(|2 TpGSp

pDp VV

kI −=

[ ]2)(22 OUTOUTTnIHn

Dn VVVVkI −−=

)/(1|)|)(/(2

1)(

)(

1

np

TPDDnpTnOUTIH

TnOUTIHn

TpIHDDpOUTn

in

out

DnDp

out

in

DnDp

in

out

kkVVkkVV

V

VVVkVVVkVk

dVdV

dIdIdV

dVdIdI

dVdV

+

−++=

−=−−

−−+−=

−=−

−−=

Substitute in (1), then solve for VOUT , finally obtain VIH

(1)

NMOS & PMOS saturation

CMOS inverter – Param. Calculation Example Calculate VM

22

2

2

|)|(2

|)||(|2

|)||(|2

|)||(|2

TpMDDp

TnMn

TpGSpp

Dp

TnGSnn

Dn

VVVk

VVk

VVk

I

VVkI

−−=−

−=

−=

.. Solve for VM

Summary

• CMOS inverter – most used, smallest, lowest power dissipation, best inverter characteristics.…base for more complex logic gates

• Calculation of static parameters: VIH , VIL , VOH , VOL , VM .

•Important: Deduce the region of operation of the transistors (verify later)• VIH , VIL slope = -1, use chain rule to simplify calculations• VTC affected by R, KR

Recordatorio

• Buscar copias de Dr. Jimenez en Reproducciones ($1-$2) – “Digital circuits using MOS transisitors”