mos fabrication - UTEP · Fabrication Overview ! aim of course not to teach fabrication – simply...
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MOS Fabrication Prof. MacDonald 1
Transcript of mos fabrication - UTEP · Fabrication Overview ! aim of course not to teach fabrication – simply...
MOS Fabrication
Prof. MacDonald
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Fabrication Overview
l aim of course not to teach fabrication – simply an overview of basic steps – circuit designers need to understand process – other classes provide details (Lush, Quiñones, Zubia)
l Basic steps – photolithography – pattern setting – implantation – add dopants to silicon – deposition – add new layers (metals, oxides) – etching – take away sections of layers – oxidation – for gate oxides - need native oxide
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Fabrication
Si Wafer
Si Wafer are now migrating from 200 mm to 300 mm Generally around 25 mm thick - fragile
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Fabrication – well implant
Si Wafer
High energy implant buries well dopants deep in wafer.
photo resist pattern block
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Fabrication – well implant
Si Wafer
High energy implant buries well dopants deep in wafer.
photo resist pattern block
NWell for PFETs
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Fabrication – shallow trench iso etch
Si Wafer – P type
STI replaced natively grown field oxides in the late 90’s. Dig trench and fill it in with oxide.
NWell for PFETs PWell for NFETs
photo resist block photo resist block
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Fabrication - shallow trench iso deposit
Si Wafer – P type
All area not filled with STI is active area and is free to contain transistors.
NWell for PFETs PWell for NFETs oxide
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Fabrication – gate
Si Wafer – P type
Natively grow ultra-thin gate dielectric (15 angstroms) and deposit poly silicon as gate node.
NWell for PFETs PWell for NFETs
Very thin native oxide provides clean electrical interface.
poly silicon acts as the gate node and can withstand subsequent high temperature processing (i.e. implants) Metal used originally.
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Fabrication – source/drain implant
Si Wafer – P type
Heavy dose / lower energy implant. Gate provides mask for channel – referred to as self-aligned implant
NWell for PFETs PWell for NFETs
photo resist pattern block N+ N+
N+
P
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Fabrication – inter layer dielectric
Si Wafer – P type
Chemically deposited Oxide. New challenge is to use low k dielectrics. Mechanical problems exists.
NWell for PFETs PWell for NFETs
inter-layer dielectric
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Fabrication – inter layer dielectric
Si Wafer – P type
Contact deposition – Tungsten plugs
NWell for PFETs PWell for NFETs
inter-layer dielectric
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Fabrication – metal 1 deposit
Si Wafer – P type
Traditionally aluminum, now copper
NWell for PFETs PWell for NFETs
inter-layer dielectric
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Fabrication – metal 2 and beyond
Si Wafer – P type
repeat – deposit ILD, etch and deposit vias, deposit metal and etch. Most chips today have 7 layers of metal.
NWell for PFETs PWell for NFETs
inter-layer dielectric
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Fabrication – metal 2 and beyond
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Fabrication – metal 2 and beyond
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Schematic of inverter
I1
I2 out in
inverter is simplest CMOS circuit input low – PFET turns on NFET turns off output pulled high input high – PFET turn off, NFET turns on output pulled low 16
Layout of inverter – top view
start with n-well (p-well block) for location of PFETs NFETs can be anywhere else 17
Layout of inverter – top view
create active area. ISO exists everywhere else.
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Layout of inverter – top view
grow gate oxide, deposit poly, where poly crosses active area you have a transistor.
n-well
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Layout of inverter – top view
Channel length defines process node (e.g. 0.25u, 180nm, 130nm, 90nm, 60nm, 45nm, 35nm, 22nm etc).
n-well minimum photo-lithographical dimension
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Layout of inverter – top view
Width of active area defines width of transistor. The wider the more drive current. PFETs generally are wider as holes have less mobility than electrons.
n-well
W
W
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Layout of inverter – top view
deposit contacts and metal 1 connections
n-well
drain
drain
source
source
gate
vdd
gnd
input output
well ties keep PWELL grounded and NWELL at Vdd
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Layout of inverter – top view
n-well
drain
drain
source
source
gate
vdd
gnd
input
I1
I2 out in
I1
I2
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Chip Circuit Rows
single circuit row
nwell
pwell
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Chip Circuit Rows
single circuit row
our inverter
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Chip Circuit Rows
single circuit row
our inverter
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Chip Circuit Rows
single circuit row NAND NOR our inverter
Flip Flop
inv inv 3 input NAND
3 input NOR
full adder
This what a chip looks like to logic designers – no transistors just logic blocks. Routing not shown. 27
Die Photo – PowerPC 970 64 bit uP
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Die Photo – PowerPC 405LP
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Die Photo – Pentium
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