Mont-Blanc work Past, present &...
Transcript of Mont-Blanc work Past, present &...
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montblanc-project.eu | @MontBlanc_EU
This project has received funding from the European Union's Horizon 2020 research and innovation program under grant agreement n° 671697
Mont-Blanc work
Past, present & future
Etienne WALTER, Project manager (Bull/Atos)
Coordinator of Mont-Blanc phase 3
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PAST
March 2017 Mont-Blanc - Orap presentation 2
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Mont-Blanc objectives
March 2017 Mont-Blanc - Orap presentation 3
2012 2013 2014 2016 2015 2017 2018
Mont-Blanc
Mont-Blanc 2
Mont-Blanc 3
Proof of concept : HPC
computing based
on mobile embedded
technology
Extend the concept and
explore new possibilities • Prepare an industrial solution
• Test market acceptance
Vision: leverage the fast growing market of mobile technology for
scientific computation
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Mont-Blanc
March 2017 Mont-Blanc - Orap presentation 4
Mo
tiva
tio
n
• Mobile devices
• Low power
• Lower frequencies
• Clock gating mechanisms
• Low cost
• Mass market
• Increasing performance
• Good ratio
• Performance / power
• Performance / $
• Many missing features
• Low core count
• Poor network
• Lack of software Dem
on
stra
ted
• Parallel system software
• Cluster installation & management
• Runtime
• Tools
• Application scalability
• Even with very low end component technologies
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PRACE prototypes
• Tibidabo
• Carma
• Pedraforca
Mini-clusters
• Arndale
• Odroid XU
• Odroid XU-3
• NVIDIA Jetson
Mont-Blanc prototype
• Operational since May 2015 @ BSC
• 1080 compute cards
• Dual Cortex-A15
• GPU Mali-T604
• 4 GB LPDDR3
• Up to 64 GB local storage
• USB-to-Eth network
• Fine grained power monitoring system
ARM 64-bit mini-clusters
• APM X-GENE2
• Cavium ThunderX
• NVIDIA TX1
The Mont-Blanc prototype ecosystem
March 2017 Mont-Blanc - Orap presentation 5
2012 2013 2014
Prototypes are critical to accelerate software development System software stack + applications
2015 2016 2017
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6
Exynos 5 compute card 2 x Cortex-A15 @ 1.7GHz 1 x Mali T604 GPU 6.8 + 25.5 GFLOPS 15 Watts 2.1 GFLOPS/W
Carrier blade 15 x Compute cards 485 GFLOPS 1 GbE to 10 GbE 300 Watts 1.6 GFLOPS/W
Blade chassis 7U 9 x Carrier blade 135 x Compute cards 4.3 TFLOPS 2.7 kWatts 1.6 GFLOPS/W
Rack 8 BullX chassis 72 Compute blades 1080 Compute cards 2160 CPUs 1080 GPUs 4.3 TB of DRAM 17.2 TB of Flash
35 TFLOPS 24 kWatt
The Mont-Blanc prototype
March 2017 Mont-Blanc - Orap presentation 6
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Application based fault tolerance
Fine grained task-based checkpointing within the runtime (FTI)
Error recovery
Application Based Fault Tolerance
Error detection
Exploit “unused” bits of data (pointers) for storing check-sum of data
Full chain tested on a real application
March 2017 Mont-Blanc - Orap presentation 7
Successful experiments on x86, ARMv7 and ARMv8
Compensating hardware limitations at software level
Issue: Provide resiliency in an unprotected system
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Power monitoring
Fine grained power monitoring infrastructure
Integrated with standard tools
Paraver to correlate performance and power
consumption
SLURM plugin for jobs energy accounting
March 2017 Mont-Blanc - Orap presentation 8
Issue: Improve the Mont-Blanc power monitoring infrastructure
Development of energy aware job scheduling policies
Improvement of tools
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Memory fault statistics and analysis
Developed a simple in-house memory scanner
Scanning user-space (~3GB/node) when nodes are idle
Collected statistics for 13 months / 12 Tbytes/hours
Fact: Memory of Mont-Blanc prototype is not ECC protected
Can we survive with this? What do we learn from this?
Cf Unprotected computing : a large scale study of DRAM raw error rate on a supercomputer L. Bautista, F. Zyulkyarov, O. Unsal, S. McIntosh-Smith
99% of the errors are concentrated in 3 nodes
After data analysis, a model of “quarantine
technique” has been developed.
MTBF from 2.1 hours to 156.9 hours.
Affecting 0.5% of the cluster resources.
March 2017 Mont-Blanc - Orap presentation 9
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Mont-Blanc 1/2 observations
March 2017 Mont-Blanc - Orap presentation 10
• Between applications, system integrator and technology providers (IP, SoC, runtime…)
Overall need of tighter co-design
• Node architecture is a key component
• A more balanced & more aggressive approach is needed for full exploitation of benefits
Hardware architecture
• Fundamental system and designer mentality
• Need to move towards task-based models, asynchrony, overlap communication/computation
• With minimum code refactoring cost
Software needs to evolve from latency-oriented
applications to throughput-oriented
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PRESENT
March 2017 Mont-Blanc - Orap presentation 11
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Going forward: Technical challenges (1/2)
New challenges with the diminishing
technology scaling observed (on core
performance, frequency …)
need to leverage new paradigms
How to optimize the global compute
efficiency ?
find optimal balance for
• I/O bandwidth & latency, memory, compute nodes
bypass unnecessary latencies
investigate benefit of heterogeneous architectures
March 2017 Mont-Blanc - Orap presentation 12
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Going forward: Technical challenges (2/2)
Assess planned architecture with simulation work
Get prepared for massive and efficient parallelism
Enhance the software environment
run times (OmpSs/OpenMP), tasks operations (MPI),
scheduler, compiler & math libraries
Always keep in mind applications
assess solution with real applications
enhance performance & energy monitoring tools (MAQAO,
system level)
hide/minimize the impact of HW architecture
March 2017 Mont-Blanc - Orap presentation 13
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Mont-Blanc 3 project key objectives
Design a compute node based on ARM architecture for a pre-exascale system
Well balanced : Memory, Interconnect, IO
Simulation will be used to evaluate the options on applications
Evaluate new high-end ARM core and accelerator, and assess different options for compute efficiency
Heterogeneous cores, new option for VPU, high performance core
Some assessment with existing solutions will be done using applications
One key idea : prepare to transform applications from being latency limited to throughput limited
Develop the software ecosystem needed for market acceptance of ARM solutions
March 2017 Mont-Blanc - Orap presentation 14
Prototypes
Scientific applications
HPC software ecosystem
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Work domains
March 2017 Mont-Blanc - Orap presentation 15
Architecture Simulation
Balanced Architecture
Computing Efficiency
Sw Environment
Applications
Hw. Platform (test cluster) & mini clusters
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March 2017 Mont-Blanc - Orap presentation 16
Architecture Simulation
Balanced Architecture
Computing Efficiency
Sw Environment
Applications
Hw. Platform (test cluster) & mini clusters
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WP5 Simulation Tools: evaluation of existing tools
March 2017 Mont-Blanc - Orap presentation 17
Name on-line/offline scope granularity speed(up)
gem5 (classic memory)
on-line core/SoC u-arch/insts ~100-200 KIPS
Elastic trace (gem5) off-line interconnect/memory system
u-arch/insts ~ 7x (gem5)
SimMATE (gem5) off-line memory system u-arch/insts ~6x – 800x (gem5)
Garnet (gem5) on-line interconnect ~0.2x (gem5)
TaskSim off-line compute node/task scheduler
arch/tasks ~ 10x native (burst) ~20x gem5 (memory)
Dimemas off-line cluster/off-chip network
bursts/messages “very fast”
SST/macro on-line cluster/off-chip network
bursts/messages ~ 0.3-3x native
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Multi-scale simulation workflow plan
March 2017 Mont-Blanc - Orap presentation 18
u-arch/insts arch/insts bursts/tasks inter-proc messages
SimMATE
TaskSim
Dimemas
Spee
d
Granularity
gem5 (on-line)
SST/macro
Elastic trace
dist-gem5
Scope
core/SoC multi-core compute-node cluster
MUSA
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March 2017 Mont-Blanc - Orap presentation 19
Architecture Simulation
Balanced Architecture
Computing Efficiency
Sw Environment
Applications
Hw. Platform (test cluster) & mini clusters
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Applications
Objective:
Provide input for co-design:
• key input for simulation
Search how to adapt programming practice to the throughput age – develop and promote best practices/recommendations on programming methodologies
Demonstrate architecture implementation
Sources:
Industrial applications (AVL)
Applications of interest at Supercomputing centers
Relevant Mini-apps from all over the world
Main achievements
Comprehensive study of a large number of applications
Porting & evaluation on ARM v8 platforms
March 2017 Mont-Blanc - Orap presentation 20
Applications
Runtime Architecture
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March 2017 Mont-Blanc - Orap presentation 21
Architecture Simulation
Balanced Architecture
Computing Efficiency
Sw Environment
Applications
Hw. Platform (test cluster) & mini clusters
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GCC LLVM Pathscale Mercurium Compilers
SLURM OpenLDAP NTP Ganglia Cluster management
OpenMP Nanos++ CUDA HSA MPI Runtime libraries
Drivers Ubuntu OpenSUSE CentOS Fedora Operating System (Linux kernel-based)
Power management Lustre NFS DVFS
Hardware support
CPU CPU CPU CPU
CPU
CPU
CPU
CPU
GPU CPU
GPU
Accelerator Accelerator Accelerator
Network
(Heterogeneous) Hardware
Extrae Perf MAQAO Allinea Developer tools
ATLAS ARM Mathematics Libraries BLIS Scientific libraries
Kernels Mini-applications Full applications Applications (source files – C/C++/Fortran/Python etc.)
HPC ARM Software Stack
March 2017 Mont-Blanc - Orap presentation 22
Porting MAQAO
Optimised ARM mathematics libraries
Porting PGI-Flang
OpenMP+OmpSs heterogeneous support
improvements
OmpSs accelerator support improvements
LLVM+GNU OpenMP optimisations
Porting TinyMPI
OmpSs and MPI communication/computation overlap
Topology-aware MPI
Linux kernel heterogeneous support improvements
memcpy-optimisations techniques via RDMA
Heterogeneous device specifications
Power management improvements
+ Contribution to OpenHPC (from 1.2)
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March 2017 Mont-Blanc - Orap presentation 23
Architecture Simulation
Balanced Architecture
Computing Efficiency
Sw Environment
Applications
Hw. Platform (test cluster) & mini clusters
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Compute Efficiency Effort
Objective: propose more aggressive
architectural designs
The focus is on:
increasing computation throughput
optimizing energy efficiency
Three lines of effort are followed:
Development and evaluation of a symbiotic combination of different
types of compute cores (big.LITTLE, in-order / OoO )
Analysis of ARM compute acceleration technologies (such as SVE) and
optimisation of the memory system
Evaluation of existing SoCs
March 2017 Mont-Blanc - Orap presentation 24
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Exploiting run-time priorities from the NoC
Hypothesis: Improve the performance of OmpSs applications by using QoS in the NoC favouring tasks in the critical path.
Goal: Reducing packet latency and, consequently, miss penalty of memory instructions of critical tasks.
Method: Generated packets (triggered by L1 cache misses) will include priorities (already used by Nanos’ scheduler) for QoS arbitration in NoC routers.
Background:
Adjust core frequency based on task criticality.
Additional support to change cores frequency using priorities.
We employ the same infrastructure to assign the priority of each L1 cache miss.
Chollesky
Tasks of the critical path (supposing the same length for all
types of task)
March 2017 Mont-Blanc - Orap presentation 25
Credit: CATA: Criticality Aware Task Acceleration for Multicore Processors (Castillo, E. et al. @ IPDPS’16).
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PRACE prototypes
• Tibidabo
• Carma
• Pedraforca
Mini-clusters
• Arndale
• Odroid XU
• Odroid XU-3
• NVIDIA Jetson
Mont-Blanc prototype
• Operational since May 2015 @ BSC
• 1080 compute cards
• Dual Cortex-A15
• GPU Mali-T604
• 4 GB LPDDR3
• Up to 64 GB local storage
• USB-to-Eth network
• Fine grained power monitoring system
ARM 64-bit mini-clusters
• APM X-GENE2
• Cavium ThunderX
• NVIDIA TX1
Mont-Blanc 3 Test platform
• Cavium ThunderX2
• Bull Sequana architecture
The new test-platform
March 2017 Mont-Blanc - Orap presentation 26
2012 2013 2014 2015 2016 2017
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Integration in industrial design (Bull sequana island)
March 2017 Mont-Blanc - Orap presentation 27
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Bull sequana compute blade with Cavium ThunderX2 cpu
March 2017 Mont-Blanc - Orap presentation 28
Cavium ThunderX2 CN99xx
ARM V8 Processor
Interconnect Mezzanine
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Test-platform objective
Integration test-bed for sw infrastucture
& applications
Validation of simulation models
Test customer acceptance
Generate further requirements
March 2017 Mont-Blanc - Orap presentation 29
to be deployed in H2 2017
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FUTURE
March 2017 Mont-Blanc - Orap presentation 30
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Towards a market driven approach
Prepare a solution than can be brought to the market
assess what would still be missing/needed to fulfill customer expectations
find right cost/features balances
adapt an industrial integration approach, preparing scalability and volume production
set-up industrial partnerships & ecosystem
Keep the right timing
Time-to-Market
but development cycles are heavy & risky
Get prepared for next steps
acceptance of ARM based solutions
approach the market with project results
March 2017 Mont-Blanc - Orap presentation 31
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Further steps (within or beyond current scope of work)
Continue effort on software stack
Continue SoC design work
Memory issues: work on NVM/HBM/3D-memories
Interconnect integration
Work on data (storage/movement)
Work on accelerators
Secure the SoC provisioning
reinforce the partnership with our provider
(Cavium)
evaluate alternative sources
consider a European sourcing (funding issue)
March 2017 Mont-Blanc - Orap presentation 32
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Perspectives
Our vision :
Need to permit « good independence » between apps & HW levels • (SVE’s vector-length agnosticism is a good example)
• need to provide programmers with the right programming paradigms
• kind of “loose coupling” model between apps & hw developments
One single solution cannot optimally fit all needs, all Apps • need for an architecture flexible enough to permit and facilitate adaptation
We are (co)operating in a wide environment
European projects & stakeholders (POP, Sage projects for instance)
Non-European projects: US (Argonne labs), Japan …
Exascale is a collective journey
we’re probably just in the middle
& Europe must take a significant part
March 2017 Mont-Blanc - Orap presentation 33
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montblanc-project.eu | @MontBlanc_EU
This project has received funding from the European Union's Horizon 2020 research and innovation program under grant agreement n° 671697
Thank you for your attention
Credits : all Mont-Blanc partners (third phase, but also first & second phases)