Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf Topics Testability and architecture....
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Transcript of Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf Topics Testability and architecture....
![Page 1: Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf Topics Testability and architecture. Design methodologies. Multiprocessor system-on-chip.](https://reader036.fdocuments.net/reader036/viewer/2022062308/56649eb55503460f94bbd6a4/html5/thumbnails/1.jpg)
Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Topics
• Testability and architecture.• Design methodologies.• Multiprocessor system-on-chip.
![Page 2: Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf Topics Testability and architecture. Design methodologies. Multiprocessor system-on-chip.](https://reader036.fdocuments.net/reader036/viewer/2022062308/56649eb55503460f94bbd6a4/html5/thumbnails/2.jpg)
Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Architecture testing
• Want to make system as testable as possible with minimum cost in hardware, testing time.
• Can use knowledge of architecture to help choose testability points.
• May want to modify architecture to improve testability.
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Some scan latches are more useful than others
• Acyclic register-transfer graphs are easy to test.
• Register-transfers with feedback are harder to test—state becomes contaminated during test.
• When choosing partial scan registers, choose feedback paths first.
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Identifying partial scan opportunities
• Construct register graph, which shows connections between registers:– nodes are registers;– edge between two nodes if there is a
combinational path between them.
• Sequential depth is distance from primary input to a node.
![Page 5: Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf Topics Testability and architecture. Design methodologies. Multiprocessor system-on-chip.](https://reader036.fdocuments.net/reader036/viewer/2022062308/56649eb55503460f94bbd6a4/html5/thumbnails/5.jpg)
Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Register graph example
machine
register graph
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Analyzing register graphs
• High sequential depth implies that the register is harder to test.
• Registers contained register-graph cycles (FF2-FF3) are hard to test (although self-loops are not hard).
• Add partial scan registers to effectively reduce sequential depth of node and its neighbors.
![Page 7: Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf Topics Testability and architecture. Design methodologies. Multiprocessor system-on-chip.](https://reader036.fdocuments.net/reader036/viewer/2022062308/56649eb55503460f94bbd6a4/html5/thumbnails/7.jpg)
Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Built-in self test (BIST)
• Includes on-chip machine responsible for:– generating tests;– evaluating correctness of tests.
• Allows many tests to be applied.• Can’t afford large memory for test results
—rely on compression and statistical analysis.
![Page 8: Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf Topics Testability and architecture. Design methodologies. Multiprocessor system-on-chip.](https://reader036.fdocuments.net/reader036/viewer/2022062308/56649eb55503460f94bbd6a4/html5/thumbnails/8.jpg)
Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Generating vectors
Use a linear-feedback shift register to generate a pseudo-random sequence of bit vectors:
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
BIST architecutre
• One LFSR to generates test sequence.• Another LFSR captures/compresses
results.• Can store a small number of signatures
which contain expected compressed result for valid system.
![Page 10: Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf Topics Testability and architecture. Design methodologies. Multiprocessor system-on-chip.](https://reader036.fdocuments.net/reader036/viewer/2022062308/56649eb55503460f94bbd6a4/html5/thumbnails/10.jpg)
Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Design methodologies
• Every company has its own design methodology.
• Methodology depends on:– size of chip;– design time constraints;– cost/performance;– available tools.
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Generic design flow
architecturalsimulation
floorplan
register-transferdesign
logicdesign
circuitdesign
layout
functional/performanceverification
testability
detailedspecs
tapeout
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Specification and planning
• Driven by contradictory impulses:– customer-centric concerns about cost,
performance, etc.;– forecasts of feasibility of cost and performance.
• Features, performance, power, etc. may be negotiated at early stages; negotiation at later stages creates problems.
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Estimation and planning
• Estimation techniques vary with module:– memories may be generated once size is
known;– data paths may be estimated from previous
design;– controllers are hard to estimate without details.
• Estimates must include speed, area, power.
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Floorplanning and budgeting
• The purpose of early floorplanning is to establish budgets for each major component: area, delay, power, etc.
• The project leader must ensure that budgets are met at all times. If it becomes clear that meeting a budget for a component is impossible, the floorplan must be redone ASAP.
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Logic design
• For controllers, good state assignment is usually requires CAD tools.
• Logic synthesis is an option:– very good for non-critical logic;– can work well for speed-critical logic.
• Logic synthesis system may be sensitive to changes in the input specification.
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Circuit/layout design
• Tasks:– size transistors;– draw layout.
• Alternative design styles:– full custom logic (very tedious);– standard cell.
• Full custom most likely for datapaths, least likely for random logic off critical path.
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Design validation
• Must verify:– layout (design rule check = DRC);– circuit performance;– clock distribution;– functionality;– power consumption / power bussing.
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Testing
• Automatic test pattern generation = ATPG.• Must verify that circuit can be tested,
generate a compact set of manufacturing test vectors.
• Test vectors often comprised of vectors taken from simulation + ATPG-generated vectors.
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Tapeout
• Tapeout: generating final files for masks. Shipped to mask-making house.
• Pre-tapeout verification is importance since it will take months to get results from fab.
• Tapeout party follows. Size of party depends on importance of chip design project.
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Multiprocessor systems-on-chips
• System-on-chip is a complete integrated system.
• MPSoC has more than one processing element:– CPU.– DSP.– Hardwired accelerator.
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Styles of MPSoC
• Homogeneous, as in multicore.• Heterogeneous:
– Several different types of processing elements.– Non-uniform memory system, with different
PEs accessing different parts of memory.– Non-uniform interconnect structure.
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
MPSoCs and IP
• MPSoCs require a lot of IP:– Processing elements.– Memories.– Networks-on-chip.– I/O devices.
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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf
Trimedia TM-1300 architecture