Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf Topics n Performance analysis of...

Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf

Topics

Performance analysis of sequential machines.


Unbalanced delays

Logic with unbalanced delays leads to inefficient use of logic:

long clock periodshort clock period


Signal skew

Machine data signals must obey setup and hold times—avoid signal skew.


Clock skew

Clock must arrive at all memory elements in time to load data.


Qualified clocks and skew

Logic in the clocking path introduces delay. Delay can cause clock to arrive at latches at

different times, violating clocking assumptions.

When designing qualification logic:– minimize and check skew;– sharpen clock edge.


Qualification skew example


Clock period

For each phase, phase period must be longer than sum of:– combinational delay;– latch propagation delay.

Phase period depends on longest path.


Unbalanced delays

Logic with unbalanced delays leads to inefficient use of logic:

long clock periodshort clock period


Flip-flop-based system performance analysis


Flip-flop-based system model

Clock signal is perfect (no rise/fall), period P. Clock event on rising edge. Setup time s.

– Time from arrival of combinational logic event to clock event.

Propagation time p.– Time for value to go from flip-flop input to output.

Worst-case combinational delay C.– Time from output of flip-flop to input.


Clock parameters


Clock period constraint

P >= C + s + p. s p C


Clock with rise/fall


Rise/fall clock period constraint

P >= C + s + p + tr. s p Ctr


Min-max delays

Delays may vary:– Manufacturing

variations.– Temperature variations.

Min/max delays compound over paths.– Delays within a chip

are correlated.

t


Latch system clock period

For each phase, phase period must be longer than sum of:– combinational delay;– latch propagation delay.

Phase period depends on longest path.


Latch-based system model


Two-phase timing parameters


Clock period constraint

Total clock period (both phases):– P >= C1 + C2 + 2s + 2p.

Each phase must meet timing for its own latch.


Latch-based system model


Advanced performance analysis

Latch-based systems always have some idle logic.

Can increase performance by blurring phase boundaries. Results in cycle time closer to average of phases.


Example with unbalanced phases

One phase is much longer than the other:


Spreading out a phase

Compute only part of long paths in one phase:


Spreading out a phase, cont’d.

Use other phase for end of long logic block and all of short logic block:


Problems

Hard to debug—can’t stop the system. Hard to initialize system state. More sensitive to process variations.


Timing and glitches in FSMs

If inputs don’t change, can outputs glitch?

DQ

logicinput output


Skew

Skew: relative delay between events. Signal skew: most important for

asynchronous, timing-dependent logic. Clock skew: can harm any sequential

system.


Signal skew

Machine data signals must obey setup and hold times—avoid signal skew.


Signal skew example


Clock skew

Clock must arrive at all memory elements in time to load data.


Clock skew example


Clock skew in system

D Q

D Q

logic


Clock skew and qualified clocks


Clock skew analysis model

s12 = 1 – 2s21 = 2 – 1


Skew and clock period

Assume that each flip-flop operates instantaneously:– T >= 2 + 12

If clock arrives at FF2 after FF1, then we have more time to compute.

Given clock period, determine allowable skew:– s12 >= T + 2


Timing through logic

As skew increases, we have less time to get the signal through the logic.


Clock distribution

Often one of the hardest problems in clock design.– Fast edges.

– Minimum skew.


Clock skew example

10 ps 10 ps

20 ps 20 ps

30 ps 30 ps

D Q D QD Q

D Q


Retiming

Retiming moves registers through combinational logic:


Retiming properties

Retiming changes encoding of values in registers, but proper values can be reconstructed with combinational logic.

Retiming may increase number of registers required.

Retiming must preserve number of registers around a cycle—may not be possible with reconvergent fanout.

Modern VLSI Design 4e: Chapter 5 Copyright 2008 Wayne Wolf Topics n Performance analysis of...

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