MODERN 1 st Year Review ENIAC-120003 MODERN Ref. Technical Annex MODERN_PartB Rev2 v2.4

MODERN 1st Year Review ENIAC-120003 MODERN Ref. Technical Annex MODERN_PartB Rev2 v2.4

WP1: Giuliana Gangemi WP2: André Juge

WP3: Wilmar Heuvelman WP4: Davide Pandini

WP5: Loris Vendrame

Coordinator: Jan van Gerwen

Date: June 22, 2010 (09.30 - 17.00 hrs)

Review period: 2009-03-01 : 2010-02-28

2CONFIDENTIAL MODERN 1st Year ReviewJune 22, 2010

Agenda

General information (JvG)– Objectives– Consortium– Resources planned and used– Overview of deliverables and milestones status– Cooperation, dissemination and exploitation– Project management: progress, funding problems and amendments– Other issues, Q&A

For WP1 (GG), WP2 (AJ), WP3 (WH), WP4 (DP) and WP5 (LV)– Relationship between workpackages– Progress, highlights and lowlights– Technical status and achievements of deliverables (incl. changes)– Cooperation– Dissemination (publications, patents), exploitation– Other issues, Q&A


Objectives

The objective of the MODERN project is to develop new paradigms in integrated circuit design that will enable the manufacturing of reliable, low cost, low EMI, high-yield complex products using unreliable and variable devices.

Specifically, the main goals of the project are: Advanced, yet accurate, models of process variations for

nanometre devices, circuits and complex architectures. Effective methods for evaluating the impact of process variations

on manufacturability, design reliability and circuit performance. o Reliability, noise, EMC/EMI.o Timing, power and yield.

Design methods and tools to mitigate or tolerate the effects of process variations on those quantities applicable at the device, circuit and architectural levels.

Validation of the modelling and design methods and tools on a variety of silicon demonstrators.

1

23 4 5

Layout and strain induced variability (Synopsys)


Consortium

The MODERN Consortium features strong competence and expertise in the field of advanced technologies, with a well-balanced participation between Large Industries, SMEs, Research Centres and Universities from all over Europe.

9 Countries28 Partners


Resources planned and used

Work

Package

Title

9 1 4 2 26 4 20

58 5 5 6 6 30 6

107 6 19 18 7 12 17 7 4 6 1256 20 7 13 160

639 19 54 84 60 24 42 48 18 48 23 32 12 174

198 0 16 5 12 6 70 18 19 4 8 15 18 7137 15 5 12 6 68 6 18 7

0730 44 36 13 24 18 204 66 102 108 18 23 15 12 27 20

169 0 0 12 9 55 12 14 5 15 15 19 8 677 9 12 14 6 24 120

603 66 24 36 12 78 36 30 30 36 72 60 58 23 42

52 6 16 3 3 18 0 0 0 6 038 15 3 2 18 0 00

274 14 63 19 6 54 24 10 18 12 38 16

29 1 0 2 2 0 0 1 1 1 12 0 2 0 1 3 1 218 2 1 1 1 10 0 1 20

115 5 5 6 5 2 6 6 2 2 6 30 12 3 6 2 4 3 3 6

563 0 13 0 14 9 33 19 18 55 0 27 27 31 119 40 0 5 19 19 19 4 12 0 17 30 0 19 15331 0 0 0 0 9 32 0 20 0 0 27 27 32 114 0 0 0 0 24 0 6 0 0 0 0 0 19 21

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 02,419 66 43 73 42 12 109 56 84 84 66 95 56 108 342 120 288 36 90 72 108 18 70 0 50 30 186 30 84

'(*) NOT FUNDED IN ITALY

TOTAL

Actual totalPlan total

Cum. Act. totalCum. Plan total

12. C

EA

-LE

TI

13. M

ontp

ellier

Labora

tory

26. V

ienna U

niv

ers

ity

15. N

um

onyx Ita

ly S

rl

16. (C

oord

inato

r) N

XP

-NL

18. P

olit

ecnic

o d

i Torino

19. S

TM

icro

ele

ctr

onic

s S

.r.l.

20. S

ynopsys S

witz

erland L

LC

22. T

IEM

PO

SA

S

21. T

hale

s S

A

28. U

niv

ers

ity o

f C

ala

bria

29. T

he U

niv

ers

ity o

f G

lasgow

23. D

elft

Univ

ers

ity

24. E

indhoven U

niv

ers

ity

25. G

raz U

niv

ers

ity

27. A

lma M

ate

r S

tudio

rum

31. U

niv

ers

itat P

olit

ecnic

a d

e C

ata

lunya

WP4

Architectural to system level:

modeling, analysis, and

Cum.Plan total

Planned total

WP1

Target technologies,

application domains,

WP2

Process/device to compact modeling

Cum. Act. total

5. T

ekla

tech

Physical/circuit to RT-level: PV-aware and PV-

robust

Actual totalPlanned total

Planned total

Cum. Act. totalCum.Plan total

Actual total

WP3

2. A

ustr

iaM

icro

syste

ms A

G

3. C

SE

M

4. E

lastix

PERIOD: m1 to m12

30. S

apie

nza U

niv

ers

ita d

e R

om

a

Cum. Act. total

6. In

fineon T

echnolo

gie

s

8. IM

EP

-LA

HC

Labora

tory

Actual total

10. In

tegra

ted S

yste

m D

evelo

pm

ent S

A

11. C

onsorz

io N

azio

nale

TO

TA

LS

1. S

TM

icro

ele

ctr

anic

s S

A

9. S

TM

icro

ele

ctr

onic

s S

AS

Actual total

Cum. Act. total

Cum.Plan total

Actual totalPlanned total

Cum. Act. totalCum.Plan total

Planned totalWP5

Test structures and

demonstrators

WP6

Management, dissemination

and exploitation

Planned totalCum. Act. totalCum.Plan total

Cum.Plan total

Actual total

Partner - Person-month per Workpackage

TABLE 3. PERSON-MONTH STATUS TABLECONTRACT N°: 120003ACRONYM: MODERN


Overview of deliverables and milestones status (1)Del. no. Deliverable name WP no. Task

leadNature Dissemina

tionlevel

Delivery date

(proj. month)

Contributors (lead)

Actual / Forecast

delivery date

Delivered Comments

D1.1 Definitions of problems and technologies,Specifications for tools, methods and design techniques

1 ST-I R PP M06 ST-I, AMS, IFXA, NMX, NXP, THL

15-06-2010 No Postponed

D1.2 Check list and verification tests for tools, methods and design techniques

1 ST-I R PP M12 ST-I, AMS, IFXA, NMX, NXP, THL

31-07-2010 No Postponed

D2.2.1 Assessment of state-of-the-art TCAD methodology and usability concerning PV for industrial purposes including identification of current deficiencies of tools

2 UNGL R CO M06 UNGL 10-09-2009 Yes

D2.2.2 Device simulation analysis of dominant variability sources in 45nm planar bulk CMOS technologies. Prototype implementation of the treatment of individual dopants and traps in the device modelling tools

2 UNGL R CO M12 UNGL, UNET, ST-I, SNPS

26-02-2010 Yes

D2.3.1 Characterization of the influence of variability sources in planar bulk CMOS devices down to 45nm.Experimental characterization of Non-Volatile- Memory devices in the presence of PV.Parametric mismatch fluctuation effects in 32 nm FinFETs, first PV results on 22nm FDSOI MOSFETS

2 NXP R CO M12 STF2, IMEP, UNET, NXP NMX, LETI, UNGL

29-03-2010 Yes

D2.4.1 Specification of considered degradation effects, modelling approaches and device parameters

2 AMS R CO M06 UNGL, TUW 09-09-2009 Yes

D3.1.1 Set of alternative symbolic models for lib cells 3 TUD P CO M12 NXP, ST-I, TUD, TUE, UNRM

23-04-2010 Yes

D3.2.1 Process development kit (PDK), circuit techniques, and speed-up algorithms for PV-aware circuit simulation

3 UNBO R CO M12 ST-I, UNBO, UNCA, UNRM

02-04-2010 Yes

D3.3.1 PV-tolerant schematics evaluation and Monitor & Control (M&C) strategies in digital and AMS&RF

3 POLI R CO M12 CSEM, IFXA, LETI, POLI, UPC

29-03-2010 Yes


Overview of deliverables and milestones status (2)

Del. no. Deliverable name WP no. Task lead

Nature Disseminationlevel

Delivery date

(proj. month)

Contributors (lead)

Actual / Forecast

delivery date

Delivered Comments

D3.4.1 Impact of supply noise, and clock distribution on EMI and circuit timing

3 NXP R CO M12 LIRM, ST-I 16-04-2010 Yes

D3.4.2 RF-interaction models for combined PCB-package-IC 3 NXP R CO M12 NXP 02-04-2010 YesD4.2.1 PV-tolerant asynchronous blocks, ultra low-power circuits and

architectures, and asynchronous/de-synchronization flow4 ELX R CO M12 TMPO, CSEM,

ELX, POLI, ST-I

15-02-2010 Yes

D4.3.1 Robust architecture specification and SystemC model 4 ISD R CO M12 THL, ST-F, ISD

01-02-2010 Yes

D5.1.1 Review of test structure state of the art and first results on intra-die variability and matching characterization on available structures in different technology nodes

5 AMS R CO M12 NMX, STF2, TUGI

28-02-2010 Yes

D5.2.1 Basic concept verification of on-chip monitor, noise, compensation, test chip architectures

5 IFXA R CO M12 NXP, IFXA 25-03-2010 Yes

D5.3.1 Software prototype implementation of MOR for MIMO systems of R, RC, RCL

5 SNPS R CO M12 NXP 01-04-2010 Yes

D6.1.1 Internal project website 6 NXP P CO M01 ST-I 01-06-2009 YesD6.1.2 IPR management guidelines 6 NXP R CO M01 NXP 01-10-2009 YesD6.1.3 Risk management plan 6 NXP R CO M06 NXP 09-10-2009 YesD6.1.4 Semi-annual project progress report 6 NXP R CO M06 NXP, all 04-12-2009 YesD6.1.5 Project activity report (Year 1) 6 NXP R CO M12 NXP, all 17-05-2010 YesD6.2.1 Public part of project web-site 6 UNET D PU M01 ST-I 01-06-2009 YesD6.2.2 Press release at the start of the project 6 UNET R PU M03 ST-I 04-09-2009 Yes


Overview of deliverables and milestones status (3)

Milestone number

Milestone name Work package(s) involved

Expected date (proj.

month)

Actual / Forecast

delivery date

Achieved Means of verification Comments

M1.1 Problem Definition and Tests 1,2,3,4,5 M12 31-07-2010 No D 1.1, D1.2 PostponedM3.1 Abstract Models CMOS and AMS&RF 3 M12 22-04-2010 Yes Abstract models for CMOS cell

libraries reported and verified

M3.3 PV aware circuit simulation techniques 3 M12 02-04-2010 Yes PV aware circuit simulation techniques working and verified

M3.5 M&C strategies for digital and AMS&RF 3 M12 29-03-2010 Yes M&C strategies for digital and AMS&RF developed and verified

M3.7 RF interaction models 3 M12 02-04-2010 Yes RF interaction models developed

M4.1 PV-tolerant asynchronous/de-synchronized, ultra low-power, robust functional blocks, and SystemC models

4 M10 15-02-2010 Yes D4.2.1D4.3.1

M4.2 Prototype asynchronous/de-synchronization flow 4 M10 15-02-2010 Yes D4.2.1M6.1 First project review by ENIAC all M08 22-06-2010 No Reviewer’s feedback Planned 22-06-2010


Cooperation, dissemination and exploitation

10

CONFIDENTIAL MODERN 1st Year ReviewJune 22, 2010

Project management: progress, funding problems and amendments

11


Other issues Q&A

12


WP1: Relationship between workpackages

13


WP1: Progress, highlights and lowlights

WP1 has the following specific objectives:

– 1. Clearly define the issues related to nano-electronic technologies that will be tackled in the MODERN project (e.g.,sensitivity of performances, power, yield, deficiencies of existing design techniques, etc).

– 2. Set the target technologies for which the above listed problems will be faced.

– 3. Define the specifications of the prototype tools, methods and flows that will come up as solutions of the previously listed problems.

– 4. Define the requirements of the integration work needed to embed the new tools into the existing design frameworks provided by the EDA partners within the flows in use at ST, NMX, IFX,THL, AMS and NXP.

– 5. Define up front all activities of all WPs of MODERN exception made of the management.

14


WP1: Progress, highlights and lowlights

Task T1.1 Problem Definition. Technology Definition

Partners: ST-I, AMS, IFXA, NMX, NXP, THL,ST-F

Description of the problems to be addressed in the project. Agree on the technologies to be used

Task T1.2 Feasibility Study. Definition of Tool Specifications

Partners: ST-I, AMS, IFXA, NMX, NXP, THL,ST-F

Define a list of tools, methods and design practices to be developed in technical WPs.

Feedback from WP2, WP3, and WP4 leaders will be needed in this task.

For any of items (tools, methods and design practices) defined above, produce the relative specification.

Task T1.3 Specification of Tool demonstration and validation

Partners: ST-I, AMS, IFXA, NMX, NXP, THL,ST- F

For each tool or method specified produce a verification plan or check list to check the tool not only meets the specification but also solve the problem defined in the problem definition Task 1.4

15


WP1: Technical status and achievements of deliverables (incl. changes) 1 of 2

D1.1 due M6 delivered at M15 (June the 22nd 2010)

D1.2 due M12 delivered at M15 (June the 22nd 2010)

M1.1 Problem Definition and Tests due M12 delivered M15 (june the 22nd 2010)

CHANGES Description and Motivations

– D1.1: “Specification of internal design flows, environments and existing tools interfaces and industrial requirements for upgrades “

– D1.2 “Verification of upgrades achieved by the MODERN deliverables according the specifications”

16


WP1: Technical status and achievements of deliverables (incl. changes) 2 of 2

Explanation:

The specification activity has gone forward at Task level within each work Package.

From Tools, Models,Design techniques specifications , done internally in each Work Package, we moved to the definition of the the Industrial requirements for upgrades.

Chage of perspective due to the fact that now the partners requirements are different from what thought at proposal time and the WP1 activities have started trying to make converge all partners necessities and the synthesis requirements of the different WPs in the best format with respect to the day by day activities.

The purpose to make the WP1 outcome more useful to the project and the partners has made necessary the decision to delay the deliverable D1.1 to the 15th of June 2010 (and consequently the D1.2 to end of July2010).

A new template for D1.1 has been agreed and we require now all Silicon Vendors involved in the project to contribute to it.

17


WP1: Cooperation

WP leader: ST-I

Strong dependence on partners: NXP,THL,IFX,AMS,ST-I,SNPS ,ST-F

Collaboration with partners: NXP,THL,IFX,AMS,ST-I,SNPS ,ST-F ,

collaboration

Telephone conferences with: NXP,THL,IFX,AMS,ST-I,SNPS ,ST-F according requirements of deliverables.

With WP Leaders weekly since the month of May.

18


WP1: Other issues, Q&A

19



20


Task T2.x: Task name

Partners (underlined task leader):

Explain in a few words: goal of task, what you did this period, what will be delivered and when.

Explain in a few words: what went well, better than expected and what went worse than expected; describe corrective actions.

WP2: Progress, high- and lowlights

21


WP2: Technical status and achievements of deliverables (incl. changes)

22


WP2: Cooperation

WP leader: STF2

If strong dependence on partners: list partners, describe dependence

Collaboration with partners: list partners, collaboration (division of labor, role, …)

Face to face meetings with: list partners (when)

Telephone conferences with: list partners (when)

23


WP2: Dissemination (publications, patents), exploitation

24



25



26







27



28


WP3: Cooperation

WP leader: NXP





29



30



31



32







33



34


WP4: Cooperation

WP leader: ST-I





35



36



37



38







39



40


WP5: Cooperation

WP leader: NMX





41



42



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MODERN 1 st Year Review ENIAC-120003 MODERN Ref. Technical Annex MODERN_PartB Rev2 v2.4

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Transcript of MODERN 1 st Year Review ENIAC-120003 MODERN Ref. Technical Annex MODERN_PartB Rev2 v2.4