Modeling Snapback and Rise-Time Effects in TLP Testing for ESD ...

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WCM 2005, May 9-12, Anaheim, CA, USAYuanzhong (Paul) Zhou

Modeling Snapback and Rise-Time Effects in TLP Testing for ESD MOS

Devices Using BSIM3 and VBIC Models

Yuanzhong (Paul) Zhou, Duane Connerney, Ronald Carroll, Timwah Luk

Fairchild Semiconductor, South Portland, ME 04106

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Outline

• Research Motivation

• Snapback in MOS Devices and Previous Models

• Macro Model using BSIM3 and VBIC

• Advantages of New Macro Model

• Simulation of Snapback and Rise Time Effect

• Results and Discussions

• Conclusion

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Research Motivation

ESD Is a Major IC Reliability Concern: Responsible for 30%~50% Customer Returns

Accurate SPICE Models for Integrated ESD Simulation Can Reduce ESD Design Iteration

MOSFETs in Snapback Operation Mode Are Widely Used as ESD Protection in CMOS Technology

Rise Time of ESD Pulse Has Significant Impact on Performance of MOS ESD Protection

A Practical SPICE Macro Model for Snapback of ESD MOS Devices is Needed and Good Understanding on the Rise Time Effect is Helpful.

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Snapback in MOS Devices• Four Regions in I-V Curve

– (1) Linear Region– (2) Saturation Region– (3) Avalanche Region – (4) Snapback Region

Region (4)

Region (1)

Region (2)

Region (3)

Gate Bias

Vd

Id

Vt1

N+N+

STI STISTI

Pwell

VG

P+Substrate

P+

DV

Isub

Ic

Ib

Ids

Depletionlayer

Electrons Emitted when S/BJunction Is Forward Biased

SV

ImpactIonization

Rsub

• Snapback due to Parasitic NPN – Holes Created by Impact Ionization in

D/B Depletion Layer Are Injected Into Substrate

– Parasitic NPN turns on when voltage drop cross Rsub ( Vbe of BJT) (Isub×Rsub) reaches ~0.7V

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Previous MOS Snapback Models(1)

• Numerical SPICE Models Have Been Publicly Reported

• Four Essential Components: – Main MOS– Parasitic BJT – Avalanche Current Source – Substrate Resistor

• The BJT Is Modeled With EM or GP Models

G

DS

B

RdRs

Rsub

Igen

Ic

Ids

Id=Ids+Ic+Igen

Isub

Ib

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Previous MOS Snapback Models(2)

• The Explicit Current Source Is Given by

where M is multiplication fact, given by Miller formula

or

( ) ( )cdsgen IIMI +⋅−= 1

−−⋅−

=

dsatd VVK

KM

2exp11

1( )[ ]11exp ddsatd VVkM −−= ( )[ ]22exp ddsatd VVk −−+

• The Models Are Implemented either in Proprietary SPICE, or Using Behavior Language Verilog-A or VHDL-A

• The Verilog-A Models Can Have Low Simulation Speed and May Cause Serious Convergence Problems

• Proprietary SPICE Has Limited Accessibility to Designers and Needs Extra Support

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Macro Model Using BSIM3 and VBIC

• Our New Macro Model Structure Includes Three Main Components: – NMOS modeled by BSIM3 – Parasitical NPN modeled by VBIC – Substrate resistance

G

DS

B

RdRs

Rsub

Cbe Cbc

CgdCgs

Cgb

Bi

E CId=Ids+Ic

Iave

Isub• The Impact Ionization Current or

Avalanche Current Source Is Built in BSIM3 and VBIC Models

( ) ( )( )121−−⋅−⋅−⋅⋅=

MCbciVPCAVCeVPCAVCII bcicave

( ) IdsaeVdeffVdsLeff

Isub VdeffVds

−−

⋅−⋅

+=

00

1β

αα

IaveIsubIgen +=

• Equivalently, We Have

similar to ( )[ ]11exp ddsatd VVkM −−= ( )[ ]22exp ddsatd VVk −−+

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Advantages of New Snapback Macro Model

Simple Structure and Strong Capability• Standard components only and no external current source • Partially decoupled substrate current for BJT and intrinsic MOS• Transient simulation capability from sophisticated capacitance modeling in

BSIM3 and VBIC• High simulation speed since no Verilog-A or VHDL-A involved• Less convergence issues due to no Verilog-A and fine-tuned algorithms of

BSIM3 and VBIC• VBIC offers simulation capability for self-heating effect

A Practical Approach: Easy to Implement and Use• No need using behavior languages (Verilog-A, …) • No need for special SPICE implementation by individual Users • The availability is high since both BSIM3 and VBIC are widely included in

various simulators.• CAD environment is compatible to non ESD models

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Simulation of Snapback and Rise Time Effect

Snapback was simulated with transient simulation using schematic below Voltage pulse sequences with varied rise time were used as the input The stabilized Vd and Id were measured as the simulation results

Voltagesource

50Ω

Schematic of TLP Simulation for ggNMOSInput voltage Vin, drain voltage Vd and drain

current Id vs. time t in a single pulse

0

2

4

6

8

10

12

0 20 40 60 80 100 120 140 160

Id

Vd

Vin

0

0.04

0.08

0.12

0.16

0.20

0.24

t (ns)

Vd/

Vin

(V)

Id (A

)

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Results and Discussions(1): Snapback Curves

Snapback curves demonstrate that trigger voltage Vt1 decreases as the rise time of the input pulse is reduced

The dependence of Vt1 on the rise time was observed in ggNMOS and gcNMOS configurations

Snapback curves of a ggNMOS structure (lines: simulation, symbols: measurement)

2 3 4 5 6 7 8 9 100

0.05

0.1

0.15

0.2

0.25

0.3

0.35

Trise=8ns

Trise=20ns

Vd (V)

Id (A

)

Snapback curves of a NMOS with a 10k resistor between gate and ground

(lines: simulation, symbols: measurement)

3 3.5 4 4.5 5 5.5 6 6.50

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

Vd (V)

Id (A)

Trise=1.5ns

Trise=8.0ns

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Results and Discussions(2): Trigger Voltage Vt1

Vt1 of gcNMOS was observed much more sensitive to the rise time than Vt1 of ggNMOS

Sensitivity simulation indicates that the overlap capacitance has no impact at all on Vt1 for ggNMOS but cause most variation for gcNMOS

Vt1 for ggNMOS is affected by junction capacitance and transit time

Vt1 vs. rise time for ggNMOS and gcNMOSobserved in measurement

Vt1 vs. CJC and tF in a ggNMOS(Trise=8ns)

8.0

8.4

8.8

9.2

9.6

10

Vt1

(V)

Transit Time (ps)100 200 300 400 500

0.8 0.9 1.0 1.1 1.2CJ / CJ0

Vt1 vs. Transit TimeVt1 vs. CJCVt1 vs. CJE

0 4 8 12 16 204

6

8

10

12

ggNMOS

gcNMOS

Vt1

(V)

trise (ns)

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Results and Discussions(3): Vbe Spike under ESD Pulse

Vgs>0 due to gate coupling is the well-known cause of Vt1 drop in gcNMOS

Vbe of NPN shows a spike at rising edge of input voltage pulse Vbe may drop back to a stabilized value or continue increasing. The

dividing point is corresponding to the trigger voltage

-0.8-0.6-0.4-0.2

00.20.40.60.8

1

0 20 40 60 80 100 120

Vpulse=8V

Vpulse=10V

Vpulse=9.14V

Vpulse=9.15V

Time (ns)

Vbe

(V)

00.10.20.30.40.50.60.70.80.9

1

3 4 5 6 7 8 9 10 11 12

Vbe_max

Vbe_pulse Vbe_DC

Vbe

(V)

Vpulse (V)

Vbe vs. Time in a single pulse for a ggNMOS

Vbe vs. ESD stress voltage in transient (Vbe_pulse and Vbe_max) and quasi-static (Vbe_DC) events for ggNMOS

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Results and Discussions (4)

Displacement current through the Drain/Bulk junction causes a Vbe spike in the parasitic NPN in ggNMOS.

Avalanche current in Drain/Bulk junction is enhanced by the Vbe spike, which eventually results in a lower trigger Vt1.

Higher CJC and shorter rise time (higher dV/dt) cause bigger Vt1 reduction.

It is important to properly model the Drain/Bulk junction capacitance as well the Source/Bulk junction capacitance and the base transmit time to achieve accurate simulation for the trigger voltage of ggNMOS snapback.

For NMOS with a resistor between gate and drain, Drain/Gate overlap capacitance is the dominant parameter Vt1 dependence on rise time

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Conclusion

A unique macro model structure for snapback simulation of ESD MOS devices has been developed

The model takes the advantage of built-in formulas and fine-tuned algorithms in sophisticated BSIM3v3 and VBIC models

It offers advantages of high simulation speed, wider accessibility, and less convergence issues

The model has been used for investigation of Vt1 dependence on the rise time of transmission line pulse (TLP)

The simulation demonstrated that the tf and junction capacitance of parasitic BJT have impact on Vt1 even for ggNMOS

The cause of Vt1 drop in ggNMOS is the displacement current due to dV/dt in TLP pulses

Modeling Snapback and Rise-Time Effects in TLP Testing for ESD ...

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