Solid-State Electronics 47 (2003) 2131–2134

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Short Communication

Modeling and simulation of asymmetric gatestack (ASYMGAS)-MOSFET

Manoj Saxena b, Subhasis Haldar c, Mridula Gupta a, R.S. Gupta a,*

a Semiconductor Device Research Laboratory, Department of Electronic Science,

University of Delhi, South Campus, New Delhi 110 021, Indiab Department of Physics & Electronics, Deen Dayal Upadhayaya College, University of Delhi, New Delhi 110 015, India

c Department of Physics, Motilal Nehru College, University of Delhi, New Delhi 110 021, India

Received 1 November 2002; received in revised form 1 March 2003; accepted 1 May 2003

Abstract

We propose a new structure, asymmetric gate stack (ASYMGAS)-MOSFET and its 2-D analytical model. There is

two-layer gate stack oxide near the drain and single gate oxide near the source. The model predicts a step function

profile in the potential along the channel, which ensures reduced DIBL. In ASYMGAS-MOSFET, the average electric

field in the channel is enhanced, and therefore electron velocity, near the source, which improves the overall carrier

transport efficiency. The results so obtained are verified using a two-dimensional device simulator, ATLAS, over a wide

range of device parameters and bias conditions. Good agreement is obtained for channel lengths down to 0.15 lm.

Thus, confirming the validity of our model.

� 2003 Published by Elsevier Ltd.

Keywords: ASYMGAS; Gate stack; DIBL; Carrier transport; Efficiency

1. Introduction

New technical challenges emerge as the critical di-

mensions of the MOS transistor are continually scaled

down to deep sub-micron for higher level of integration

and performance [1]. But as the gate length is reduced,

three problems persist: (a) short-channel effects (SCE),

(b) gate transport inefficiency and (c) hot electron effect.

There have been numerous device structures [2–4] re-

ported in the literature to overcome these problems.

Apart from the problems mentioned, the continued

scaling of SiO2-based gate dielectrics leads to large gate

leakage and therefore, a new structure i.e. asymmetric

gate stack (ASYMGAS)-MOSFET, in which gate

leakage is greatly reduced, is proposed for future ULSI

circuits. In ASYMGAS-MOSFET, the average electric

* Corresponding author. Tel.: +91-11-2410-5580; fax: +91-

11-2688-6606.

E-mail address: rsgu@bol.net.in (R.S. Gupta).

0038-1101/$ - see front matter � 2003 Published by Elsevier Ltd.

doi:10.1016/S0038-1101(03)00221-1

field in the channel is enhanced, and therefore electron

velocity, near the source, which improves the overall

carrier transport efficiency. The average electric field

under the gate further increases and the high density of

interface trap states reduces using a gate stack structure

[5–7]. In this note, we have tried to explain the advan-

tages of ASYMGAS-MOSFET, especially the step-

function in the potential profile, over the conventional

Si-MOSFET with the same geometric specifications that

allows us to utilize the benefits of ballistic and overshoot

transport. The results have been verified using 2-D de-

vice simulator: ATLAS [8].

2. Model formulation

Schematic structure of ASYMGAS-MOSFET is

shown as Fig. 1. The two-dimensional potential distri-

bution /ðx; yÞ can be obtained by solving 2-D Poisson�sequation. Assuming that the impurity density in the

Fig. 1. Schematic diagram of ASYMGAS-MOSFET.

2132 M. Saxena et al. / Solid-State Electronics 47 (2003) 2131–2134

channel region is uniform and that the influence of the

charge carriers on the electrostatics of the channel can

be neglected, the two-dimensional Poisson�s equation

can be expressed as

d2/ðx; yÞdx2

þ d2/ðx; yÞdy2

¼ qNA

eSið1Þ

where /ðx; yÞ corresponds to the electrostatic potential

in the channel, NA is the substrate doping density, q is

the electronic charge and eSi is the permittivity of silicon.

In the present analysis the channel region has been di-

vided into two parts in which the potential under the

single gate oxide (SGO) region and the gate stack oxide

(GSO) region can be represented as

/1ðx; yÞ ¼ /S1ðxÞ þ C11ðxÞy þ C21ðxÞy2 þ C31ðxÞy3

for 0 < x < L1 ð2aÞ

/2ðx; yÞ ¼ /S2ðxÞ þ C12ðxÞy þ C22ðxÞy2 þ C32ðxÞy3

for L1 < x < L1 þ L2 ð2bÞ

In conventional MOSFET, there is only one gate oxide

but in ASYMGAS structure we have SGO region near

the source and GSO region near the drain. Therefore,

the effective gate potential for the two regions, SGO and

GSO, would be different as it depends upon the effective

gate oxide thickness. The coefficients C11, C21, C31, C12,

C22, and C32 have been calculated using the boundary

conditions where the potential and the electric fluxes are

continuous at the gate oxide/Si interface and at the in-

terface of SGO and GSO regions and the electric field at

the depletion edge is zero and the potential is the sub-

strate bias––VSUB and the boundary conditions at the

source and the drain end are:

At the source end

/1ð0; 0Þ ¼ /S1ð0Þ ¼ Vbi ð3aÞAt the drain end

/2ðL1 þ L2; 0Þ ¼ /S2ðL1 þ L2Þ ¼ Vbi þ VDS ð3bÞOn substituting the values of C11, C21, C31, C12, C22, and

C32 in (2a) and (2b) we get

/1ðx; yÞ

¼ /S1ðxÞ �VG0 � /S1ðxÞ

ctox

� �y

þ 3ctox þ 2dctoxd2

ðVG0

�� /S1ðxÞÞ �

3ðVG0 þ VSUBÞd2

�y2

� 2ctox þ 2dctoxd3

ðVG0

�� /S1ðxÞÞ �

2ðVG0 þ VSUBÞd3

�y3

ð4aÞ

/2ðx; yÞ

¼ /S2ðxÞ �VG0 � /S2ðxÞ

ctox

� �y

þ 3ctox þ 2dctoxd2

ðVG0

�� /S2ðxÞÞ �

3ðVG0 þ VSUBÞd2

�y2

� 2ctox þ 2dctoxd3

ðVG0

�� /S2ðxÞÞ �

2ðVG0 þ VSUBÞd3

�y3

ð4bÞ

The surface potentials /S1ðxÞ and /S2ðxÞ under SGO

region and GSO region can be obtained by substituting

(3a) and (3b) into (1) and are obtained as

/S1ðxÞ ¼ VG0 � qNA

eSi

�þ 6ðVG0 þ VSUBÞ

d2

�k21

þg10 sinh

L1 � xk1

� �þ g1L1 sinh

xk1

� �� �

sinhL1

k1

� �ð5aÞ

/S2ðxÞ¼VG0 � qNA

eSi

�þ6ðVG0 þVSUBÞ

d2

�k22

þg20 sinh

ðL1þL2Þ�xk2

� �þg2L2 sinh

x�L1

k2

� �� �

sinhL2

k2

� �ð5bÞ

where

k1 ¼

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffictoxd2

2ð3ctox þ 2dÞ

s; k2 ¼

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffictoxeffd2

2ð3ctoxeff þ 2dÞ

s

M. Saxena et al. / Solid-State Electronics 47 (2003) 2131–2134 2133

VG0 is defined as VG0 ¼ VGS � VFB and c ¼ eSi=e1 where toxis the oxide thickness of SGO region, tox1 and tox2 are theoxide thickness of the e1 (SiO2) and the e2 (high-K) di-electric respectively in the GSO region, VGS is the gate-

to-source voltage, VSUB is the back-substrate bias, VFB is

the flat-band voltage and d is the short channel depletion

width [9].

toxeff ¼ tox1 þe1e2tox2 ð6Þ

where toxeff is the scaled thickness of the GSO region in

terms of the corresponding e1 (SiO2) thickness. Using the

boundary conditions where the potential and the electric

fluxes are continuous at the interface of SGO and GSO

regions along with (3a) and (3b), the coefficients g10, g2L2,g20 and g1L1 are evaluated and given as

g10 ¼ Vbi � VG0 þ qNA

eSi

�þ 6ðVG0 þ VSUBÞ

d2

�k21 ð7aÞ

g2L2 ¼ Vbi þ VDS � VG0 þ qNA

eSi

�þ 6ðVG0 þ VSUBÞ

d2

�k22

ð7bÞ

Fig. 2. Surface potential variation with the normalized channel

position. Circle and box represents simulation results for

ASYMGAS-MOSFET for tox1 ¼ tox2 ¼ 45 �AA. Diamond and

cross represent simulation results for conventional Si-

MOSFET, single gate oxide, having tox ¼ 90 �AA.

g20 ¼n3 þ n2m1

n1 þ n2g1L1 ¼ g20 � m1

where Vbi is the built-in-potential and VDS is the drain-to-

source potential and

n1 ¼1

k2sinh

L1

k1

� �cosh

L2

k2

� �ð8Þ

n2 ¼1

k1sinh

L2

k2

� �cosh

L1

k1

� �ð9Þ

n3 ¼ g101

k1sinh

L2

k2

� �� �þ g2L2

1

k2sinh

L1

k1

� �� �ð10Þ

m1 ¼qNA

eSi

�þ 6ðVG0 þ VSUBÞ

d2

�ðk21 � k22Þ ð11Þ

The electric field component, in the x-direction, underthe SGO region and under the GSO region can be ob-

tained by differentiating (5a) and (5b) respectively.

Fig. 3. Horizontal electric field, at the gate oxide/silicon inter-

face, variation along the normalized channel position calculated

using the model and from the ATLAS device simulation. Circle

and box represents simulation results for ASYMGAS-

MOSFET and diamond and cross represent simulation results

for conventional Si-MOSFET.

3. Results and discussion

At low drain voltages for SMG-MOSFET, the source

and drain fields cancel each other at the center of the

device. High drain voltage does not change the source

field, but it does increase the drain field. Therefore, there

is a shift in the zero-field point towards the source.

However, it is interesting to note that for DMG-

MOSFET there is not much change in the potential

under M1 even for high values of VDS. Hence, SGO re-

gion is screened from the changes in the drain potential.

So, the SGO region is called as the �controlling gate

oxide� and the GSO region is called �screening gate ox-

ide�. Fig. 2 shows that the magnitude of the positive-

offset voltage increases with the increase in permittivity,

2134 M. Saxena et al. / Solid-State Electronics 47 (2003) 2131–2134

e2, of the top-oxide layer in the gate stack region. As the

offset voltage increases so is the screening of region SGO

from drain voltage variation and therefore, more re-

duction in DIBL. The average electric field, under the

gate, increases with the increase in dielectric constant of

the top-gate oxide in GSO region due to the increase in

transverse electric field and is shown in Fig. 3. The peak

electric field at the drain for ASYMGAS structure with

high-K, as top-gate oxide in the GSO region, is lower

than for conventional single gate oxide Si-MOSFET.

This reduction in electric field leads to reduction of the

hot-carrier effect at the drain end.

4. Conclusion

A 2-D potential and electric field model is developed

for ASYMGAS-MOSFET. The step-function profile in

the surface potential exhibits improvement in screening

of the drain potential variation, and reduced short

channel effects. The peak in the electric field distribution

under the gate ensures more uniformity in the average

drift velocity of the electrons in the channel. The results

have been verified using ATLAS: 2-D device simulator.

Acknowledgement

The authors are grateful to the Defense Research and

Development Organization, Ministry of Defense, Gov-

ernment of India, for the necessary financial assistance

to carry out this research work.

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