Modeling and Design of a Low-Voltage SOI Suspended-Gate MOSFET(SG-MOSFET) with a Metal-Over-Gate Architecture

Adrian M. Ionescu1, Vincent Pott1,2, Raphael Fritschi1,2, Kaustav Banerjee3,Michel J. Declercq1, Philippe Renaud2, Cyrille Hibert2, Philippe Fluckiger2, Georges A. Racine2

1Electronics Laboratories (LEG), Swiss Federal Institute of Technology Lausanne, Switzerland2Center of Microtechnology (CMI), Swiss Federal Institute of Technology Lausanne, Switzerland

3Center of Integrated Systems, Stanford University, Stanford, CA, USAE-mail: Adrian.Ionescu@epfl.ch

AbstractA novel MEMS device architecture: the SOI SG-MOSFET, which combines a solid-state MOStransistor and a suspended metal membrane in aunique metal-over-gate architecture, is proposed. Aunified physical analytical model (weak, moderateand strong inversions) is developed and used toinvestigate main electrostatic characteristics in orderto provide first-order design criteria for low-voltageoperation and high-performance. It is demonstratedthat the use of a thin gate oxide (<20nm) is essentialfor a high Con/Coff ratio (>100) and a low springconstant (<100N/m) is needed for low voltage (<5V)actuation. An adapted fabrication process is reported.

1. IntroductionThe MEMS platform has attracted special

attention for RF ICs, especially wireless, because ofits gain in terms of: device and systemminiaturization, CMOS-compatibility, power savings,higher performances and, especially, newfunctionality, such as re-configurable circuitarchitectures in which RF switches could programsignal coupling to interconnect lines and passivecomponents are programmable and/or tunable [1-10].The basic building block of RF MEMS circuits is theRF-MEMS switch, which plays a similar role to theMOS switch in a standard RF system. RF MEMSdevices have several clear advantages over their solid-state counterparts (FETs and diodes): lower seriesresistances, low power operation and negligible inter-modulation distortion, [2-4].

This paper reports on the physical and analyticalmodeling and the design of a novel MEMS-devicearchitecture, called the suspended-gate (SG)MOSFET, which combines in a single cell aMOSFET and a MEMS switch with a metal-over-gatearchitecture. An adapted new technological process isproposed, involving the use of polysilicon oramorphous silicon as sacrificial layers. It isdemonstrated that the SG-MOSFET has some uniqueelectrical characteristics and is particularly adaptedfor low-voltage MEMS contact-less switches (withbetter performances for programmable interconnectsthan FPGA) and, furthermore, for high-Q tunableMEMS capacitors.

2. SG-MOS architecture and principleThe cross section and the principle of the SOI

SG-MOSFET are depicted in Fig. 1: it combines in atop-down architecture a metal membrane MEMSswitch and a partially depleted (PD) SOI MOSFET. Atypical device design inspired by RF MEMSmembrane switches, including suspension arms, isgiven in Fig. 2 that also shows its 3-D simulatedactuation under an uniformly distributed force, [11].When the front gate voltage, Vg1 (simply denoted byVg), is increased, the intrinsic gate-voltage, Vgint

(=Vgint1), which drives the MOS channel formation, istuned according to a capacitor divider:

gapintgc

gintg C/C1

VV

+= (1)

where Cgcint, Cgap are the intrinsic gate-to-channelcapacitance of the underneath MOSFET and the air-gap capacitance, respectively. Note that in thefollowing analysis the back gate (Vg2) and the body(Vb) of the PD SOI MOSFET are consideredgrounded. The gate membrane moves continuouslydownwards as long as the equilibrium is maintainedbetween electrostatic and elastic forces:

electr20gap

2intggair

elastic F)xt(

)VV(A

21

kxF =−−ε

== (2)

where x is the gate displacement, tgap0 the initial air-gap dimension and Vgint the intrinsic gate voltage.

When Vg equals the pull-in voltage, Vpi, unstableequilibrium is reached and the switch (suspendedmembrane) moves from the ‘off’ to the ‘on’ state(tgap=0). It is worth noting that in metal-metal platecapacitors, Vpi is a well-known non-linear function of:the initial air-gap, (tgap0-tox), the membrane area, A,and the spring effective elastic constant, k. Unstableequilibrium condition is reached at x=tgap0/3, which isa limiting factor for the tuning range of MEMScapacitors. It is can be demonstrated that the use of anMOS capacitor connected in series (like in the case ofSG-MOSFET architecture), underneath the suspendedmetal membrane, can slightly extend the equilibriumregion beyond tgap0/3 [3] and the well known Vpi

formulation of the metal-metal switch:

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30gap

0pi t

Ww27k8

Vε

= (3)

where W and w are the membrane and underneathmetal line widths, respectively, is no longer adapted,depending also on the value of the series capacitor.Note that the SG-MOSFET architecture has not anyunderneath metal line and, for simple analogy, it canbe considered that the inversion layer of the MOSFETplays the role of the underneath metal line of a metal-metal RF MEMS capacitive switch.

(a) (b)Fig. 1 (a) Cross section of n-channel SOI SG-MOSFET and (b) simplified electrical equivalentschematic.

Fig. 2 3-D numerical simulation with SOLIDIS [11]of the deflection of a SG-MOSFET metal membrane(100x100 µm2) under uniformly distributed force of1000Pa. The suspension hinge design (number ofmeanders) determines the equivalent elasticcoefficient, k.

3. SG-MOSFET unified DC modelIn order investigation, a long channel, partially

depleted (PD) SOI MOSFET (for which Si-bulkMOSFET models stand) is considered. The followingphysical unified expression of the gate-to-channelcapacitance, Cgc, available for weak, moderate andstrong inversions (with source, drain and back gatesupposed grounded for simpler analytical equations)is proposed:

[ ][ ] 1V/)2V)V(V(exp2/)1(

CV/)2V)V(V(exp2/)1(

CCCCC

)V(C

thFfbgintg

oxthFfbgintg

dinvox

invoxintgintgc

+ηηφ−−η−η

ηηφ−−η−η

=++

=

(4)where Cox, Cinv and Cd are the oxide, inversion anddepletion capacitances, respectively, η=1+Cd/Cox,Vth=kT/q is the thermal voltage, and the otherparameters are standard for MOSFET devices. Thissimple continuous formulation allows the compactintegration of the inversion charge as a function of theSG-MOSFET intrinsic voltage Vgint:

+

η

ηφ−−η−ηη=

== ∫∞−

1V

2V)V(Vexp

122

lnVC

dV)V(C)V(Q

th

Ffbgintgthox

V

intgintggcintginv

intg

(5)Eq. (5) is then used to derive the SG-MOSFET draincurrent at low voltage (quasi-linear regime) in both‘on’ and ‘off’ states of the switch. The proposedanalytical model is able to capture some uniquecharacteristics of the SG-MOSFET in a single,unified analytical expression:(i) the dynamic threshold voltage: low in the ‘on’

state and high in the ‘off’ state, which is a keyadvantage for RF switch use because of a higherisolation in the ‘off’ state compared to the solidstate MOSFET,

(ii) the super-exponential dependence of Qinv on Vg

in the subthreshold region,(iii) the super-linear dependence of Qinv on Vg in

both moderate and strong inversions.It is worth noting that in strong inversion, eq. (5)becomes similar to the well-known formulation of theinversion charge:

)V)V(V(C)V(Q Tgintgoxginv −= (6)

where VT=Vfb+2ηφF is the intrinsic threshold voltageand because Vgint is a non-linear function of Vg

through eq. (1), it follows that the SG-MOSFET has aspecific super-linear dependence of Qinv with respectto the gate voltage, Vg.

4. Design-Of-Experiment (DOE) andmodel predictionsBased on the new proposed analytical

formulation, calibrated by static 3-D electro-mechanical numerical simulation, various SG-MOSarchitectures with a metal-over-gate (Al) architectureand thin oxide (5-50nm) have been investigated.

The aim of our DOE was to identify anacceptable design window for a low voltage DCactuation (CMOS compatible), with acceptably smallgate area. As a first approximation, we have observedthat using the SG-MOSFET for RF switchapplications needs a low-loss (high resistivity or SOI)

Hinge

n+

n+

Gate (Al) membrane

L

W

drain

Equivalentspring

tgap tox

p n+n+

source

Suspended(movable)metal gate

x

Si substrate

Back gate

Vgint

Vs Vd

Vg1=Vg

Vg2

Buried oxide

Vb

Inversionlayer

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substrate and air-gaps in excess of 0.2µm (for betterisolation when the switch is not actuated).

Fig. 3 SG-MOSFET actuation for various tgap0.

Fig. 4 SG-MOSFET actuation for various k.

Fig. 5 SG-MOSFET actuation for various A.

Fig. 6 SG-MOSFET actuation for various tox.

Fig. 7 Intrinsic (internal) gate voltage, Vgint, vs.extrinsic gate voltage, Vg, with the oxide thickness,tox, as a parameter.

Figs. 3, 4, 5 and 6 depict typical calculated SG-MOSFET gate electrostatic actuations for various: (i)initial air-gap, tgap0 (Fig. 3), (ii) spring constant, k(Fig. 4), (iii) gate area, A=WxL (Fig. 5) and (iv)oxide thickness (Fig. 6).

Systematic calculations based on the proposedmodel suggest that a combination of spring constantless than 100N/m (possible by an adapted, meander-like, design of the gate hinges, Fig. 2), air-gap lessthan 0.5µm and area larger than 20x20µm2, define apreliminary SG-MOSFET low-voltage (Vpi<5V)window design. It is found that the gate oxidethickness has no great impact on the pull-in voltagevalue. This is also confirmed in Fig. 7, where theinternal gate voltage, Vgint, is plotted against the SG-MOSFET external gate voltage, Vg. It should benoted that the typical switching speed between ‘off’and ‘on’ states is estimated to be of the order of 10 to100µs (being dictated by the membrane pull-downtime, as for the metal-metal RF switches).

Another interesting result is suggested by Fig. 8 aand b, where the evolution of the SG-MOSFETsurface potential, ψS, is plotted for various parametersof the device architectures. It is found that themembrane always snaps down in moderate inversion,near the onset of strong inversion, which is a veryunique characteristic. This result is in good agreementwith [3] that reported on the non-equilibrium of asimilar device associated with strong inversion.Moreover, this result highlights the usefulness of aunified analytical model including all regimes ofMOS inversions (weak, moderate and strong).

A key parameter for a RF switch is the ratiobetween its capacitance in ‘off’ and ‘on’ states thatshould be larger than 100 [1, 2]. Typical SG-MOSFET switching capacitance characteristics arereported in Fig. 9 a and b. It is clearly demonstratedthat a Con/Coff ratio in excess of 100 can be obtainedby the use of a reasonably thin oxide (tox<10-20nm)instead of a large initial gap. This is a very useful andoriginal finding for the device design since in the low-voltage analysis it was shown that tox does notsignificantly impact the pull-in voltage value.

0.10 1.00 10.00 100.00

Vg (V)

tgap

(µµ µµ

m)

1.2

1.0

0.8

0.6

0.4

0.2

0

k(N/m)=100, A=WxL(µmxµm)=100x100, tox(nm)=10

tgap0+tox(µm) = 1

0.5

0.2

0.10.05

Vpi

0 1 2 3 4 5Vg (V)

tgap

(µµ µµ

m)

0.2

0.15

0.10

0.05

0

k(N/m)= 500200100502010

tox(nm)=10A=WxL(µmxµm)=100x100tgap0(µm)=0.19

0.0 5.0 10.0 15.0 20.0Vg (V)

tgap

(µµ µµ

m)

0.2

0.15

0.10

0.05

0

A=WxL(µmxµm)=10x10

20x2050x50

100x100200x200

k(N/m)=100tox(nm)=10tgap0(µm) =0.19

0.0 1.0 2.0 3.0

Vg (V)

tgap

(µµ µµm

)

0.2

0.15

0.1

0.05

0

tox(nm)=5

1020

50

k(N/m)=100A=WxL(µmxµm)=100x100tgap0(µm)=0.2

0.1

1

10

0.10 1.00 10.00

Vg (V)

Vg

int

(V)

k(N/m)=100A=WxL(µµµµmxµµµµm)=100x100tgap0+tox(µµµµm)=0.2

gate pulled-in:Vg = Vgint

tox(nm)= 50

5

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(a)

(b)Fig. 8 SG-MOSFET surface potential, ψS, versus Vg.

(a)

(b)Fig. 9 SG-MOSFET extrinsic capacitance, Cgc, vs.gate voltage, Vg: a) tox as a parameter; Con/Coff >100 isobtained for tox<10-20nm and b) k as a parameter.

The SG-MOSFET inversion charge, Qinv(Vg),derived from eq. (6) is plotted in Fig. 10. It can beobserved that there are more than five orders ofmagnitude difference between inversion charge in‘on’ and ‘off’ states (switch pulled-down and up). Itfollows that the device works as a combination of asolid-state MOSFET and a micromechanical switchand can also be useful for microrelay (or currentswitch) applications. The device drain current andtransconductance at low VD (=50mV) are reported inFigs. 11, 12 and 13. Typically, the switching occursprior to the onset of strong inversion (in moderateinversion) and the drain current has a slight super-linear dependence on the extrinsic gate voltage Vg.

It is worth noting that in the subthreshold region(weak inversion), because of the action of thecapacitor divider described by eq. (1), the SG-MOSFET can theoretically exhibit a localsubthreshold slope better than the ideal limit for asolid-state bulk or SOI MOSFET (60mV/decade).However, as already mentioned, the devicecommutation speed is essentially limited by theelectromechanical displacement of the suspended gatemembrane.

Fig. 10 SG-MOSFET inversion charge, Qinv, vs. gatevoltage, Vg, with k, as a parameter.

Fig. 11 SG-MOSFET drain current, ID, vs. gatevoltage, Vg, (in log-lin scale) at low drain voltage,VD=50mV, with k as a parameter.

0

0.2

0.4

0.6

0.8

1

1.2

0.00 1.00 2.00 3.00 4.00 5.00

Vg (V)

ψψ ψψS (V

)

k(N/m)=100A=WxL(µmxµm)=100x100tgap0(µm)=0.2

NA=1016cm-3

tox(nm) = 5 1020

50

2φF

Suspended gate pulled down: tgap=0

Suspended gatein equilibrium (up)

0.20

0.40

0.60

0.80

1.00

0 1 2 3 4 5

Vg (V)

ψψ ψψS (V

)

k(N/m)= 10 2001005020 500

tox(nm)=10, tgap0(mm)=0.19A=WxL(µmxµm)=100x100

2ΦF

NA=1016cm-3

0 1 2 3 4 5Vg (V)

Cg

c (F

/m2)

k(N/m)=100A=WxL(µmxµm)=100x100tgap0+tox(µm)=0.20

10-7

10-6

10-5

10-4

10-3

10-2tox(nm) = 5

10

20

50

Switch ON: Cgc =HIGH

Switch OFF: Cgc = LOW

0 1 2 3 4 5Vg (V)

Qin

v ( C

/m2 )

k(N/m)= 500200100502010

tox(nm)=10, tgap0(µµµµm)=0.19A=WxL(µµµµmxµµµµm)=100x100

10-1

10-2

10-4

10-5

10-6

gate membrane pulled-down

10-3

10-7

gate membranein equilibrium (up)

0 1 2 3 4 5Vg (V)

Cg

c (

F/m

2 ) k(N/m)= 500200100502010

tox(nm)=10, tgap0+tox(µµµµm)=0.2A=WxL(µµµµmxµµµµm)=100x100

10-2

10-3

10-4

10-5

10-6

~Cox

0 1 2 3 4 5Vg (V)

I d (

A )

k(N/m)= 500200100502010

tox(nm)=10, tgap0+tox(µµµµm)=0.20A=WxL(µµµµmxµµµµm)=100x100

10-4

10-5

10-7

10-8

10-9

Switch down

10-6

10-12

Switch up (equilibrium)

10-10

10-11 Subthreshold

OFF

ON

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Fig. 12 SG-MOSFET drain current, ID, vs. gatevoltage, Vg, (in lin-lin scale), at low drain voltage,VD=50mV, with k as parameter. Inset, the specificsuper-linear dependence in moderate inversion, priorto the gate snap-down, is highlighted.

Fig. 13 Transconductance, gm, vs. gate voltage, Vg,derived from data in Fig. 12.

5. Equilibrium and capacitor tuningrange

One key concern for the use of the SG-MOSFETarchitecture as a tunable RF capacitor is its limitedtuning range (around 50%) because of the snap-downevent near 1/3 of the gap. A significant increase of thetuning range can be essentially provided by theextension of the equilibrium via the series connectionof a constant value high-Q capacitor (Fig. 14). Theseries capacitor can be smartly integrated in theMEMS device by the use of one extra-metal layer; themovable gate is made of a metal-insulator-metalsandwiched architecture, instead of a single metal.The intrinsic gate voltage, Vgint, is now:

)CC(

)CC(C1

VV

gapstab

gapstabgc

gintg

⋅+⋅

+= (7)

In Fig. 15 the impact of various values of the seriescapacitance on the device stabilization is shown. Itappears that a trade-off should be considered amongthe tuning range (extension of the stable region) andthe low voltage actuation.

Fig. 14 Electrical equivalent circuit of the stabilizedSG-MOSFET, including a series capacitance, Cstab.

Fig. 15 Effect of a series capacitance, Cstab, on thegate displacement and extension of the SG-MOSFETequilibrium region. The device parameters are:A=200x200µm2, tgap0=0.2µm, tox=10nm, k=100N/m.

6. SPICE modelingTable 1 shows the mechanical-to-electrical

analogy that allows building a SG-MOSFET DCmacro-model for fast simulation with SPICE. Thespecific electrostatic displacement of the suspendedgate can be modeled by using an empiricalpolynomial voltage-controlled source, f(VG),combined with a conventional MOSFET model, asshown in Fig. 16. A second voltage source can beadded in order to model some hysteresis effectslinked with charge trapping in the gate oxide. Thepassive elements, R and L, mirror the damping andthe inertia (mass) of the SG-MOSFET membrane andare relevant especially for the membrane dynamics(transients) and AC investigations.

Table 1: Mechanical-to-Electrical AnalogyMechanical

VariableElectricalVariable

Damping, c Resistance, RStiffness-1, k-1 Capacitance, C

Mass, m Inductance, LForce, F Voltage, V

Velocity, v Current, I

Cd

0 2 4 6 8 10Vg (V)

t gap

(µµ µµ

m)

0.2

0.15

0.1

0.05

0

Equilibrium

Cstab(pF)=0.5

125

10

Vgint

ψψψψS

Cgap

Cox

Cinv

Vgsg

Vg

Cstab

0 1 2 3 4 5Vg (V)

I d (

nA

)k(N/m)= 10 2001005020 500

tox(nm)=10, tgap0+tox(µµµµm)=0.2A=WxL(µµµµmxµµµµm)=100x100

25

super-lineardependence

20

15

10

5

0

VD=50mV

0 1 2 3 4 5Vg (V)

gm

=d

I d/d

Vg(

nS

)

k(N/m)= 10 2001005020 500

20

15

10

5

0

VD=50mV

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Fig. 16 Equivalent electrical SPICE model of theSG-MOSFET according to the mechanical-to-electrical analogy reported in Table 1.

(a)

(b)Fig. 17 a) and b) AlSi membranes released using the drySF6 etching of sacrificial amorphous silicon (images withdifferent magnification factors).

7. Fabrication processState-of-the-art fabrication processes for RF

MEMS switches and tunable capacitors [4-10] usesurface micromachining to release the movable metalmembranes. Some typical sacrificial layers are SiO2,polymers and/or similar insulators.

This work reports on a new CMOS-compatibleMEMS-process, specially designed to provide SG-MOSFET architectures on SOI or bulk siliconsubstrates. The novelty of the process consists of theSF6 dry etching of polycrystalline silicon for therelease of the suspended SG-MOSFET metal gate.

Polycrystalline silicon is here the sacrificial layer. Analternative to this process consists of the use ofamorphous silicon (a-Si) instead polycrystallinesilicon. Amorphous silicon is also expected toimprove the underneath roughness of the releasedmetal membrane. The new releasing techniques arecombined with an adapted design of a metal-over-gatearchitecture, the suspended gate being made of Al orAlSi. In Fig. 17, SEM micrographs of fully suspendedAlSi membranes, released with the dry SF6 processand using a-Si, which becomes the sacrificial layer,are reported.

8. Conclusion

A novel MEMS device architecture: the SOI SG-MOSFET, which combines a solid-state MOStransistor and a suspended metal membrane, in ametal-over-gate architecture, was proposed. A unifiedphysical analytical model was developed and used topredict main electrostatic characteristics and providefirst-order design criteria for CMOS-compatible, low-voltage actuated RF switches. Main DCcharacteristics for both capacitive switch andmicrorelay applications are addressed. It is shown thatcontrolling the thickness of the gate oxide (<20nm) isessential for a high Con/Coff ratio (>100) and a lowspring constant (<100N/m), provided by specialmeander-like hinge design, is needed for <5Vactuation. Other key results concern the specificsuper-exponential and super-linear drain currentdependence on the gate voltage, at low drain voltage,the possibility to obtain a subthreshold slope betterthan the theoretical solid-state bulk/SOI MOSFETlimit and equilibrium extension solutions.

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R

L

f(Vg)+_

Vs Vd

Vg

kc

mF

n+ p n+

Vb

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