Mixed Signal VLSI Design: Advanced Digital and ... · PDF fileNeuromorphic Circuits ......

Department of Electrical Engineering and Information Technology Endowed Chair for Parallel VLSI-Systems and Neural Circuits

Mixed Signal VLSI Design: Advanced Digital and

Christian Mayr, 18.10.2010

Advanced Digital and Neuromorphic Circuits

Department of Electrical Engineering and Information Technology Endowed Chair for Neural Circuits and Parallel VLSI-Systems

Chair Overview

� 1 professor

� 1 assistant professor

� 19 research associates

15.07.2011 Slide 2

� 19 research associates

(analog/mixed-signal/digital ASIC designers)

� 1 technician

� 5 student assistants

� acquired third party funds in 2009: 1,2M EUR


Competencies

� Fullcustom Analog and Mixed Signal Circuit Design

� Sensor circuits (photosensors)

� Data converters, signal conditioning

� Physical Implementation of Nanoscale VLSI Circuits

� MPSoC implementation

15.07.2011 Slide 3

� MPSoC implementation

� Microchips in 40nm planned for 2011

� Concepts and Methodologies for Low-Power Design

� Energy efficient solutions for baseband processing

� Neuromorphic Circuits

� Neural event communication and routing

� VLSI and Biology in the Loop


Project Overview

� ZMDI AG - TU Dresden R&D Cooperation

� Design and Optimization of Mixed-Signal-Circuits (AD-Converter, Signal conditioning)

� BMBF-Project SyEnA: Synthesis driven design of analog circuits

� Infineon AG –TU Dresden R&D Cooperation

15.07.2011 Slide 4

� Infineon AG –TU Dresden R&D Cooperation

� Implementation of Multi Standard Baseband Processors (MuSIC2/3)

� EU-FP7-financed neuromorphic projects:

� IP BrainScaleS, Marie Curie Network FACETS-ITN: Waferscale Neuromorphic Hardware

� STReP CORONET: Closed-Loop Interfaces VLSI - Biology

� Cluster of Excellence CoolSilicon – CoolBaseStationICs Project

� Energy efficient Analog-/Mixed-Signal-Components and MPSoCs for baseband processing


R&D Cooperation with ZMDI

� Example:

15.07.2011 Slide 5

� Example:SAR-ADC Design

� 8x Input

� 14bit, 1M Sample/s

� 0.35µm XFAB

� System concept, ADC architecture, mismatch analysis, Design ADC core (Capacitance array, Trimming Methodic)


MASH 2-1-1 DSM with integrated novel preamplifier for automotive applications, area

10 Bit Delta-Sigma-Modulator (DSM) 2nd order in 65nm (03/2005, process not fully characterized) as test bed for analog circuit performance

CCII

amplifier

Instrumentation

amplifier

2-1-1 Σ∆ modulator

with preamplifier

0 0.5 1 1.5 2-0.5

0

0.5

1

1.5

2

2.5

Zeit (ms)

Spannung (V

)

15.07.2011 Slide 6

preamplifier for automotive applications, area advantage factor 4 compared to current literature

OPV

+ -

- +Inp

ut si

gn

al

VR

ef+

VR

ef-

VCM

VCM

Cadj

C0

CI

&Φ2

Φ2

Φ1

Φ1

Φ2Φ1

ADJ

FB

amplifier amplifier with preamplifier

Buffer with

adapt. biasing

Test

crossbar

Decimation and

digital control


� Goal: Reduction of porting and optimization effort

� Methodologies for automation of analog design technology migration� Lookup table methods for transistor characterization� Rule-based operating point porting strategies� Automated feasibility analysis of design portability

Technology Independent Design of Analog Integrated Circuits

15.07.2011 Slide 7


Fullcustom Analog and Mixed Signal Circuit Design

� Photosensor arrays in 90/65nmCMOS technology

� Design and

15.07.2011 Slide 8

� Design and evaluation of analog circuits in leading edge digital technologies


MPSoC Projects

TomahawkVendor : UMC

Die area : 100 mm²

Tape-out : 05/2007

Project : WIGWAM (BMBF)

Partner : Vodafone Chair

130 nm

MuSICVendor : Infineon

Die area : 64 mm²

Tape-out : 07/2006

Project : MxMobile (BMBF)

Partner : Infineon/FhG

90 nm

MuSIC2Vendor : Infineon/TSMC

Die area : 100 mm²

Tape-out : 2009

Project : Infineon


65 nm

15.07.2011 Slide 9


Flow : ICPROPartner : Infineon/FhG

Flow : Inway


Flow : Inway

ATLASVendor : TSMC

Die area : 16 mm²

Tape-out : 2010

Project : CoolBasestations (BMBF)


Flow : ICPRO

65 nm

MuSIC3Vendor : Infineon/TSMC

Die area : ?

Tape-out : 2011

Project : Infineon

Partner : Infineon

Flow : Inway

40 nm


Low Power Design – Power Aware Design Flow

MPSoC Architecture & Programming Model

Pow

er

Managem

ent

Pow

er

Managem

ent

• Power management features defined at architectural level have strong impact on hardware implementation

15.07.2011 Slide 10

Design

ImplementationPow

er

Managem

ent

Pow

er

Managem

ent

implementation

• Characteristics of implemented power management hardware determine efficiency of power management


� MuSIC2 – SIMD-Cluster

� 4 SIMD-Cores4 Processing elements,1 general purpose (GP) core each

Physical Implementation of Nanoscale VLSI Circuits

15.07.2011 Slide 11

core each

� 2 GP cores

� 4MBit Memory

� 800k standard cells

� 65nm CMOS

� Partial power shut-off

� 1.0V supply voltage


CoolBaseStationICs

� Goal: Power-reduction of MPSoCs for baseband processing

� System- und circuit concepts for power efficient NoC

(Network on Chip) architectures and on-chip-

communication

� Investigations of concepts for adaptive power regulation

15.07.2011 Slide 12

� Investigations of concepts for adaptive power regulation

(frequency and/or voltage scaling, power shut-off)

� Cell-based design of full-custom macros

(Register Files, FIFOs, datapath elements)

� Analog, mixed-signal components

(NoC-transceivers, voltage regulators)

� MPSoC demonstrator implementation (65nm CMOS)


ATLAS Testchip • GALS system based on ADPLLs

• Implementation of Power Shut Off (PSO) and Dynamic Voltage & Frequency Scaling

• Fast VDD switching

15.07.2011 Slide 13

• Fast VDD switching by on chip hardware

• Configurable low level power management CTRL

• NoC links for distances of several mm

• Maximum link bandwidth 72 GBit(bidirectional)


EU-Project FACETS, BrainScaleS, FACETS-ITNFast analog Computing with Emergent Transient States

15.07.2011 Slide 14


FACETS: Novel Computational Paradigms

The FACETS waferscale system: Neuromorphic circuits in a large-scale adaptive pulse-processing application

15.07.2011 Slide 15


Cutout of the FACETS waferscale system focused on the digital network


15.07.2011 Slide 16



10 Gbit/s linkcable

power supply boardwith current measurementcapabilities

sense cable GigabitEthernetcable

powercable

10V – 14Vpower input

referenceclock

differentialprobeHost control

15.07.2011 Slide 17

FPGA AER board

Digital NetworkASIC (DNC)

LVDS transmission

►Highly Integrated 14 Layer PCB with , ready for integration Waferscale

System

►Setup for Layer 2 and host communication for 4 DNCs(=32 HICANNs)


CORONET: Influencing Behaviour in Animals

15.07.2011 Slide 18

Micro-

Electrode

Array (MEA)

Cell Culture

Network States

Gentle Steering

Coupling

Dynamics

Biomimetic

Network

NeuroSoC

System PCB

FPGA

Config AER

BA

High-Density

Synapse Matrix with

Long Term Plasticity

Short Term Plasticity

AER Decoder

Short Term Plasticity

AER Decoder

AE

R D

ecoder

Routing, Topology

Configuration, Delays

Neuro

ns

Arb

iter

Multi-Output DAC,

Multiple Current BiasB

idirectional

AE

R Inte

rface

Sm

all

Config.&

Test

Inte

rface

Configura

ble

Pois

son

Genera

tors

Pulse

Communication

and Routing on

Chip and off Chip

Network

Stimulation

and Biasing

(Peripheral

Components)

Neuromorphic

Components

NeuroSoC in CMOS VLSI Biomimetic Network

(including Support System)


ASIC Design Lab• Common platform for chip design activities of chairs of Prof. Ellinger, Prof.

Schüffny and Prof. Fettweis

• Available technologies nodes:

- Austria-Microsystems (AMS) 0.35µm

- XFAB 0.35µm, 0.18µm

- UMC 0.18µm, 0.13µm, 90nm

15.07.2011 Slide 19

- UMC 0.18µm, 0.13µm, 90nm

- STM 65nm, 45nm

- IBM (Mosis)

- IHP (GaAs, by Prof. Ellinger, CCN)

- TSMC 65 nm

• Reusable design flow (ICPRO)

– Project and Design Flow Management System for Design and Verfication of Integrated Circuits

– used for all chip design project (analog, mixed-signal and digital)

– EDA tools of main vendors (Cadence, Synopsys, Mentor) are integrated

• High-capacity Compute Hardware

– Linux Compute Cluster (total 28 (2x)cores, 400GB Mem, 8TB storage)

Mixed Signal VLSI Design: Advanced Digital and ... · PDF fileNeuromorphic Circuits ......

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