MITSUBISHI SEMICONDUCTORS POWER MODULES MOS USING … IGBT … · structures of the IGBT, MOSFET...

Sep.1998

4.0 Using IGBT Modules

Mitsubishi IGBT modules aredesigned to be rugged, low lossand easy to use. Use of advancedprocessing technologies gives lowon-state saturation voltages whilemaintaining the high switchingspeed needed for 20kHz operation.The information presented in thissection is intended to help users ofMitsubishi IGBT modules apply thedevices effectively and reliably.

4.1 Structure and Operationof IGBT Module

The IGBT, Insulated Gate BipolarTransistor, is a switching transistorthat is controlled by voltageapplied to the gate terminal.Device operation and structure aresimilar to those of an InsulatedGate Field Effect Transistor, morecommonly known as a MOSFET.The principal difference betweenthe two device types is that theIGBT uses conductivity modulationto reduce on-state conductionlosses.

A brief comparison between thestructures of the IGBT, MOSFETand npn Bipolar JunctionTransistor (BJT) is depicted inFigure 4.1. The npn BJT is a threejunction device that requires acontinuous current flowing into thebase region to supply enoughcharges to allow the junctions toconduct current. Because theMOSFET and the IGBT arevoltage controlled devices, theyonly require voltage on the gate tomaintain conduction through thedevice. The IGBT has one junctionmore than the MOSFET, and this

Figure 4.1 Three Major Device Technologies

MITSUBISHI SEMICONDUCTORS POWER MODULES MOS

USING IGBT MODULES

B E

n+

p

n–

n+

C

SG

p

n–

n+

D

n+

SiO2

EG

p

n–

n+

C

n+

SiO2

p+

npn POWER BIPOLAR n-CHANNEL POWER MOSFET n-CHANNEL POWER IGBT

E

C

B

S

D

G

E

C

G

Low on-state drop conductivity modulation

Current control device, large drive power

Medium fast switching

High on-state drop for majority carrier condition

Voltage control drive, small drive power

Very fast switching

Medium on-state drop for conductivity modulation

Voltage control drive, small drive power

Fast switching

Advantage Disadvantage

Sep.1998

junction allows higher blockingvoltage and conductivitymodulation, as described below,during conduction. This additionaljunction in the IGBT does limitswitching frequency however.

4.1.1 Silicon Structure

The IGBT silicon structure is asshown in Figure 4.2. A positive volt-age on the gate attractselectrons from the “p” gate regiontowards the silicon surface underthe gate. These electrons invertthe “p” directly under the gate toform an “n” region, thus creating apath for charge flow between the“n” collector region and the “n”emitter region. A zero or negativevoltage (depends on the device)on the gate maintains the off-bias.

4.1.2 Device Operation

When the device is on, thecollector is at a higher voltage thanthe emitter, and therefore minoritycarriers are injected from thecollector p+ region into the

collector bulk region (n+ bufferlayer and collector “n” region). Thecharges reduce the collector bulkregion resistance and thuscollector to emitter voltage drop isreduced (relative to VDS(on) ofMOSFET).

When a positive gate voltage is firstapplied, a gate current flows untilthe gate capacitance is chargedand the gate voltage rises to the“on” level. When the gate voltage isremoved, the charges injected intothe collector bulk region must beremoved before high voltage canbe blocked.

The IGBT surface emitter pattern isstriped geometrically, in contrast tothe FET cell-based geometry. TheIGBT uses the same small featuresize advantages of the MOSFET,but the striped geometry offersmore ruggedness and immunityfrom latch-up of the parasitic thyris-tor shown in Figure 4.3A.

A circuit model of a typical IGBT isillustrated in Figure 4.3A. H-SeriesIGBTs use optimized buffer layer,p± well doping and alignments,gate structure, and surface patterndesigns. Minority carrier

lifetime control techniques are usedto reduce the gain of the “pnp” bi-polar element and minimize lateralRBE values, thus precluding latch-up. Therefore, the equivalent circuitmodel of a H-Series IGBTis reduced to the schematic in Fig-ure 4.3B.

4.1.3 Wafer Processing

IGBT wafer processing is similar toFET processing. The siliconmaterial is a dual epitaxialstructure, and gate and emitterregions are diffused and/or ionimplanted into the emitter side.Selective doping, electronicirradiation, and other processingtechniques are used duringemitter-side processing.

Many of the same processingtechniques used to fabricate FETdevices are employed in IGBTmanufacture. The high di/dt anddv/dt capabilities of the FETsresult from the control of minoritycarriers near the gate “p” regionand collector “n” region interface.The same techniques plus addi-tional steps to control carrier life-time near the collector N+ bufferregion help to generate immunityfrom latch-up and to enhance the

Figure 4.2 IGBT Cross Sectionand Silicon Structure

Figure 4.3 IGBT Internal Parasitics


USING IGBT MODULES

n+

p+

E

p+p+n+ n+

p pe

G

LG

n–

CHOLES

Rb

e

e ELECTRONS

RMOD

C

C E

G

RBE

RMOD

C

C E

G

RBE

A. MODEL OF CONVENTIONAL TYPE B. MODEL OF Mitsubishi RUGGED IGBT

VCE(sat) = VBE + IMOS • RMOD + IMOS • rDS(ON)

Sep.1998

switching ruggedness of H-SeriesIGBTs. Ultra clean facilities andin-line wafer testing promoteconsistent processing, thusensuring chips of the highestquality and reliability.

4.1.4 Module PackagingConstruction and Layout

IGBT modules consist of multipleIGBT chips mounted on anisolated substrate, which is itselfmounted on a heatsinking copperbase plate (Figure 4.4A).

Mitsubishi IGBT modules use anisolating ceramic substrate withcopper patterns metallurgiclybonded to the top and bottomsurfaces. (Figure 4.4B). Thismounting method allows highlyautomated module assembly while

minimizing thermal impedance.Mitsubishi IGBT modules usematerials with similar thermalcoefficients of expansion so thatthermal stress is limited. Thusthese IGBT modules can beexpected to provide improvedthermal cycle life over existingpower transistor modules.

Free-wheeling diodes are alsomounted in the module for easeof system assembly and to allowminimum lead inductance, bothinside and outside the module.Interconnection inside the modulesis accomplished with rigid bussingto ease assembly. Rigid bussingalso offers symmetric layout ofinternal components so theparasitic inductance is reducedand module ruggedness isenhanced.

4.1.5 Features of U-Series IGBTPackages

A new IGBT module packagecalled “U-Series” was developed byMitsubishi Electric in 1996. Thenew package technology achievesa significant reduction in internal in-ductance and improved reliabilityover older designs. The time re-quired to assemble the new mod-ule was substantially reduced byusing a special case that has thepower electrodes molded into itssides rather than inserted after thecase is molded. Figure 4.5 is across section drawing of the newIGBT module package. The mainelectrodes are connected directlyto the power chips using large di-ameter aluminum bonding wires. Inorder to help simplify power circuitand snubber designs or possiblyeliminate the need for snubbers al-together an effort was made tominimize the inductance of the newU-Series package. A variety oftechniques were used to reduceeach component of the package in-ductance. One of the most signifi-cant improvements was made pos-sible by the new insert moldedcase design. Wide electrodes aremolded into the side of the case toform parallel plate structures thathave considerably less inductance

Figure 4.5 Cross Section of U-Series Module PackageMAIN TERMINAL ELECTRODE

SILICONE GEL

COVER

INSERT MOLDED CASE

AIN SUBSTRATEPOWER CHIPSCU BASE PLATEAL BOND WIRES

CASE (EPOXY RESIN)

COMMON (C2E1)

EMITTER (E2)

COLLECTOR (C1)

GATE AND EMITTER (G1, E1, G2, E2)

EPOXY RESIN

SILICONE GEL

ALUMINUM WIRE

SILICON CHIPNEW INSULATING BASE (ALN ISOLATOR)

BASEPLATE

BASE

IGBT, FWD CHIPNEW INSULATING PLATE

INSULATION MATERIAL

COPPER

BASE

COLLECTOR PLATE

INSULATION PLATE

COPPER TERMINAL

SEMICONDUCTOR CHIP

(A) (B)

H-SERIES IGBT MODULE

CONVENTIONAL POWER MODULE

Figure 4.4 Structure of Mitsubishi IGBT Module and Module Base Plate Construction


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Sep.1998

than conventional electrodes. Inaddition, the strain relieving “S”bends that were needed in theelectrodes of conventional modulesare not needed in the U-Seriespackage because the aluminumbond wires perform the strain re-lieving function. Elimination ofthese “S” bends helped to furtherreduce the electrode inductance.Overall, as a result of these induc-tance reducing features the U-Se-ries modules typically have aboutone third the inductance of conven-tional modules. A further reductionin assembly time was achieved byreducing the number of solderingsteps during manufacturing. Withthe conventional module the chip tosubstrate and substrate to base

plate soldering is done first withhigh temperature solder. Then thecase is attached to the base plateand a second low temperature sol-dering step is used to connect thepower electrodes. In the new mod-ule the second step is not neededbecause the connectionsto the power electrodes are madeusing the aluminum bond wires.The soldering temperature of thechip and substrate attachment canbe reduced. The lower solderingtemperature minimizes the effectsof the mismatched coefficients ofexpansion between the base plateand the AlN DBC substrate. The re-sult is a reduction in thermal stressduring manufacturing and improvedpower cycle reliability.

4.2.1 Absolute Maximum RatingsSymbol Parameter Definition

VCES Collector-Emitter Blocking Voltage Maximum Off-state collector-emitter voltage with gate-emitter shorted

VGES Gate-Emitter Voltage Maximum gate-emitter voltage with collector-emitter shorted

IC Continuous Collector Current Maximum collector current – DC

ICM Peak Collector Current Repetitive Peak collector current, Tj ≤ 150°CIE Continuous Diode Current Maximum diode current – DC

IEM Peak Diode Current Repetitive Diode peak current, Tj ≤ 150°CPC Power Dissipation Maximum power dissipation, per device, TC = 25°CTj Junction Temperature Allowable range of IGBT junction temperature during operation

Viso Isolation Voltage Minimum RMS isolation voltage capability applied electric terminal to base plate,

1 minute duration

Mounting Torque Allowable tightening torque for terminal and mounting screws

4.2.2 Electrical CharacteristicsSymbol Parameter Definition

Static

ICES Collector-Emitter Leakage Current IC at VCE = VCES, VGE = 0, gate-emitter shorted, Tj = 25°CIGES Gate-Emitter Leakage Current IG at VGE = VGES, VCE = 0, collector-emitter shorted, Tj = 25°CVGE(th) Gate-Emitter Threshold Voltage VGE at IC = specified mA, VCE = 10V

VCE(sat) Collector-Emitter Saturation Voltage VCE at IC = rated IC and VGE = 15V

QG Total Gate Charge Charge on gate at VCC - 0.5~0.6VCES, rated, IC = rated IC, VGE = 15V

VEC Emitter-collector voltage Diode voltage at IE = -rated IC, VGE = 0V

Dynamic

Cies Input Capacitance Gate-emitter capacitance with VCE = 10V

Coes Output Capacitance Collector-emitter capacitance with the gate shorted to the emitter

Cres Reverse Transfer Capacitance Gate-collector capacitance with the emitter connected to the guard terminal of

the impedance analyzer

4.2 IGBT Module Ratingsand Characteristics

The ratings as shown inSection 4.2 are most importantfor IGBT's operation andenvironment. A maximum ratingis a value which establishes eithera limiting capability or limitingcondition (either maximum orminimum). It is determined for aspecified value of environmentand operation. Therefore, youcannot use the IGBT modulebeyond its maximum or minimumrating's value.


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Sep.1998

4.2.4 Test Circuits andConditions

The following test circuits are usedto evaluate IGBT characteristics.

1. VCE(sat) and VECTo ensure specified junctiontemperature, Tj,measurements of VCE (sat)

VCC

CURRENT MONITOR

VGE

L

D.U.T.

Irr

t

IC

t

IE

IE

Irr

trr

IE

0.5 IrrQrr = 1/2 Irr trr

+VGE1

-VGE2

E

C

V ICVGE

RG

E

C

V IC

+VGE1

-VGE2

RG

lC

RLOAD

VCC

Figure 4.6 Reverse Recovery Measurement Circuit and Waveform Figure 4.7 V CE (sat) Test

Figure 4.8 V CE Test

Figure 4.9 Resistive LoadSwitching Test Circuit

4.2.2 Electrical Characteristics (Continued)Symbol Parameter Definition

Dynamic (Continued)

td(on) Turn-on Delay Time Time from VGE = 0V to IC = 10% of final value

tr Rise Time Time from IC = 10% of final value to IC = 90% of final value

td(off) Turn-off Delay Time Time from VGE = 90% of initial value to IC = 90% of initial value

tf Fall Time Time from IC = 90% of initial value to IC = 10% of initial value

trr Diode Reverse Recovery Time Time from IC = 0A to projection of zero IC from Irr and 0.5 Irr points with

IE = -rated IC and at specified di/dt (Refer to Figure 4.6)

Qrr Diode Reverse Recovery Charge Area under Irr curve from IC = 0A to projection of zero IC from Irr and

0.5x Irr points with IE = rated IC and at specified di/dt (Refer to Figure 4.6)

4.2.3 Thermal Characteristics

Symbol Parameter Definition

Rth(j-c) Thermal Resistance, Junction to Case (Tj - TC)/(IC-X VCE), IC conducting to establish thermal equilibrium

Rth(c-f) Thermal Resistance, Case to fin (TC - Tf)/(IC X VCE), IC conducting to establish thermal equilibrium lubricated

and VEC must be performedas low duty factor pulsed tests.(See Figures 4.7 and 4.8)

2. Resistive Load Switching TestCircuit. (See Figure 4.9)

3. Half-Bridge Switching TestCircuit (See Figure 4.10)


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Sep.1998

4.3 Safe Operation Area

Protecting IGBTs againstdisturbance caused by overcurrents or over voltage is animportant design topic in mostswitching applications. In the caseof all hard switching applications,such as inverter or chopper circuitsfor motor controls and transformerloads, the turn-off switching SOAand short circuit capability are thetwo most important ratings ofIGBTs today.

4.3.1 The Turn-off SwitchingSOA of IGBT

The turn-off switching SOA is simi-lar to RB SOA (Reverse Bias SOA)of Darlington transistors.The switching operation for atypical inverter bridge circuit(Figure 4.11) will generate thecurrent and voltage waveformillustrated in Figure 4.12. Inturning off an inductive loadcurrent, the voltage rise precedesthe current fall. As the gatevoltage reduces below itsthreshold value, the intrastructural

MOSFET channel window getsblocked and injection of electronscease. Removal of the storedminority carriers (holes) in the“n” base region starts, and duringthis interval, the parasitic widebase pnp transistor operated by vir-tue of its current gaincharacteristics causing thecollector current to continueflowing. Thus, the later part of theIGBT turn-off fall current, is mainlydue to the hole current. Some ofthe holes in the “n” base regioncontinues to cross through theC-B junction of the parasitic npntransistor and travel horizontallybelow the “n” emitter layer.(Figure 4.13)

This flow of holes causes apotential drop across the “p” bodyresistance, RD, and tends toactivate the npn transistor. Aturn on of the npn transistor,while the pnp transistor is stillactive, can lead to pnp thyristorlatch-up, which means loss ofgate control and, eventually,destruction of the device. Thisproblem has been eliminated in

the Mitsubishi IGBTs by carefuloptimization of the devicegeometry.

The Switching SOA curve is thelocus of points defining themaximum allowable simultaneousoccurrence of collector current andcollector to emitter voltage duringturn-off. Figure 4.14 shows thatH-Series IGBTs offer squareswitching SOA for 600V and1200V devices at 2X rated current.

The curves show that independentof VCE, the device current mustbe kept below 200% ratedcurrent. This limit is due to thedesigned current density of thechips and internal connections inthe module.

VGE

0

lC

0

90%

90%

10%

t

t

td(on) trtd(off)

tf

Figure 4.10 Switching TimeWaveform

+VGE1

-VGE2

RG

VCClE

lC

SHORT

Figure 4.11 Half-Bridge Switching Test Circuit


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Sep.1998

4.3.2 Short Circuit SOA

Most power conversionapplications require that theapplied switch should survivea short circuit on the systemoutput without any damage.When considering short circuitwithstand capability of IGBTmodules, two distinguishingcases are generally reviewed:

Case-1 – Switching on of anIGBT into a short circuit,

Case-2 – Load or groundfaultshort-circuit across aswitched on IGBT.

Figure 4.15 shows the circuitryand waveforms for each case.

In Case-1, as the IGBT turnson, initial rate of rise of IC isdetermined by the wiringinductance, L. Also, the voltage,VCE, drops to some value belowVCC as the L discharges. Soonafter this, VCE switches back toalmost full VCC level. The dv/dt atthis switch back is coupled to thegate through the reverse transfercapacitance thus causing amomentary rise of gatevoltage.This extra gate voltagemobilizes more electron and holeplasma within the IGBT modulestructure. The effect of thistranslates to a higher peakcollector current within a couple ofmicroseconds. The circuit design(e.g. layout, bias condition,selection of RG, maximum supplyvoltage, etc.) is important tolimit the short circuit currentmagnitude in this high injectionstate. Due to high current density

Figure 4.12 Switching Waveforms (Half-Bridge Mode)

TURN-ON 50A/div 100V/div 50ns/div

TVCE IC

VCEICO

RG=3.9 ohm

T

T

T

TURN-OFF 50A/div 100V/div 50ns/div

EMITTER GATE

COLLECTOR

RB

HOLEN°

N°

P°

P

e

N°

Figure 4.14 Turn-off Switching SOA

COLLECTOR-EMITTER VOLTAGE (VOLTS)

0 200 400 600 800 1000 CO

LLE

CT

OR

CU

RR

EN

T, I

C, (

NO

RM

ALI

ZE

D T

O M

OD

ULE

RA

TIN

G)

1X

01400

LIMIT FOR 600V

CLASS (-12H)

LIMIT FOR 250V

CLASS (-5F)

CONDITIONS: Tj = 25∼125°C VGE = ±15V RG = VCC ≤

2X

1200

LIMIT FOR 1200V CLASS

(-24H)LIMIT FOR 1700V CLASS (-34H)

SEE TABLE 4.2 RECOMMENDED RANGE 150V (5F) 400V (12H) 800V (24H) 1000V(28H) 1100V (34H)

1600

LIMIT FOR 1400V CLASS (-28H)

Figure 4.13 High Injection On-state Electron and Hole Currentswithin an IGBT Structure


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Sep.1998

within the silicon, the internaltemperature rises and it causes thehigh short circuit peak current to re-duce to a lower value which corre-sponds to what is called a satura-tion current. To protect the devicefrom destruction, thecurrent has to be cut off within aspecified period, which is normallyspecified by the input gate pulsewidth, tw. At turn off, a sharp fall ofcollector current in the presence ofthe wiring inductance, L1, causesVCE to shoot up by an amountequivalent to:

∆VCE ≈ L1 X diC/dt.

The instantaneous value ofcollector-emitter voltage, VCE,including this surge peak valuemust not be allowed to go beyondthe specified voltage limit given by

SCSOA. (See Figures 4.16, 4.17,4.18, 4.19, and 4.20)

In Case-2 short circuit an externalshort circuit occurs while the IGBTis already in the on state. (SeeFigure 4.15B) The increasing shortcircuit forces the IGBT chip todesaturate causing the collector-emitter voltage to rise fromVCE(sat) to almost full VCC. Thedv/dt during IGBT desaturationmay be higher compared toCase-1 and is coupled backthrough the reverse transfercapacitance, which is now higher atthe low on-state voltage, and mayresult in a higher momentary rise ofgate voltage. As a result the magni-tude of the short circuit in Case-2can reach significantly higher val-ues than in Case-1.

In Figures 4.16, 4.17, 4.18, 4.19,and 4.20 the short circuit self limita-tion in Case-1 is shown asthe dark area. Careful precautionsmust be considered in Case-2 toprevent the short circuit currentmagnitude going beyond a magni-tude of ten times the rated currentas an absolute limit (shaded areain Figures 4.16, 4.17, 4.18, 4.19,and 4.20).

Cautions:1. SCSOA is valid for gate pulse

width, tW, ≤ 10µs2. SCSOA is a non-repetitive

capability. H-Series IGBTmodules can survive up to 100short circuit events on anon-repetitive basis over thelife of the equipment.

Figure 4.15 Cases of Short-Circuit

lC

VCC

RG

LI

VCE

C

E

G

VCC

VCE

VCE(pk)

VCE

IC

ICP

IGBT TURN-ON

tw

IC(off)

t

dv/dt

lC

Q1 (on)

L11

C

E

G

VCC

VGE

(OFF)

Q4 (on)SHORT

L12

(OFF)

VCC

IC

ICP

LOAD SHORTED

tw

IC(off)

VGE

VCE(pk)

dv/dt

Q1 ON STATE

ÆVCE

(A) CASE-1

SHORT-CIRCUIT

(B) CASE-2

SHORT-CIRCUIT


USING IGBT MODULES

Sep.1998

4.4 Performance Curves

The characteristic curves showtypical electrical characteristics andmaximum transient thermal imped-ance characteristics of the IGBTand FWDi.

4.4.1 Output Characteristics

The output characteristics(Figure 4.21) define the value ofVCE that the IGBT will have whenconducting a given IC for a givenvalue of VGE. The IGBT isintended for switching operationonly and the range for practicaluse is limited to the range of VCEwithin the saturation area.

4.4.2 Collector-Emitter Saturation Voltage

VCE(sat) is a function of junctiontemperature, collector current, andgate-emitter voltage. VCE(sat) of

COLLECTOR-EMITTER VOLTAGE, VCE, (VOLTS)

0 100 200 300 400 500

CO

LLE

CT

OR

CU

RR

EN

T, I

C, (

NO

RM

ALI

ZE

D)

10X

9X

8X

7X

6X

5X

4X

3X

2X

1X

0600

600V CLASS

CONDITIONS: VCC ≤ 400V Tj = 25∼125°C VGE = ±15V tw = 10µs RG = SEE TABLE 4.2

RECOMMENDED RANGE

Figure 4.16 Short-Circuit SOAfor Modules 600VClass


0 200 400 600 800 1000

CO

LLE

CT

OR

CU

RR

EN

T, I

C, (

NO

RM

ALI

ZE

D)

10X

9X

8X

7X

6X

5X

4X

3X

2X

1X

01200

1200V CLASS

CONDITIONS: VCC ≤ 800V Tj = 25∼125°C VGE = ±15V tw = 10µs RG = SEE TABLE 4.2

RECOMMENDED RANGE

Figure 4.17 Short-Circuit SOAfor Modules 1200VClass


0 200 400 600 800 1000

CO

LLE

CT

OR

CU

RR

EN

T

X

100

(%)

10X

9X

8X

7X

6X

5X

4X

3X

2X

1X

01200

1400V CLASS

CONDITIONS: VCC ≤ 1000V Tj = 25∼125°C VGE = ±15V tw ≤ 10µs RG = SEE TABLE 4.2

RECOMMENDED RANGE

I C(S

HO

RT

)

I C(R

AT

ED

)

Figure 4.18 Short-Circuit SOAfor 1400V Modules

Figure 4.19


0 500 1000 1500

CO

LLE

CT

OR

CU

RR

EN

T

X 1

00 (

%)

10X

9X

8X

7X

6X

5X

4X

3X

2X

1X

0

IGBT MODULE SCSOA 1700V CLASS

I C (

SH

OR

T)

I C (

RA

TE

D)

CONDITIONS: VCC ≤ 1100V Tj = 25∼125°C VGE = ±15V tw ² 10µs RG = RECOMMENDED

RANGE

CO

LLE

CT

OR

CU

RR

EN

T

X 1

00 (

%)

IGBT MODULE SCSOA 250V CLASS

I C (

SH

OR

T)

I C (

RA

TE

D)


0 50 100 150 200

10X

9X

8X

7X

6X

5X

4X

3X

2X

1X

0250

CONDITIONS: VCC ≤ 100V Tj = 25∼125°C VGE ² ±10V tw = 10µs

RECOMMENDED RANGE

RG = R

Figure 4.20


USING IGBT MODULES

Sep.1998

H-Series IGBTs decreases at lowIC with increasing temperature, thatis, it has a negative temperaturecoefficient, whereas, after exceed-ing the crossover point the tem-perature coefficient becomes posi-tive.

Figures 4.22 and 4.23 showtypical collector-emitter saturationvoltage characteristics, VCE(sat)versus IC, and VCE(sat) versusVGE respectively.

4.4.3 Device Capacitance

As the IGBT is a MOS gatedevice, it has three characteristiccapacitances Cies, Coes, andCres. These capacitances arespecified in the data sheetbecause they are the most readilymeasured. They can be usedto determine the IGBT junctionand diffusion physicalcapacitance, CGE, CGC, andCCE, by the formula given inTable 4.1 All three specifiedcapacitances are small duringdevice off state, but the largediffusion capacitance portion ofthe gate-collector capacitance


CO

LLE

CT

OR

CU

RR

EN

T, I

C, (

AM

PE

RE

S)

OUTPUT CHARACTERISTICS (TYPICAL)

200

0 2 4 6 8 10

160

120

80

40

0

Tj = 25°C

12

10 9

7

6

5

8

15VGE = 20V

Figure 4.21

COLLECTOR-CURRENT, IC, (AMPERES)

CO

LLE

CT

OR

-EM

ITT

ER

S

AT

UR

AT

ION

VO

LTA

GE

, VC

E(s

at),

(VO

LTS

)

COLLECTOR-EMITTER SATURATION VOLTAGE CHARACTERISTICS

(TYPICAL)

5

0 160 320 480 640 800

4

3

2

1

0

VGE = 15V Tj = 25°C

Tj = 125°C

GATE-EMITTER VOLTAGE, VGE, (VOLTS)

CO

LLE

CT

OR

-EM

ITT

ER

S

AT

UR

AT

ION

VO

LTA

GE

, VC

E(s

at),

(VO

LTS

)

COLLECTOR-EMITTER SATURATION VOLTAGE CHARACTERISTICS

(TYPICAL)

10

0 4 8 12 16 20

8

6

4

2

0

Tj = 25°C

IC =160A

IC = 800A

IC = 400A

Figure 4.22

Figure 4.23

causes them to increasedramatically during low collector-emitter states. (Figure 4.25) Inputcapacitance curves are drawn forVGE = 0V.

Table 4.1Cies = CGE + CGC (in parallel)

(measured C-E shorted)Coes = CCE + CGC

(measured G-E shorted)Cres = CGC

4.4.4 Gate Charge

Since input capacitance varieswith VCE voltage, anotherparameter is used to better specifythe energy required to turn on andoff the IGBT, the gate charge, QGcharacteristic. The “QG vs. VGE”curve shows the charge necessaryto switch the IGBT. The first slopecorresponds to the charging of theinput capacitance while VCEequals VCC. When the VGE(th) isachieved, the collector current, IC,causes the VCE to decrease to-wards VCE(sat). During the VCEfall the CGC capacitance increasesrapidly and prevents the increaseof VGE as it draws more charge.

RB

n+

p+

E

p+p+n+ n+

p pe e

G

LG

n–

C

Figure 4.24 IGBT DeviceCapacitances


CA

PA

CIT

AN

CE

, Cie

s, C

oes,

Cre

s, (

pF)

CAPACITANCE VS. VCE (TYPICAL)

10-1 100 102

105

104

103

102101

Cies

Coes

Cres

Figure 4.25 Typical IGBTCapacitances


USING IGBT MODULES

Sep.1998

When VCE stabilizes, the input ca-pacitance also stabilizes and theadditional charge increases theVGE voltage up to the full on level.At turn off the same charge quan-tity must be extracted.

4.4.5 SwitchingCharacteristics

While the switching times given onthe data sheets as electricalcharacteristics are for resistiveload switching, the performancecurves are for half-bridge inductive

Figure 4.27 Measurement Circuit and Waveforms of Switching Time

Figure 4.28 Half-Bridge Switching Test (Inductive Load)

+VGE1

-VGE2

RG

VCClE

lC

LShort

COLLECTOR CURRENT, IC, (AMPERES)

SW

ITC

HIN

G T

IME

, (ns

)

HALF-BRIDGE SWITCHING CHARACTERISTICS

(TYPICAL)

103

101 102 103

102

101

td(off) tf td(on)

tr

VCC = 600V VGE = ±15V RG = 1.6Ω Tj = 125°C

(A) HALF-BRIDGE SWITCHING TEST CIRCUIT

(B)

GATE CHARGE, QG, (nC)

GA

TE

-EM

ITT

ER

VO

LTA

GE

, VG

E, (

VO

LTS

)

GATE CHARGE, VGE

20

0 500 1000 1500 2000 2500

16

12

8

4

0

IC = 400A

VCC = 300V

VCC = 200V

Figure 4.26 Typical GateCharge

+VGE1

-VGE2

RG

lC

RLOAD

VCC

VGE

0

lC

0

90%

90%

10%

t

t

td(on) trtd(off)

tf

(A) RESISTIVE LOAD SWITCHING TEST CIRCUIT

(B) SWITCHING TEST TIME WAVEFORMS

load. (See Figure 4.28) Thisreflects the fact that inductiveloads are the most prevalentapplication for IGBTs. Theswitching times are defined inFigure 4.27B with ton = td(on) + trand toff = td(off) + tf. The turn-ondelay time, td(on), is the timerequired to attract excesselectrons to the region justunderneath the gate. The risetime, tr, is the time required forcollector current to increase from10% of its final value to 90% of itsfinal value. Rise time is basicallylimited by gate impedance charac-teristics, which are partially a func-tion of the gate contact geometryand partially a function of the inputcapacitances discussed previously.The turn-off delay time, td(off) isdue to gate capacitance limitingcharges from leaving the under-gate area. Since charges are notrequired to leave the actual siliconcrystal, as is the case with bipolardevices, turn-off delay time of anIGBT is considerably shorter thanthe storage time of bipolar devices.The fall time, tf, is not limited by de-vice capacitance. It includes thetime necessary for recombinationof excess charges stored in the n-bulk (tail period).

4.4.6 FWDi Characteristics

Characteristics of the diode partare shown in Figures 4.29 and4.30. The diode part means thefree-wheeling diode (FWDi)anti-parallel to the IGBT.

Figure 4.29 shows the voltage dropbetween anode and cathode whena forward current is supplied to theFWDi.


USING IGBT MODULES

Sep.1998

Typical reverse recoverycharacteristics of the FWDi areshown in Figure 4.30. Thesemeasurements are made using acircuit which operates as ahalf-bridge with inductive load.(Figure 4.28A) The low values oftrr and Irr and their relativeindependence of forward currentare a unique feature of the FWDiused in H-Series IGBT modules.

4.4.7 Transient ThermalImpedance

The transient thermal impedance,Zth(j-c) gives the rise of junctiontemperature over case

temperature per unit of powerapplied for a given time period.(See Figures 4.31 and 4.32) Thevalue of Zth(j-c) is obtained bymultiplying the value of Rth(j-c) bythe normalized factor taken fromthe curve at the time of interest.The steady state thermalresistance, Rth(j-c) is thesaturated value of Zth(j-c). If thisvalue is smaller, the maximumallowable power loss, PC, of adevice becomes larger:

Tj(max) – TCPC =

Rth(j-c)

4.4.8 Switching Energy Charac-teristics

Switching energy curves are pro-vided in order to simplify estimationof switching losses.Use of these curves is describedin more detail in Section 3.4.1 ofthis application data. Figures 4.33through 4.41 show turn-on andturn-off switching energy as a func-tion of collector current forMitsubishi 250V, 600V, 1200V,1700V H-Series and U-SeriesIGBT modules. Figures 4.42 and4.43 show switching loss versusseries gate resistance for U-SeriesIGBT modules.

4.5 IGBT Selection

Proper selection of an IGBTinvolves two key points. Both arerelated to keeping the IGBTwithin its maximum ratings duringoperation. The first criterion is thatthe peak collector current duringoperation including any requiredoverload current must be within theSWSOA (this means < 2 x Irated or2 x nameplate current). Thesuggested IGBT selections inSections 2.3, 2.4, and 2.5 arebased on a 200% overloadrequirement and allow 20% forripple current factors indetermining the peak IGBT currentrequirement for the inverter. Thesecond criterion is that the IGBToperating junction temperaturemust always be kept below Tj(max)(150°C) in all normal operation in-cluding expected motor overload.Power dissipation and thermal de-sign considerations are discussedin detail in Section 3.4. Modulesselected for listing inSections 2.3, 2.4, and 2.5 willmeet these requirements withnormal environmental and

TIME, (s)

NO

RM

ALI

ZE

D T

RA

NS

IEN

T T

HE

RM

AL

IMP

ED

AN

CE

, Zth

(j-c

) Z

th =

Rth

• (

NO

RM

ALI

ZE

D V

ALU

E)

TRANSIENT THERMAL IMPEDANCE CHARACTERISTICS

(IGBT)

101

10-5 10-4 10-3

100

10-1

10-2

10-3

10-3 10-2 10-1 100 101

Single Pulse TC = 25°C Per Unit Base = Rth(j-c) = 0.08°C/W

10-1

10-2

10-3

TIME, (s)

NO

RM

ALI

ZE

D T

RA

NS

IEN

T T

HE

RM

AL

IMP

ED

AN

CE

, Zth

(j-c

) Z

th =

Rth

• (

NO

RM

ALI

ZE

D V

ALU

E)

TRANSIENT THERMAL IMPEDANCE CHARACTERISTICS

(FWDi)

101

10-5 10-4 10-3

100

10-1

10-2

10-3

10-3 10-2 10-1 100 101

Single Pulse TC = 25°C Per Unit Base = Rth(j-c) = 0.18°C/W

10-1

10-2

10-3

Figure 4.31 Figure 4.32

0.8 1.2 1.6 2.0 2.4 2.8101

EMITTER-COLLECTOR VOLTAGE, VEC, (VOLTS)

FREE-WHEEL DIODE FORWARD CHARACTERISTICS

(TYPICAL)

102

103

NE

GA

TIV

E C

OLL

EC

TO

R-C

UR

RE

NT

, -I C

, (A

MP

ER

ES

)

Tj = 25°C

Figure 4.29

EMITTER CURRENT, IE, (AMPERES)

RE

VE

RS

E R

EC

OV

ER

Y T

IME

, trr

, (ns

)

REVERSE RECOVERY CHARACTERISTICS (TYPICAL)

103

101 102 103

102

101

trr

Irr

di/dt = -800A/µsec

102

101

100 RE

VE

RS

E R

EC

OV

ER

Y C

UR

RE

NT

, Irr

, (A

MP

ER

ES

)

Figure 4.30


USING IGBT MODULES

Sep.1998


USING IGBT MODULES

10-2

COLLECTOR CURRENT, IC (AMPERES)

SWITCHING ENERGY 600V CLASS H-SERIES IGBT MODULE

TU

RN

-ON

SW

ITC

HIN

G, E

SW

(m

J/P

ULS

E)

10-1

100

101

101 102

CM50-600**-12H IC = Ir/10~Ir FOR EACH MODULE

CM

-50*

*-12

H

CM

-150

**-1

2H

CM

-200

**-1

2H

CM

-300

**-1

2H

CONDITIONS: HALF-BRIDGE SWITCHING MODE Tj = 125°C VCC = 300V VGE = ±15V RG = 625/Ir

TURN-ON

CM

-400

**-1

2H

TURN-OFF

CM

-75*

*-12

H

CM

-100

**-1

2H

10-1

100

101

102

TU

RN

-OF

F S

WIT

CH

ING

, ES

W (

mJ/

PU

LSE

)

CM

-600

**-1

2H





TU

RN

-ON

SW

ITC

HIN

G, E

SW

(m

J/P

ULS

E)

10-1

100

101

102

101 102

CM

50**

-24H

CM

75**

-24H C

M15

0**-

24H

CM

200*

*-24

H

CM

300*

*-24

H

CONDITIONS: Tj = 125°C VCC = 600V VGE = ±15V RG = 313/Ir CM600HA-24H : RG = 2.1Ω

TURN-ON

TURN-OFF

103

100

101

102

TU

RN

-OF

F S

WIT

CH

ING

, ES

W (

mJ/

PU

LSE

)

CM

100*

*-24

H

CM

400*

*-24

H

CM

600*

*-24

H

CM

50**

-24H

CM

75**

-24H

CM

150*

*-24

H

CM

200*

*-24

H

CM

300*

*-24

H

CM

100*

*-24

H

CM

400*

*-24

H

CM

600*

*-24

H



TU

RN

-ON

SW

ITC

HIN

G, E

SW

(m

J/P

ULS

E)

10-2

10-1

100

101

100 101

CM

15T

F-2

4H CM

30T

F-2

4H


TURN-ON

TURN-OFF

102

10-1

100

101

TU

RN

-OF

F S

WIT

CH

ING

, ES

W (

mJ/

PU

LSE

)

CM

20T

F-2

4H

CM

15T

F-2

4H

CM

30T

F-2

4H

CM

20T

F-2

4H

10-3



TU

RN

-ON

SW

ITC

HIN

G, E

SW

(m

J/P

ULS

E)

10-2

10-1

100

100 101

CM15/20/30TF*-12H IC = Ir/10~Ir FOR EACH MODULE

CM

15T

F*-

12H

TURN-ON

CM

20T

F*-

12H

TURN-OFF

10-2

10-1

100

101

TU

RN

-OF

F S

WIT

CH

ING

, ES

W (

mJ/

PU

LSE

)

CM

30T

F*-

12H


Sep.1998


USING IGBT MODULES

101


TU

RN

-ON

SW

ITC

HIN

G, E

SW

(m

J/P

ULS

E)

TU

RN

-OF

F S

WIT

CH

ING

, ES

W (

mJ/

PU

LSE

)

102

102 103

CONDITIONS: Tj = 125°C VCC = 600V VGE = ±15V RG = 3.3Ω

TURN-ON

TURN-OFF

CM1000HA-24H

101

102

10-2


TU

RN

-ON

SW

ITC

HIN

G, E

SW

(m

J/P

ULS

E)

10-1

100

101

102

102 103

CONDITIONS: Tj = 125°C VCC = 100V VGE = ±10V RG = 2500/Ir

TURN-ON

TURN-OFF

103

10-1

100

101

102

TU

RN

-OF

F S

WIT

CH

ING

, ES

W (

mJ/

PU

LSE

)

CM

350D

U-5

F

CM

450H

A-5

F

CM

600H

A-5

F

CM

350D

U-5

F

CM

450H

A-5

F

CM

600H

A-5

F

100100

COLLECTOR CURRENT, I C (AMPERES)

TU

RN

-ON

SW

ITC

HIN

G, E

SW

(m

J/P

ULS

E)

101

102

101 102 103

CONDITIONS: Tj = 125°C VCC = 800V VGE = ±15V RG = 312/Ir CM600HA-28H: RG = 2.1Ω CM1000HA-28H: RG = 3.3Ω

TURN-ON

TURN-OFF

CM

50**

-28H

CM

75**

-28H

CM

100T

F-2

8H CM

200D

Y-2

8H

CM

300D

Y-2

8H

CM

400H

A-2

8H

CM

600H

A-2

8H

CM

1000

HA

-28H

CM50~1000-28H (IC = Ir /10~Ir)

Figure 4.37

Figure 4.39

Figure 4.38SWITCHING ENERGY

1200V CLASS H-SERIES IGBT MODULESWITCHING ENERGY

250V CLASS H-SERIES IGBT MODULE


101

102

100

TU

RN

-OF

F S

WIT

CH

ING

, ES

W (

mJ/

PU

LSE

)

Sep.1998

Figure 4.40


Figure 4.41

10-1


TU

RN

-ON

SW

ITC

HIN

G ,

ES

W (

mJ/

PU

LSE

)

100

101

101 102


SWITCHING ENERGY 600V CLASS U-SERIES IGBT MODULE

CM

150T

U-1

2H

CM

200T

U-1

2H

CM

300D

U-1

2H

CM

400D

U-1

2H

CM

600H

U-1

2H

CM

150T

U-1

2H

CM

200T

U-1

2H

CM

300D

U-1

2H

CM

400D

U-1

2H

CM

600H

U-1

2H

CM

100T

U/B

U-1

2H

CM

75T

U/B

U-1

2H

CM

100T

U/B

U-1

2H

TURN-ON

TURN-OFF

100

101

10-1

TU

RN

-OF

F S

WIT

CH

ING

, ES

W (

mJ/

PU

LSE

)


TU

RN

-ON

SW

ITC

HIN

G, E

SW

(m

J/P

ULS

E)

100

101

102

101 102

CONDITIONS: HALF-BRIDGE SWITCHING MODE Tj = 125°C VCC = 600V VGE = ±15V RG = 312.5/Ir CM600HU-24H: RG = 2.1Ω


TURN-ON

TURN-OFF

CM

50T

U-2

4H

CM

75T

U-2

4H

CM

100T

U-2

4H

CM

150D

U-2

4H

CM

200D

U-2

4H

CM

300D

U-2

4H

CM

50T

U-2

4H

CM

75T

U-2

4H

CM

100T

U-2

4H

CM

150D

U-2

4H

CM

200D

U-2

4H

CM

300D

U-2

4H

CM

400H

U-2

4H

CM

600H

U-2

4H

CM400HU-24H

CM600HU-24H

100

101

102

TU

RN

-OF

F S

WIT

CH

ING

, ES

W (

mJ/

PU

LSE

)

10-1

GATE-RESISTANCE, RG (Ω)

TU

RN

-ON

SW

ITC

HIN

G, E

SW

(m

J/P

ULS

E)

100

101

101

102

100 101

CONDITIONS: Tj = 125°C VCC = 300V VGE = ±15V IC = Ir

CM

-75*

U-1

2H

CM

-100

*U-1

2H

CM

-150

*U-1

2H

100

TU

RN

-OF

F S

WIT

CH

ING

, ES

W (

mJ/

PU

LSE

)

TURN-ON

TURN-OFF

CM600HU-12H

CM600HU-12H

CM400DU-12H

CM400DU-12H

CM300DU-12H

CM300DU-12H

CM200*U-12H

CM200*U-12H

CM150*U-12H

CM100*U-12H

CM75*U-12H


GATE RESISTANCE, RG (Ω)


TU

RN

-ON

SW

ITC

HIN

G, E

SW

(m

J/P

ULS

E)

100

101

102

103

100 101

CONDITIONS: Tj = 125°C VCC = 600V VGE = ±15V IC = Ir

104

101

102

103

TU

RN

-OF

F S

WIT

CH

ING

, ES

W (

mJ/

PU

LSE

)

CM600HU-24H

CM600HU-24H

CM400HU-24H

CM400HU-24H

CM300DU-24H

CM300DU-24H

CM200DU-24H

CM200DU-24H

CM150DU-24H

CM150DU-24H

CM50*U-24H

CM50*U-24H

CM75*U-24H

CM75*U-24H

CM100*U-24H

CM100*U-24H

TURN-OFF

TURN-ON


USING IGBT MODULES

Sep.1998

heatsink considerations. It maybe possible (or required) to use alower (higher) current rated ifmore (or less) efficient coolingis employed.

4.6 IGBT Module Gate Drive

IGBTs require gate voltage toestablish collector to emitterconduction. This gate voltage canbe applied by a variety of drivecircuits. The parameters to beconsidered in selecting a drivecircuit include device off biasingrequirements, gate chargerequirements, ruggednessrequirements and power supplyavailability.

A recommended drive circuitincludes substantial on biasingand off biasing. Such a circuit isshown in Figure 4.44. The IGBTgate-emitter impedance is largeenough that turn-on can beaccomplished with MOSFET drivetechniques, but as the IGBT inputcapacitance is larger than for aMOSFET the IGBT turn-off biasshould be stronger than manyMOSFET drives offer.

4.6.1 Gate Drive Voltage

For turn-on a positive gatevoltage of 15V ±10% isrecommended. This value issufficiently high to fully saturate theIGBT and minimize on-state losseswhile it is sufficiently low to limitshort circuit current and itsresulting power stress. In no caseshould a gate drive outside of therange of 12 to 20V be used forturn-on.

An IGBT will be off when its gatevoltage is zero. However, in orderto ensure that the IGBT stays in

its off state when dv/dt noise ispresent in the collector-emittervoltage an off bias must be used.Use of reverse bias also decreasesturn off losses. The relationshipbetween reverse bias voltage andswitching losses is shown inFigure 4.45. For H-Series IGBTsan off bias of -5 to -15V is recom-mended.

H-Series IGBT modules are notsuitable for linear operation. Gatevoltages in the 3 to 11V rangeshould only appear on the IGBT’sgate during rapid switchingtransitions.

4.6.2 RG - Series Gate Resistance

Selecting the proper series gate re-sistor for IGBT gate drive is veryimportant. The value of the gateresistor has a significant impact onthe dynamic performance of theIGBT. The IGBT is turned on andoff by charging and discharging thegate capacitance. A smaller gateresistor will charge/discharge thegate capacitance faster, reducingthe switching times and switchinglosses. Figures 4.46 and 4.47depict the typical dependence ofswitching times and losses on thevalue of the series gate resistor.

Under short circuit or during turn offof the free-wheeling diode acrossan IGBT, the dv/dt applied to theIGBT and its collector to gate ca-pacitance can cause acurrent to flow in the gate circuit. Ifthis current is large enough thevoltage developed across thegate resistor can cause the IGBT toturn on. So, while smaller gate re-sistances offer enhancedruggedness (rejection of dv/dtturn on), they also provide less

margin for noise and can lead tooscillation problems in conjunctionwith the gate-emitter capacitanceand any parasitic inductance in thegate drive wiring.

In addition, smaller gate resistorsallow faster turn-on di/dt of theIGBT. This may cause high dv/dtand increased surge voltage atFWDi recovery.

Giving consideration to all of theabove effects, Table 4.2 gives therecommended values of seriesgate resistance. The value givenfor the minimum series gate resis-

VG

+VGE

–VGE

Q1

Q2

RG

18V

Q1, Q2: VCEO ≥50V IC, Max. ≥

RG: See Table 4.2 or data sheet for suggested value

RG

VGE + + VGE

-

Figure 4.44 Typical IGBT GateDrive Circuit

0101

GATE REVERSE BIAS VOLTAGE, -VGE, (VOLTS)

SW

ITC

HIN

TG

LO

SS

, ES

W (

mJ/

PU

LSE

)

102

103

4 8 12 16 20

Esw(off)

Esw(on)

CONDITIONS: HALF-BRIDGE INDUCTIVE LOAD SWITCHING OPERATION Tj = 125oC VCC = 300V VGE = ±15V IC = 300A

Figure 4.45 Switching Energyas a Function ofReverse-BiasVoltage


USING IGBT MODULES

Sep.1998

tor is the standard resistor that isused for determining all data sheetparameters and characteristics.The maximum value given allowsfor flexibility in slowing down theswitching speed and avoiding po-tential oscillation problems withoutrisking linear operation. It also pro-vides for slower switching in lowerfrequency applications whereswitching losses are not as criticaland reduced transient voltages andgate drive currentrequirements may be a factor.

Table 4.2 was generatedconsidering hard switchedinductive load applications whichrepresent the majority of IGBTapplications. There are some low

frequency, chopper, and resonantmode applications for which valuesof series gate resistance outside ofthe limits in the table may be used.Consult the factory for specificrecommendations in these cases.

Figure 4.46 TypicalDependence ofSwitching Time onGate Resistance

100 101 102102

GATE RESISTANCE, RG, (Ω)

t d(o

n), t

r, t d

(off)

, tf,

(ns)

t d(on)

t f

t r

103

104

td(off)

CONDITIONS: HALF-BRIDGE INDUCTIVE LOAD SWITCHING OPERATION Tj = 125oC VCC = 300V VGE = ±15V

100 101 102101

GATE RESISTANCE, RG, (Ω)

SW

ITC

HIN

TG

LO

SS

, ES

W (

mJ/

PU

LSE

)

102

103

CONDITIONS: HALF-BRIDGE INDUCTIVE LOAD SWITCHING OPERATION Tj = 125oC VCC = 300V VGE = ±15V

Esw(on)

Esw(off)

Figure 4.47 TypicalDependence ofSwitching Loss onGate Resistance

Table 4.2 Values of Gate Resistance

Recommended Series Gate Resistance, RG, (ohms)

Voltage Turn-on(Volts) Type Number Min. Max

CM15**-12H 42 420

CM20**-12H 31 310

CM30**-12H 21 210

CM50**-12H 13 130

CM75**-12H 8.3 83

600 CM100**-12H 6.3 63

CM150**-12H 4.2 42

CM200**-12H 3.1 31

CM300**-12H 2.1 21

CM400**-12H 1.6 16

CM600**-12H 1.0 10

CM15**-24H 21 210

CM20**-24H 16 160

CM30**-24H 10 100

CM50**-24H 6.3 63

CM75**-24H 4.2 42

1200 CM100**-24H 3.1 31

CM150**-24H 2.1 21

CM200**-24H 1.6 16

CM300**-24H 1.0 10

CM400**-24H 0.78 8

CM600**-24H 2.1 22

CM1000**-24H 3.3 33

CM50**-28H 6.3 63

CM75**-28H 4.2 42

CM100**-28H 3.1 31

CM200DY-28H 1.6 16

1400 CM300DY-28H 1.0 10

CM400HA-28H 0.78 8

CM600HA-28H 2.1 22

CM1000HA-28H 3.3 33

1700 CM400HA-34H 10 50


USING IGBT MODULES

Sep.1998

4.6.3 Gate Drive PowerRequirements

IGBT switching consumes powerfrom the gate drive power supplyas a function of the transition fromnegative to positive bias, ∆GE, thetotal gate charge, QG, and thefrequency of operation, f. Theminimum peak current capability,IG(pk) of the supply is:

∆VGEIG(pk) = ±

RG

The average power, PAVG,required of the supply is:

PAVG = ∆VGE * QG * f

where

∆VGE = VGE(on) + | VGE(off) | QG = Total Gate Charge

(See Figure 4.48) f = Switching

Frequency

4.6.4 Gate Drive LayoutConsiderations

Gate drive layout is critical to avoidpotential oscillations, slow rise ofgate voltage, loss of noise immu-nity, sag in gate supply voltage, orreduction in efficiency of the gateprotection circuitry.

Guidelines that should be followedin designing the gate drive layoutare:

1. The layout must minimize theparasitic inductance betweenthe driver’s output stage andthe IGBT. This corresponds tokeeping the loop area as smallas possible in the indicatedsection of Figure 4.49.

2. Care must be taken to avoidcoupling of noise between thepower circuit and the controlcircuit. This can beaccomplished by properplacement of the gate driveboard and/or shielding thegate drive circuit.

3. It is recommended to use theauxiliary emitter terminal forconnecting the gate drive.

4. If direct connection of thedrive PCB to the IGBT controlterminals is not possible, theuse of twisted pair (3 turns perinch of minimum length) orstripline is recommended.

5. Gate protection clamp(described in Section 4.7.1)must also have low inductancelayout and must be located asclose as possible to thegate-emitter control terminalsof the IGBT module.

6. Do not route printed circuitboard traces near each otherthat are subjected to mutualpotential changes due to IGBTswitching. High dv/dt cancouple noise through parasiticcapacitances. If crossing orparallel routing of those tracesis unavoidable, use shieldlayers in between.

7. Parasitic capacitance betweenhigh side gate drive circuits,high and low side gate drivecircuits and control circuitsmay cause problems withcoupled noise. Power supplytransformer inter-windingcapacitance can be anothersource of coupled noise.

Appropriate measures toreduce these parasiticcapacitances have to beimplemented.

8. If optocouplers are used forisolation of the high side gatedrive signals they should havea minimum common modetransient immunity of10,000 V/µs.

QG

VGE (V)

(+VGE)

QG

(-VGE)

VGE

QG (C)

∆VGE

Figure 4.48 Total Gate Chargein IGBT Switching

E

G

Figure 4.49 Gate Drive Layout


USING IGBT MODULES

Sep.1998

4.7 Protecting IGBT Modules

4.7.1 dv/dt Protection

In half-bridge and inductive modeoperation the IGBT that is in theoff state is subjected to sharp riseof positive voltage due to recoveryof its anti-parallel diode. (SeeFigures 4.50 and 4.51) This staticdv/dt can be higher than the rateof rise of VCE at turn off of theIGBT. This dv/dt generates acurrent in the collector gatecapacitance that flows into the gatedrive circuit. (See Figure 4.52) Al-though the gate is reversebiased in the off-state, this currentcauses an increase of VGEtowards VGE(th) due to the gate cir-cuit impedance. In the worst case,the threshold voltage is reached atthe IGBT chip and turn on of theIGBT is initiated resulting in an armshoot through. Therequirements to avoid this untimelyturn on are:

1. VG(off) should be sufficientlynegative. (See Table 4.3)

2. RG in off-state should be low.(Recommended values aregiven in Table 4.2.)

3. Gate circuit inductance, LG,should be minimized.

Table 4.3 Recommended GateOff-bias

VCES Minimum Recommended

Rating VGE(off) VGE(off)

600V -2V -5 to -15V

1200V -5V -5 to -15V

1400V -5V -5 to -15V

1700V -5V -5 to -15V

RGVCC

RG

Q1

Q2

Irr

D1

D2

VQ1

VQ2

LOAD

VQ1 = IL

VQ2 = –IL

VQ2

Irr

trrb

Irr

IQ2

dIQ1/dt

dVQ1/dtID1

VQ2(pk)

dVQ1/dt

VQ1(pk)VQ1

trr

iD

GCG

RG LG

dv/dt

C

E

VGEVGE(OFF)

RGi LGiG

E

Figure 4.50 One-Phase Circuit of an Inverter Bridge(Inductive Load)

Figure 4.51 Relevant Current and Voltage Waveforms ofPhase Elements

Figure 4.52 dV/dt Effect on IGBT Gate Circuit


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Sep.1998

4.7.2 Short Circuit Protection

If a short circuit occurs the stresson the IGBT must remain withinthe SCSOA. (See Section 4.3.2)Common methods of short circuitprotection are current sensing (SeeFigure 4.53) and desaturationdetection (See Figure 4.54).

Once a short circuit is detected,several techniques can beemployed to protect the IGBT fromdestruction. The most elementarytechnique is to simply turn off theIGBT within 10ms. But, in thiscase, the snubber or clamp mustbe designed for the short circuitcondition. However, it isrecommended to use turn-offtechniques that control the VGE inorder to reduce the stress on theIGBT. These techniques are:

1. Controlled Shutdown:The gate voltage is reducedeither in steps or by a rampso the short circuit current isreduced and its di/dt is also

reduced as the IGBT turns off.The spike voltage is alsoreduced.

2. VGE Clamping:As described in Section 4.3.2the peak of the short circuitcurrent depends on VGE whichis augmented by the feedbackof dv/dt through the gate-col-lector capacitance. The effectcan be overcome by clampingthe VGE safely below 18 Volts.An effective clamping circuit isshown in Figure 4.55. Theclamping diode, DCL, andclamping capacitor, CCL,should be connected directly tothe control signal terminals ofthe IGBT module. A fast for-ward recovery is required forDCL. For low current IGBTs azener clamp between gate andemitter may also be effective.

3. Reducing t w:For reducing the thermal stressin short circuit operation it isbeneficial to reduce the time in

short circuit, tw. However, thiswill increase the magnitude ofthe current at turn off (See Fig-ure 4.56) and di/dt will be in-creased. This undesirable ef-fect may be overcome by usingthe techniques in Steps 1 and2 above.

Caution:The above techniques reduce thestress at short circuit turn-off.However, they do not release thedesigner from considering worstcase turn off in snubber design.

4.7.3 Handling Precautions

Since IGBT gates are insulatedfrom any other conducting region,care should be taken to preventstatic build up which could possibledamage gate oxides. All H-SeriesIGBT modules are shipped fromthe factory with conductive foamcontacting the gate and emittercontrol terminals. Never touch thegate terminals during assemblyand keep the conducting foam in

M

A. SYSTEM BLOCK DIAGRAM

BUS CURRENT

SENSE

COMPARATOR

LATCH DISABLE

DRIVER

<SIGNAL GATE>

UNDER PROTECTION

6

PWM SIGNALS

<PWM SIGNAL GENERATOR>

CLEAR PROTECTION

CLEAR

B. LOGIC DIAGRAM FOR OVER CURRENT PROTECTION

+

– R

S

Q

<F.F.> UNDER PROTECTION PWM SIGNALS

<PWM SIGNAL GENERATOR>

CLEAR PROTECTION

CURRENT SENSOR

Figure 4.53 Short-Circuit Protection Scheme (Example)


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Sep.1998

2. Use a 100V resistor in serieswith the gate when performingcurve tracer tests.

3. Never install devices intosystems with power connectedto the system.

4. Use soldering irons withgrounded tips when solderingto gate terminals.

4.8 Parallel Operation

Mitsubishi IGBT modules can beconnected in parallel for applica-tions requiring very high currents.In such applications parallel opera-tion should only be consideredwhen the highest current moduleavailable is not large enough. Useof a single large module ratherthan smaller parallel modules isrecommended because it elimi-nates concerns about static anddynamic current balance amongthe paralleled devices.With proper attention to circuit de-sign and device selection severalmodules can be reliably operatedin parallel. The followingsub-sections outline the basic re-quirements and considerations forparallel operation of single IGBTmodules with ratings of 200A ormore.

4.8.1 Static Current Balance

Table 4.4 outlines the factorsinfluencing parallel operation ofIGBT modules. Under static on-state or DC operating conditionsthe collector to emitter saturationvoltage and junction temperaturehave the biggest influence on cur-rent sharing. To achieve reliableand consistent static current bal-ance devices should be mountedon the heat sink near to each otherwith cooling arranged to maintainuniform base plate temperaturesbetween paralleled modules. Agood general design guideline is tomaintain a base plate temperaturedifference between paralleled de-vices of 15°C or less. Parallel con-nected devices should be selectedwith matched saturation voltages.The maximum static current imbal-

place until permanent connectionsare made to the gate and emittercontrol terminals. Always groundparts touching gate terminals dur-ing installation. In general, stan-dard ESD precautions applicable toMOSFETs shouldbe followed.

Other handling precautions thatshould be observed are:

1. Use grounded work stationwith grounded floors andgrounded wrist straps whenhandling devices.

ONLY FOR ARM SHORT CIRCUIT OUT OF SATURATION SHORT CIRCUIT DIAGRAM

FAULT LATCHCLEAR

FROM DRIVE LOGIC

GATE DRIVE

DISABLE

AND

COMPARATOR

Vref

ON

OFF

RG

+

-

-

+

DCL

VGE (ON)

VGE (OFF)

CCL

IC

tw2

tw1

Figure 4.54 Out of Saturation Short-Circuit Protection

Figure 4.55 V GE ClampingCircuit

Figure 4.56 Short-Circuit atReduced t w


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Sep.1998

ance as a function of saturationvoltage at Tj = 25°C is shown inFigure 4.57. Experimental analysishas demonstrated that the currentbalance becomes considerably bet-ter at elevated junction tempera-tures. For example, in the case of1200V H-series the worst case im-balance drops from 15%at 25°C to about 5% at 125°C. Fig-ure 4.58 shows how the imbalanceshown in Figure 4.57 is defined. Tofacilitate the matching of devicesfor parallel operation Mitsubishiprovides IGBT modules markedwith a saturation voltage rank letter.All devices to be operated in paral-lel should have the same saturationvoltage rank. Devices can also besupplied in matched sets for paral-lel applications. Contact the factoryfor ordering information. Table 4.5shows the standard saturation volt-age letter rankings for MitsubishiIGBT modules. Column 1 of thistable is applicable to all voltageclasses of U-Series and H-Seriesmodules and column 2 applies to250V trench gate IGBT modules.Note that all ranks do not exist for agiven voltage class. For example,600V H-Series modules have amaximum data sheet saturationvoltage of 2.8V and therefore ranksH through M do not exist for thesedevices. Saturation voltage ranksare intended for matching sets ofdevices for parallel applications.Orders specifying a specific rankwill not normally be accepted. Thesaturation voltage rank will be ei-ther marked with white ink on thetop of the module or indicated onthe label. Saturation voltage rank-ing is available for single modules

Table 4.5 Saturation Voltage Ranks For Parallel Applications

Saturation Voltage Ranks for H-Series Saturation Voltage Ranks for 250Vand U-Series IGBT Modules Trench Gate IGBT Modules

Saturation Voltage VCE(sat) (V) Saturation Voltage VCE(sat) (V)Rank IC = Rated Current Rank IC = Rated Current

VGE = 15V VGE = 15VTj = 25C Tj = 25C

C 1.70 ~ 1.95 Q 1.15 ~ 1.30

D 1.90 ~ 2.15 R 1.25 ~ 1.40

E 2.10 ~ 2.35 S 1.35 ~ 1.50

F 2.30 ~ 2.55

G 2.50 ~ 2.80

H 2.75 ~ 3.05

J 3.00 ~ 3.30

K 3.25 ~ 3.55

L 3.50 ~ 3.80

M 3.75 ~ 4.05

rated 200A or more. Saturationvoltage ranking is not normallyavailable for dual or six pack types.Modules of different saturation volt-age ranks may be used in thesame inverter provided that de-vices connected in parallel are ofthe same rank.

When modules of the same satura-tion voltage rank are paralleled thestatic current imbalance will beminimized sothat the following recommendedderatings can be applied:


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Table 4.4 IGBT Module Parallel Operation, Current Sharing

Factors related to current sharing and their effect.

Categories of Current Sharing

IGBT Switching Steady State

Factors Effecting Current Sharing Turn-on Turn-off di/dt = 0 di/dt ≠ 0

Device ∆VCE(SAT) X X X Characterization ∆ Temperature X

Main ∆L (Supply to ∂ X X

Circuit Device) Wiring ∆L (Total Loop X X X

Inductance Including Load)

Driver to Device X X

Driver Wiring Length Diff. Wiring Output Impedance X X

of Driver

- Relation Exists X - No Relation ∂ - Relation Ambiguous or Weak

Sep.1998

For 250V Trench Gate derateIC by 10%

For 600V Class H-Series andU-Series derate IC by 10%

For 1200V and 1400V ClassH-Series and U-Seriesderate IC by 15%

For 1700V Class H-Seriesderate IC by 20%

When more than two modules areparalleled the derating can be com-puted using the following formula:

Where:

x = 0.1 for 250V devicesx = 0.1 for 600V devicesx = 0.15 for 1200V/

1400V devicesx = 0.20 for 1700V devicesn = number parallel

[1–

% Derating =

(n – 1) (1 – x)

___________ (1 + x)

( + 1) ______________

n] X 100

[1–

% Derating = (4 – 1) (1 – .1)

___________

(1 + .1)( + 1)

______________ 4

] = 13.6%

0 0.2 0.4 0.6 0.80

∆VCE(sat) (V) Tj = 25°C

∆IC

/I C x

100

%

10

20

30

600V H&U SERIES 1200V H&U SERIES 250V TRENCH GATE SERIES

IC - ∆IC IC + ∆IC

IL = 2IC

Example:

In the case of four IGBT modulesof 600V class connected inparallel, the formula is:

So the derated current with 4parallel 300A modules is:

300A(1 - 0.136) x 4 = 1037A

4.8.2 Dynamic Current Balance

Matching VCE(sat) is effective formaintaining good static steadystate current balance. This match-ing also helps some with turn offcurrent balance because of the fun-damental inverse relationship of falltime and saturation voltage. How-ever, as indicated in Table 4.4, gatedrive conditions and power circuitlayout have by far the greatest im-pact on dynamic current balancebetween paralleled devices. Tem-perature differences between par-alleled modules is also a factor be-cause of the resulting effect on de-lay time and therefore the designguidelines given in Section 4.8.1should be observed for dynamiccurrent balance as well. To under-stand the circuit layout factors af-fecting dynamic current balance itis necessary to consider two cases:

The first case is when the deviceis in the static on-state and the loadcurrent is changing. As indicatedin Table 4.4 the main cause of im-balance in this case is differencesin inductance to the load connec-tion. In practical applications this ismost oftenthe result of an asymmetric con-nection of the load as shownin Figure 4.59. A typical current im-balance waveform resulting froman asymmetric load connection isshown in Figure 4.60. Experimentalanalysis has shown that this type ofimbalance can also be caused bythe orientation of the main circuitbus bars. For example, if the loadconnection causes the load currentto run in parallel with the current inone of the paralleled modules mu-

Figure 4.57 Maximum CurrentImbalance vs.DVCE(sat)

Figure 4.58 Circuit Showing theDefinition ofCurrent Imbalance


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Sep.1998

tual inductance effects can causethe inductance of thatpath to be effectively reduced or in-creased even though the mechani-cal connection point is symmetric.

The second case that must be con-sidered is current imbalance thatoccurs at the moment of turn-on orturn-off switching. Table 4.4 indi-cates that the most important fac-tors influencing current balance arethe gate circuit design and moduletemperature. The recommendedgate drive configuration for paral-leled modules is shown in Figure4.61. The recommended approachis to use a single drive stage with aseparate RG for each paralleledmodule. The small kelvin emitterconnections on the paralleled de-

vices should be connected with ashort, low impedance symmetricconnection in order to preventground loop currents from disrupt-ing the gate drive. In some powercircuit layouts it may become nec-essary to put some part of the RGimpedance in the ground path toimpede the flow of ground loop cur-rents. However, in this case im-provements in the power circuit lay-out should be investigated first. Inorder to maintain uniform switchingit is recommended to use relativelysmall values of series gate resis-tance. Series gate resistors shouldnever be larger than ten times thevalue recommended on the datasheet of the module being used.Care must be exercised to makethe gate wiring symmetric. In gen-

ASYMMETRIC LOAD CONNECTION

SYMMETRIC LOAD CONNECTION

IC1 IC2lC

lC1

lC2

t

Figure 4.59 Circuit Diagram Showing Symmetric and AsymmetricLoad Connections

Figure 4.60 Typical CurrentImbalance Causedby AssymetricLoad Connection

eral, the best practice is to mini-mize the inductance in the gatedrive wiring. Use of a printed circuitboard mounted directly to the mod-ule or short tightly twisted wires ofequal length is recommended.Care should be exercised to avoidinductive coupling to the gate driveby keeping the wiring from runningparallel to the main circuit current.Figure 4.62 shows a typical turn-offcurrent waveform with imbalancecaused by an improper gate drive.In addition to the influences of tem-perature and gate drive the currentbalance at turn-on is influenced bythe symmetry of the inductance inthe power circuit between the mainsupply capacitors and devices.Figure 4.63 is a circuit showingsymmetric versus asymmetric main


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Sep.1998

circuit connections. Figure 4.64shows a typical turn on waveformwith current imbalance caused byasymmetric main circuit induc-tance. An effective approach to bal-ance the main circuit inductance isminimize the inductance by usinglaminated bus structures. The cur-rent imbalance waveform at turn-ondue to improper gate drive alsolooks like Figure 4.64.

NOTE:It may be observed that MitsubishiIGBTs have a negativetemperature coefficient ofsaturation voltage over a widerange of collector currents. This isnot a deterrent to parallel operationand, in fact, is an advantage as ityields lower conduction loss at highjunction temperature. Thehomogeneous processcharacteristics of H-Series IGBTsproduce V

CE(sat) characteristics

that track as a function of currentand temperature such that, once aV

CE(sat) rank is chosen, the

parallel devices will share withinthe given derating factor.

GATE DRIVER

USE SHORT LOW IMPEDANCE

CONNECTION

RG

RGTWIST

USE SAME RG

GATE AND EMITTER CONNECTIONS LOW

INDUCTANCE AND SYMMETRIC

lC

lC1

lC2

t

Figure 4.61 Gate Drive Configuration for Paralleled Modules Figure 4.62 Typical CurrentWaveform ShowingImbalance at Turn-off Due to ImproperGate Drive


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Sep.1998

Figure 4.63 Symmetric and Asymmetric Main Circuit Connections

ASYMMETRIC MAIN BUS

CONNECTION SYMMETRIC MAIN BUS CONNECTION

IC1 IC2

Figure 4.64 Typical Turn-onWaveform withCurrent ImbalanceCaused byAsymmetric MainCircuit Inductance

lC

lC1

lC2

t


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MITSUBISHI SEMICONDUCTORS POWER MODULES MOS USING … IGBT … · structures of the IGBT, MOSFET...

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