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JFET

N-Channel P-Channel

Fig. (a) Fig. (b)

Fig. (a) is the schematic symbol for the n-channel JFET, and Fig. (b) shows the symbol for the p-channel JFET. The only difference is the direction of the arrow on the gate lead.

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Fig. illustrates the current flow in an n-channel JFET with p-type gates disconnected. The amount of current depends upon two factors:

The value of the drain-source voltage, VDS

The drain-source resistance, designated rDS

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Fig.

The gate regions in a JFET are embedded on each side of the channel to help control the amount of current flow in the channel. Fig. (a) shows an n-channel JFET with both gates shorted to the source. Fig. (b) shows how an n-channel JFET is normally biased.

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Fig. (a) shows an n-channel JFET connected to the proper biasing voltages. The drain is positive and the gate is negative, creating the depletion layers. Fig. (c) shows a complete set of drain curves for the JFET in Fig. (a).

Many techniques can be used to bias JFETs.

In all cases, the gate-source junction is reverse-biased.

The most common biasing techniques are Gate Self Voltage-divider Current-source

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Fig. (a) shows an example of gate bias. Fig. (b) shows how an ac signal is coupled to the gate of a JFET. If RG were omitted, as shown in (c), no ac signal would appear at the gate because VGG is at ground for ac signals.

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One of the most common ways to bias a JFET is with self-bias. (See Fig. a) Only a single power supply is used, the drain supply voltage, VDD.

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Fig. shows a JFET with voltage-divider bias. Since the gate-source junction has extremely high resistance, the R1 – R2 voltage divider is practically unloaded. Voltage-divider bias is more stable than either gate or self-bias.

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Fig. shows one of the best ways to bias JFETs, called current-source bias. The npn transistor with emitter bias acts like a current source for the JFET. The drain current , ID, equals the collector current, IC, which is independent of the value of VGS.

JFETs are commonly used to amplify small ac signals.

One reason for using a JFET instead of a bipolar transistor is that very high input impedance, Zin, can be obtained.

A big disadvantage, however, is that the voltage gain, AV, obtainable with a JFET is much smaller.

JFET amplifier configurations are as follows: Common-source (CS) Common-gate (CG) Common-drain (CD)

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Fig. (a) shows a common-source amplifier. For a common-source amplifier, the input voltage is applied to the gate and the output is taken at the drain.

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Fig. (b)

The ac equivalent circuit is shown in Fig. (b) On the input side, RG = Zin, which is 1 MΩ. This occurs because with practically zero gate current, the gate-source resistance, designated RGS, approaches infinity.

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Fig. (a) shows a common-drain amplifier, usually referred to as a source follower. A source follower has a high input impedance, low output impedance, and a voltage gain of less than one, or unity.

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A common-gate amplifier has a moderate voltage gain. Its big drawback is that Zin is quite low. Fig. (a) shows a CG amplifier.

The metal-oxide semiconductor field effect transistor has a gate, source, and drain just like the JFET.

The drain current in a MOSFET is controlled by the gate-source voltage VGS.

There are two basic types of MOSFETS: the enhancement-type and the depletion-type.

The enhancement-type MOSFET is usually referred to as an E-MOSFET, and the depletion-type, a D-MOSFET.

The MOSFET is also referred to as an IGFET because the gate is insulated from the channel.

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Fig. (a) shows the construction of an n-channel depletion-type MOSFET, and Fig. (b) shows the schematic symbol.

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Fig. shows the construction and schematic symbol for a p-channel, depletion-type MOSFET. Fig. (a) shows that the channel is made of p-type semiconductor material and the substrate is made of n-type semiconductor material. Fig. (b) shows the schematic symbol.

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Fig.(a)

Fig. (a) shows the construction of an n-channel, enhancement-type MOSFET. The p-type substrate makes contact with the SiO2 insulator. Because of this, there is no channel for conduction between the drain and source terminals.

Zero-bias can be used only with depletion-type MOSFETs.

Even though zero bias is the most commonly used technique for biasing depletion-type MOSFETs, other techniques can also be used.

Biasing techniques include Self Voltage-divider Current-source

Drain-feedback bias is often used to bias E-MOSFETs

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Fig. (a) shows a popular biasing technique that can be used only with depletion-type MOSFETs. This form of bias is called zero bias because the potential difference between the gate-source region is zero.

One disadvantage of MOSFET devices is their extreme sensitivity to electrostatic discharge (ESD) due to their insulated gate-source regions.

The SiO2 insulating layer is extremely thin and can be easily punctured by an electrostatic discharge.

The following is a list of MOSFET handling precautions Never insert or remove MOSFETs from a

circuit with the power on.

MOSFET handling precautions (Continued) Never apply input signals when the dc power

supply is off. Wear a grounding strap on your wrist when

handling MOSFET devices. When storing MOSFETs, keep the device leads

in contact with conductive foam, or connect a shorting ring around the leads.