Minimization of Delay Sensitivity to Process Induced Vth Variations

University of TorontoUniversity of Toronto

Minimization of Delay Sensitivity to Process Induced Vth Variations

Georges NabaaFarid N. Najm

University of Toronto(georges,najm)@eecg.utoronto

.ca

Nabaa-Najm NEWCAS-05 2

Outline

Introduction Problem formulation and goals Methodology Standard simulations

Static gates Dynamic gates Transmission gates

Standalone simulations Sizing simulations Conclusion


Introduction

The threshold voltage is a fundamental operational parameter of a MOSFET

For the past 30 years, performance improvements in semiconductors have been achieved by decreasing channel length

This decrease had to be accompanied by a Decrease supply voltage

Decrease threshold voltage (Vth)

This Vth decrease has not been followed by a corresponding decrease in threshold voltage variations

Nabaa-Najm

Random Dopant Fluctuations

Threshold Voltage is a function of the dopants in the channel

Due to the decrease in the number of dopants in DSM processes there is increased variability

IBM: ISSCC 2004IBM: ISSCC 2004


Threshold Voltage Variations

Threshold voltage variations (δVth) cause variations in circuit delay that impact the chip timing yield Can cause up to 30%

variation in chip frequency [BKN02]

Threshold Variations can be divided into Within-die Die-to-die

Tschanz 2002Tschanz 2002


Problem Formuation

Previous work applies chip wide compensation schemes Unsuitable for the within-die component Within-die variations become larger as the feature

length gets smaller We study design techniques that minimize

the effects of threshold variations on circuit delay variability (minimize delay sensitivity)

Specifically, we explore: Topology issues, e.g., series vs. parallel

arrangements Design style, e.g., static vs. dynamic (NAND vs

NOR) Optimization issues, e.g., sizing


Goals

Evaluate these styles based on performance penalty, area overhead, and delay variability minimization

This per gate approach tackles within-die variations intrinsically

Design δVth aware Libraries


Methodology

We model Vth variations (δVth ) as normally distributed random variables (RVs) The 3σ limits of the Normals are from the technology files Adjusted using the Law of Area: (Horstmann99)

The larger the transistors, the smaller the input Vth variations

For all the transistors in a given logic gate consider δVth variations as: Independent Normals (n transistors -> n independent

normals) Fully Positively Correlated Normals

WLA

vth


Methodology (cont)

Used 0.13um UMC process Generated 1000 sweep points and link it

to the DELVTO parameter in SPICE Run the simulation and record

propagation delay Absolute delay is input dependent For each gate we choose the worst-case input

vectors


Methodology

Assume Linearity between process and delay

From each sweep, the sensitivity is recorded as:

0

0.005

0.01

0.015

0.02

0.025

0.03

0.035

0.04

0.045

1 9 17 25 33 41 49 57 65 73 81 89 97

No

rma

lize

d P

rob

ab

ility

Vt

0

0.005

0.01

0.015

0.02

0.025

0.03

0.035

0.04

0.045

1 9 17 25 33 41 49 57 65 73 81 89 97

No

rma

lize

d P

rob

ab

ilty

De

lay

Normal Score for Output Delay (NAND)

-4

-3

-2

-1

0

1

2

3

4

-4 -3 -2 -1 0 1 2 3 4

3Delay


Static Gates: Series better than Parallel

Series stacks exhibit less delay sensitivity than their parallel counterparts. Explanation: body-effect minimizes the

impact of Vth

Design: insert series transistors to create series stacks

0

2

4

6

8

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12

14

16

18

Independent Correlated Independent Correlated

NMOS PMOS

Del

ay V

aria

tio

ns

(%)

Series

Parallel


Hybrid Gates

The fact that series are better than parallel led us to insert a “serializing” dummy transistor into the structure of a gate

For a 2-input NAND gate, two potential configurations:

Configuration 1Configuration 1 Configuration 2Configuration 2StandardStandard


Hybrid gates: Independent

Hybrid gates exhibit less delay variability than standard gates

0

2

4

6

8

10

12

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16

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Rise Delay Fall Delay

De

lay

Va

ria

tio

ns

(%

)

Original

Hybrid


Hybrid Gates: Correlation

0

2

4

6

8

10

12

14

16

18


Del

ay V

aria

tio

ns

(%) Original

Hybrid

Even with correlation Hybrid gates exhibit less delay

variability than standard gates


Hybrid Gates: Limitations

These gains come at the expense of larger absolute delays.

These delays can be recovered by a corresponding increase in area: In order for the hybrid NAND to match the nominal delay

performance its area must be 2.1 times the area of a standard NAND gate

This overhead is reduced as the number of inputs increases; For a three input hybrid NAND, the area overhead required

to match the nominal performance of a standard 3 input NAND gate is 1.5×.

To further minimize area overhead, we use a low Vth for the dummy transistor. Area overhead required to match similar performance is

down to 78 %


Dynamic Logic

Performed similar experiments on dynamic gates

NOR gates Very susceptible to variations The footer in standard dynamic logic helps to

reduce variability Still has large variability


Dynamic Gates: NAND

NAND Dynamic gates exhibit less variation than NOR Dynamic Gates Dynamic NAND has more variations than Static NAND

But footerless dynamic NAND gates are better than those with footer Can be attributed to the fact that the footer transistor

is also subjected to the normal δVth (and the circuit is already in series)

Use NAND Logic instead of NOR logic whenever possible. Footerless NAND logic is fastest and less prone to

variability


Transmission gates

Transmission gates display the best delay variability robustness in both Correlated simulations Independent simulations

Can be explained through the intrinsic structure of the gate NMOS and PMOS have opposite Vth values (in sign) In correlated simulations, when subjected to

similar ΔVth , the contribution (faster or slower) that results from say the NMOS device is counterbalanced by an equal contribution from the PMOS device and vice versa.

In independent simulations, the variability still remains low (half that of a NAND gate)


Transmission Gates

02468

1012141618


Del

ay V

aria

tio

ns

(%)

Static NAND

Transmission Gate AND

02468

1012141618


De

lay

Va

ria

tio

ns

(%

) Static NAND

Transmission Gate AND

Transmission Gate AND Transmission Gate AND vs Static NANDvs Static NAND(Independent)(Independent)

Transmission Gate AND Transmission Gate AND vs Static NANDvs Static NAND

(Correlated)(Correlated)


Standalone tests

Second Type of Test Input threshold voltage variations on only one

transistor at a time: Goals: Find (if any) the critical transistor in a

gate Can be made wider to minimize the Vth variations

Can be used in the context of a multiple Vth solution

Results: Bottommost transistor of a stack constitutes the

bottleneck This transistor can be made larger to minimize

variability Can also be used in the context of a multiple Vth

solution


Sizing

Third set of tests Simulated gates with different transistor sizes

The sizing simulations show that: Larger gates demonstrate less variability Optimal widths are twice the width of standard gates

Delay Variability vs. Sizing 2-input NAND

02468

1012141618

x1 x1.5 x.2 x.2.5 x.3Sizing

De

lay

Va

ria

bili

ty

(%)

28

2930

31

32

3334

35

Ab

so

lute

De

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(p

s)

NAND Δrise

NAND rise


Sizing

Delay Variability vs. Sizing (2-input NOR)

0

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x1 x1.5 x.2 x.2.5 x.3

Sizing

De

lay

Va

ria

bili

ty

(%)

34.53535.53636.53737.53838.5

Ab

so

lute

De

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(p

s)

NOR Δrise

NOR rise


Conclusion

We studied the delay sensitivity of major design families with respect to Vth variations

Series stack are less sensitive than parallel configurations

Serialized standard gates: hybrid NAND and NOR gates

NAND footerless logic is “better” than standard dynamic logic.

Transmission gates are intrinsically robust with respect to Vth variations

Optimal sizing of gates seems around 2x that of standard gates

Minimization of Delay Sensitivity to Process Induced Vth Variations

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