Midas a110 b
of 1
Transcript of Midas a110 b
-
7/30/2019 Midas a110 b
1/1
STMicroelectronics Belgium N.V.
Industriepark KeibergExcelsiorlaan 44-46
B-1930 Zaventem, Belgiumhttp://www.st.com
For further information,
please contact Project Leader:Patrick Wouters
With thanks to all MIDAS partnersMEDEA+ Forum 2004, 23-24 November, Paris, France
www.medeaplus.org
A110 MIDAS:A110 MIDAS: MMultiulti--standardstandard IIntegratedntegrated
DDevicesevices forfor broadbandbroadband DSLDSL AAccessccess andand
homehome powerlinepowerline communicationcommunicationSS
.
.
.
Activities in WP4Activities in WP4
Activities in WP5Activities in WP5
Activities in WP3Activities in WP3
Mechanisms, protocols and associated architectures forMechanisms, protocols and associated architectures forSecurity/Safety and QualitySecurity/Safety and Qualityof Service (of Service (QoSQoS) over DSL and PLC) over DSL and PLC linkslinks
ContributorsContributors::
Alcatel (B), FranceAlcatel (B), France TelecomTelecom R&D (F),R&D (F), UpzideUpzide Labs (Sw), Thomson (B), Ericsson (Sw), LTH (Sw),Labs (Sw), Thomson (B), Ericsson (Sw), LTH (Sw),ENS (F), Veyado (F)ENS (F), Veyado (F)
ResponsibleResponsible::
Alcatel (B)Alcatel (B)
ActivitiesActivities::
A.3.1: Security/safety issues related to lifeA.3.1: Security/safety issues related to life--line support,line support,
remote powering and maintenanceremote powering and maintenance
A.3.2: Quality of Services over DSL and PLC linksA.3.2: Quality of Services over DSL and PLC links
A.3.2.a: Network traffic models, services classification,A.3.2.a: Network traffic models, services classification, QoSQoS requirementsrequirements
A.3.2.b: Spectrum regulation, spectral management and resourcesA.3.2.b: Spectrum regulation, spectral management and resources managementmanagement
A.3.2.c: Bonding and inverse multiple accessA.3.2.c: Bonding and inverse multiple access
A.3.3: Higher layers protocols forA.3.3: Higher layers protocols for QoSQoS, network security and user privacy, network security and user privacy
Building blocks and chipsets designsBuilding blocks and chipsets designsforfor xDSLxDSL and PLC applicationsand PLC applications
ContributorsContributors::
ST (B), Alcatel (B), Thomson (B), ESATST (B), Alcatel (B), Thomson (B), ESAT--KULKUL (B),(B), IMSEIMSE--CNMCNM (Sp),(Sp),IMEC (B), DS2 (Sp)IMEC (B), DS2 (Sp)
ResponsibleResponsible::
ST (B)ST (B)
ActivitiesActivities::
A.4.1: Design of analogue building blocks forA.4.1: Design of analogue building blocks for xDSLxDSL and PLCand PLC
A.4.1.a: Design of line driversA.4.1.a: Design of line drivers
A.4.1.b: Design of highA.4.1.b: Design of high--speed convertersspeed converters
A.4.1.c: Design of integratedA.4.1.c: Design of integrated AnalogAnalog FrontFront--EndEnd
A.4.2: Design of digital building blocks and flexible/scalable aA.4.2: Design of digital building blocks and flexible/scalable architecturesrchitectures
A.4.3:A.4.3: DesignDesign ofof activeactive splitterssplitters
MultiMulti--standardstandard wirelinewireline integratedintegrated platformsplatforms,,demonstrationdemonstration andand teststests ContributorsContributors::
Thomson (B), DS2 (Sp), FranceThomson (B), DS2 (Sp), France TelecomTelecom R&D (F),R&D (F), SebaSeba service (B),service (B), IMECIMEC--INTECINTEC (B), LEA (F)(B), LEA (F)
ResponsibleResponsible::
Thomson (B)Thomson (B)
ActivitiesActivities::
A.5.1: Development of integrated access platforms and gatewaysA.5.1: Development of integrated access platforms and gateways
A.5.2: Demonstration and tests of integrated platformsA.5.2: Demonstration and tests of integrated platforms
Features
Buffer Admission Control
Scheduler
Policing : Dual GCRA
Priority+
1
8
SchedulerATMFilter
ATMProcessor
BufferAdmission
Control
Toline
Policing
ATMP
rocessor
BufferAdmission
Control
Priority+
1
8
Scheduler
Froml
ine
Line Downstream
Line Upstream
t
Priority
Low
High
GCR = B/T
B cells
T seconds
Enhanced priority based scheduler
Quality of Service concepts
Layout view of 14 bit A-D converter in 0.25 m CMOS for ADSL CPE
Demonstrator set-up
Prototype board forPLC Analogue Front-End
High-voltage output driverin 2.5V 0.25m CMOS technology
Synoptical View Remote Powering
Cable data fromstandards
field data
(country-specific cables)
Real Time Local Loop VDSLEmulator based on DigitalTechniques
demonstrations
SW probe linked to gateway or CPE firmware
HW probe with Ethernet interface
FPGA breadboard platform for PLC 1st generation validation
First hardware version of DSPunit for VDSL Emulator,
offering a noise floor betterthan -130 dBm/Hz
