MICROSYSTEMS LABORATORYDEPARTMENT OF ELECTRICAL &

COMPUTER ENGINEERING

A CMOS Voltage Adjustable All-Pass Circuit

Robert W. Newcomb

Talk for SWAN 06December 8, 2006

(Systems Workshop on Adaptive & Networks)At the Automation and Robotics Research Institute

The University of Texas at Arlington

With Great Thanks to, and Respect for,

Frank Lewis

And especially for taking the initiative toOrganize SWAN 06

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Main topic of this talk:The design of a VLSI all-pass CMOS circuit for variable phase controlled by a voltage . Possible uses: An alternate type of phase locked loop(may have a phase noise advantage)Phase correction for various purposes.

Outline:The degree one circuit of Maundy-Aronhime; Generalization to any degreeConversion to VLSI transistors; VLSI layoutSpice simulations; MathCad symbolic analysisAt end: Some Microsystems research topics.

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Reference: B. J. Maundy & P. Aronhime, "A Novel First-Order All- Pass Filter," International Journal of Electronics, Vol. 89, No. 9, 2002, pp. 739 - 743.

The ideas are based upon the circuit of Maundy & Aronhime. Their circuit gives

Vout=2*V3-Vin Using the RC voltage divider V3={(1/sC)/[R+(1/sC)]}Vin which is

V3={1/[1+sRC]}Vin

gives the degree one all-pass transfer function

Vout/Vin=[1-sRC]/[1+sRC] = T(s)=1/T(-s)

Angle T(jw) = -2*arctan(RCw); |T(jw)|=1

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The Maundy - Aronhime Circuit

IDM2=IDM1=>VGSM1=VGSM2=>V3-Vx=Vb-0IDM4=IDM3=>VGS4=VGS3=>Vin-Vy=Vx-0IDM6=IDM5=>VGS6=VGS5=>V3-Vo=Vy-0=> Vo=V3-Vy=V3-[Vin-Vx]=V3-[Vin-(V3-Vb)]=> Vo=2V3-Vin -Vb Here Vb is a DC offset; M4&M3 require Vin offset > 2Vthreshold NMOS

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Generalization to arbitrary rational all-pass

port.-1 lossless a of impedancepoint driving the

as blesynthesiza is z(s) , thereforeand,function reactance a is d[D(s)]Ev[D(s)]/O*R z(s) where

d[D(s)]Ev[D(s)]/OR/sz

z(s)Rz(s)

z(s)/R1z(s)/R

Od[D(s)]Ev[D(s)]Ev[D(s)]

inV

3V

or

D(s)s)]/2D([(D(s)

1)inVoutV

)T(1(*)2

1(inV3V

(2) into (1)

(2) 1))in

V3

V(2(*)T(

inVoutV

set

(1) monic and Hurwitz D(s) withD(s)D(-s)

)T(in

Vout

V

D(s)N(s)

T(s)

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Transistorization for VLSI and with variable R 7

Spice run: Phase in degrees8

Spice run: Magnitude in DB 9

Bias conditions for proper operation 10

Need to account for offsets due to substrates of M2, M4, M6Not connected to their sources; adds [(-Vbs)^½-^½] to VTO

Small Signal Analysis

By replacing each transistor by its pi equivalent, and Numbering x=4, y=5, ground=6, the indefinite Y matrixis obtained. Deleting the 6th row and column yields thenodal admittance matrix.

Y11 s( )s Cg gor

0

0

s Cg gm6 go5 go6

Y12 s( )

gor

s Cgs gm6

0

0

s Cgs

s Cgd gm5

Y21 s( )

gor

0

s Cgs gm4

s Cgs

0

s Cgd

Y22 s( )

s C3 gor

s Cgs gm2

0

s Cgs

s 2 Cg( ) gm2 go2 go1

s Cgd gm3

0

s Cgd

s 2 Cg( ) gm4 go4 go3

*

Form the 2-port Y(s)=Y11-Y12*Z22*Y21 where Z22=Y22^-1From which: T(s)=-Y(s)[2,1]/Y(s)[2,2]Display by float 4 to 4 digits and then solve, for the poles and zeros at different resistor control voltages, Vr.

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Using MathCad symbolic analysis, by eliminating Internal nodes (3,4,5) the transfer function is obtained

At Vr=1; T1 s( ) .1000e-1.3408e59s

3 .4601e71s2 .4245e82s .1936e89 .5113e48s

4

.3336e47s4 .1436e59s

3 .1552e70s2 .4136e80s .1892e87

T1poles

280224017903.14247865

110019883211.21689326

40207159123.703935431

4575253.5434072945902

T1zeros

281533881897.68268219

95130927327.539115326

4560434.1831566032044

310006620783.99776471

At Vr=2; T2 s( ) .1000e-1.3407e59s

3 .4601e71s2 .4245e82s .2394e88 .5113e48s

4

.3336e47s4 .1436e59s

3 .1552e70s2 .4136e80s .2343e86

Poles

83119048162807652755.

31070021145535858293.

12849299996210576479.

2267389.3405606996897

Zeros

84495397124519949174.

25577256343187389599.

2252388.7205777607871

77665064967802876332.

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Mathcad plots from symbolic transfer function

100 1 103

1 104

1 105

1 106

1 107

200

180

160

140

120

100

80

60

40

20

0

Phase1 w( )

Phase2 w( )

w

100 1 103

1 104

1 105

1 106

1 107

0.1

1

10

A1 w( )

A2 w( )

w

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VLSI Layout for 1.2U AMI fabrication14

6 main transistors10ux10u, cap 38ux32u

Vdd

Gnd

In

OutVr

Vb

Other research topics of Microsystems Laboratory:1. Use of ABR (=Acoustic Brain-Stem Response) for

characterizing hearing loss and creation of hearing aids.Possible use for control of Parkinsons' disease.

2. Use of Beeler-Reuter heart models for VLSI mimic of heart electrical control for effect of drugs on arrythmias.

3. Spice models for flexible transistor circuit design.

4. Spice models of DNA electrical characterization and use of braid group models of DNA type structures.

5. Use of nano sized Y-junctions for room temperature nano-computers based upon electron swarms.

6. Neural networks using single electron quantum dots.

7. VLSI realization of Prof. Roa’s neural simulink model incorporating Ca channels.

8. Wireless data collection for on patient sensors

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