1. GOOD JOB..4/23/2013 1

2. 80854/23/2013 2 3. Evolution of Intel Microprocessor..4004 8008 8080 8086 8086Introduced 15/11/1/4/72 1/4/74 8/6/74 1/6/79 71Clock108 108 2 MHz5,8,10 5,8speed kHz kHzMHzMHzBus Width4 bits8 bits8 bits 16 bits8 bitsNumber of230035006000 29,000 29,000transistor(microns) (10)(6)(3)(3)Addressabl 640 16kbyt64kbyte 1MB 1MBeMemory bytes essVirtual_ _ _ _ _Memory 4/23/2013 3 4. 1980 Intel processor.80286386 TM DX386 TM SX 4867 H DXCPUIntroduced1/2/82 1/10/8516/6/8810/4/89Clock speed 6,1.2,5MHz 16-33MHz 16-33MHz 25-50MHzBus width 16 bits32bits 16bits 32bitsNumber of 134,000(1. 275,000(1) 275,000(1) 1.2Transistor5) Million(10.8-(microns)1)Addressable 16MB 4GB4GB4GBmemoryVirtual 1GB64TB 64TB 64TBmemory 4/23/2013 4 5. 1990 Intel processor.486 TM SXPentium Pentium IPentium IIIntroduced22/4/9122/3/93 01/11/95 07/5/97Clock 16-133 60- 150- 200-Speed MHz166MHz200MHz 300MHzBus Width 32 bits32bits64 bits64 bitsNumber of 1.1853.1 5.57.5Transistor( Million(1) Million(.8) Million(0.6) Million(1.35microns))Addressabl4GB4GB 64GB 64GBe MemoryVirtual 64TB 64TB64TB 64TBMemory4/23/20135 6. 2000 Intel ProcessorPentium III Pentium 4 Introduced 26/2/99 25/11/2000 Clock speed450-660MHz1.3-1.8GHz Bus Width64 bits 64 bits Number of95 Million64 Million Transistor(micro ns) Addressable64GB64GB memory Virtual Memory 64 TB 64 TB 4/23/2013 6 7. 1.It has an 8-bit MICROPROCESSOR, it provides 8-bitsdata.2.It operate in a single +5V power supply at Vcc andground to Vss.3.It operates on clock cycle with 50% duty cycle.4. It has on chip clock generator, it contain like LC ,RSor crystal .5.It can operate with 3mhz clock frequency.6.It contain 16 bits address line , 8 bits data line and 64 Kbytes memory and 256 i/o ports.4/23/2013 7 8. 7.It support 74 instructions with the following addressingmodes:a) Immediate b) Register c) Direct d) Indirect e)Implied8. The ALU of 8085 performs.a) 8 bits binary addition with or without carryb) 16 bits binary addition c) 2 digit BCD additiond) 8 bits binary subtraction with or without borrow .e)8 bits logical AND,OR EX-OR COMPLEMENT (NOT) and bit shift operation. 4/23/2013 8 9. 9. It has 8-bit accumulator ,flag register ,instructional register , six 8-bit general register(B,C,D,E.H)AND 16 BITS register (SP andPC)10. It provides five hardware interrupts :TRAP,RST7.5,RST 6.5,RST 5.5 and INTR.11. IT has serial I/O control signal.12. It provides control signals (IO/M, RD WR,) to controlthe bus cycles and so external bus controller is notrequired.13. It can be used to implemented three chipmicrocomputer with supporting I/O device like IC 8155and 8355 4/23/2013 9 10. ARCHITECTURE OF 8085 :It consist of various functional blocks as listed below :RegistersArithmetic and logic unitInstruction decoder and machine cycle encoderAddress bufferAddress/data bufferIncrementer/decrementer address latchInterrupt controlSerial I/O controlTiming and control circuitry. 4/23/201310 11. INTR INTA RST5.5 RST6.5 RST7.5 TRAP SIDSOD 8 Bit internal data bus ACCUMULATTEMPFLAG W Reg Z Reg INST Reg.ORReg.Reg. B Reg C Reg D Reg E Reg INSTRUCTI H Reg L RegON STACK ALUDECODERPOINTER &MACHINE CYCLEPC INCREMENTER/DEENCODER CREMENTER POWER +5V ADDRESS LATCH SUPPLYGND TIMING AND CONTROLX1CLK GEN CONTROL STATUSDMA ADDADD/DATAX2RESETBUFFER BUFFER AA RD CLK OUTWR ALE SO S1IO/M15- 8READY HLDA RESET OUT HOLD RESET INADDRESS BUSAD7-AD0DATA/ADD BUS 11 4/23/2013 12. The 8085 register are classified as. 1 . General purpose Registers( A,B,C,D,E,H and L 8OR 16 Bits reg.)2. Temporary Registera) Temporary data Register b) W and Z Register 3. Special purpose Registers a) Accumulator b) Flag Register ( S,Z,AC,P,CY,-Sign flag) c) Instruction Register4) Sixteen Bit Register a) Program Counter b) Stack Pointer4/23/2013 12 13. 1. 16 bit Registers a) Program Counter (PC): Program is a sequence ofinstruction ,it store the addressof the next instruction at a given time. b) Stack Pointer(SP): It Reserved area of the memory in theRAM where temporary information maybe stored.2. Arithmetic Logic Unit(ALU): It perform bitwise fundamental arithmetic operation such as ADD,SUB Also perform logic operation AND,OR, EX-OR. 4/23/201313 14. 3. Instruction Decoder : It store opcode, then sent to instdecoder.Inst decoder decodes it andaccordingly gives timing and controlsignals which control the register, the data buffer,ALU and External signal depend on nature of the instruction.4. Address Buffer : It is 8 bit unidirectional buffer .it is used to driveexternal high order address bus (A15-A 8).5.Address/Data buffer : It is Bi- Directional buffer ,it isused to drive multiplexed address/data bus, low order(A7-A0) and data bus (D7-D0). 4/23/2013 14 15. 6. Incrementer/decrementer Address Latch : The 16 bit register is used to increment and decrement the content of program counter or stack pointer as a part of execution of instrelated to them.7. Interrupt Control : The processor fetch ,decodes and executes Instructionin a sequence. Its having special routine Wheneverspecial condition exits within a program.8. Serial I/O Control : it is used for long distance data transmission and communication .it provides two lines SOD and SID for serial communication. SOD(Serial output data) is used for send data serially and SID(Serial Input data)line used to receive data serially.9. Timing and control circuitry: it is responsible for all the operationssuch as control of fetching ,decoding operation,generating appropriate signals for inst execution.10.Power Supply and Frequency signals: It requires +5v . 4/23/201315 16. A6-A1(ADDRESS BUS)AD0-AD7( I/0 3 STATE Multiplexed add/data bus)ALE( output Address Latch Enable) S0-S1(output data bus Status) S1 So 0 0 HALT 0 1 WRITE(S1 Used for advance R/W status) 1 0 READ 11 FETCH4/23/201316 17. RD (READ OUTPUT)WR ( WRITE OUTPUT)READY( INPUT) HOLD(INPUT)HLDA (OUTPUT) INTR-INTERRUPT REQUEST ( INPUT)INTR-INTERRUPT ACKNOWLEDGE (OUTPUT)1) RST 7.52) RST 6.5(INPUT)3) RST 5.5 RESTART INTERRUPTS1) RST 7.5(HIGHEST PRIORITY)2) RST 6.5(INPUT)3) RST 5.5(LOWEST PRIORITY) 4/23/2013 17 18. TRAP (INPUT)RESET IN (INPUT)RESET OUT(OUTPUT)X1,X2 ( INPUT)CLK (OUTPUT)IO/M (OUTPUT)SID (OUTPUT)SOD (OUTPUT) 4/23/2013 18 19. 4/23/2013 19