MICRONAS DPL 4519G Sound Processor for Digital and Analog ... · Sound Processor for Digital and...

DPL 4519GSound Processor forDigital and Analog

Edition Oct. 31, 20006251-512-1PD

PRELIMINARY DATA SHEET

MICRONAS

MICRONAS

Surround Systems

DPL 4519G PRELIMINARY DATA SHEET

2 Micronas

Contents

Page Section Title

4 1. Introduction5 1.1. Features of the DPL 4519G6 1.2. Application Fields of the DPL 4519G

7 2. Functional Description7 2.1. Architecture of the DPL 4519G Family8 2.2. Preprocessing I2S Input Signals8 2.3. Selection of Internal Processed Surround Signals8 2.4. Source Selection and Output Channel Matrix8 2.5. Audio Baseband Processing8 2.5.1. Main and Aux Outputs8 2.6. Surround Processing8 2.6.1. Surround Processing Mode8 2.6.1.1. Decoder Matrix9 2.6.1.2. Surround Reproduction9 2.6.1.3. Center Modes9 2.6.1.4. Useful Combinations of Surround Processing Modes10 2.6.2. Examples11 2.6.3. Application Tips for using 3D-PANORAMA11 2.6.3.1. Sweet Spot11 2.6.3.2. Clipping11 2.6.3.3. Loudspeaker Requirements11 2.6.3.4. Cabinet Requirements11 2.6.4. Input and Output Levels for Dolby Surround Pro Logic11 2.7. SCART Signal Routing11 2.7.1. SCART Out Select12 2.7.2. Stand-by Mode12 2.8. I2S Bus Interfaces12 2.8.1. Synchronous I2S-Interface(s)12 2.8.2. Asynchronous I2S-Interface12 2.8.3. Multichannel I2S-Output12 2.8.4. Asynchronous Multichannel I2S-Input13 2.9. Digital Control I/O Pins13 2.10. Clock PLL Oscillator and Crystal Specifications

14 3. Control Interface14 3.1. I2C Bus Interface14 3.1.1. Device and Subaddresses14 3.1.2. Internal Hardware Error Handling15 3.1.3. Description of CONTROL Register15 3.1.4. Protocol Description16 3.1.5. Proposals for General DPL 4519G I2C Telegrams16 3.1.5.1. Symbols16 3.1.5.2. Write Telegrams16 3.1.5.3. Read Telegrams16 3.1.5.4. Examples16 3.2. Start-Up Sequence: Power-Up and I2C Controlling

Contents, continued

Page Section Title

PRELIMINARY DATA SHEET DPL 4519G

Micronas 3

16 3.3. DPL 4519G Programming Interface16 3.3.1. User Registers Overview19 3.3.2. Description of User Registers19 3.3.2.1. Write Registers on I2C Subaddress 10hex

21 3.3.2.2. Read Registers on I2C Subaddress 11hex

21 3.3.2.3. Write Registers on I2C Subaddress 12hex

33 3.3.2.4. Read Registers on I2C Subaddress 13hex

34 3.4. Programming Tips34 3.5. Examples of Minimum Initialization Codes34 3.5.1. Micronas Dolby Digital chipset (with MAS 3528E)

35 4. Specifications35 4.1. Outline Dimensions37 4.2. Pin Connections and Short Descriptions40 4.3. Pin Descriptions43 4.4. Pin Configurations45 4.5. Pin Circuits47 4.6. Electrical Characteristics47 4.6.1. Absolute Maximum Ratings48 4.6.2. Recommended Operating Conditions (TA = 0 to 70 °C)48 4.6.2.1. General Recommended Operating Conditions48 4.6.2.2. Analog Input and Output Recommendations49 4.6.2.3. Crystal Recommendations50 4.6.3. Characteristics50 4.6.3.1. General Characteristics51 4.6.3.2. Digital Inputs, Digital Outputs52 4.6.3.3. Reset Input and Power-Up53 4.6.3.4. I2C-Bus Characteristics54 4.6.3.5. I2S-Bus Characteristics56 4.6.3.6. Analog Baseband Inputs and Outputs, AGNDC58 4.6.3.7. Power Supply Rejection58 4.6.3.8. Analog Performance

61 5. Appendix A: Application Information61 5.1. Phase Relationship of Analog Outputs62 5.2. Application Circuit

64 6. Data Sheet History

License Notice:

“Dolby Pro Logic” and “Dolby Digital” are trademarks of Dolby Laboratories.

Supply of this implementation of Dolby Technology does not convey a license nor imply a right under any patent, or any other industrial or intellec-tual property right of Dolby Laboratories, to use this implementation in any finished end-user or ready-to-use final product. Companies planning touse this implementation in products must obtain a license from Dolby Laboratories Licensing Corporation before designing such products.


4 Micronas

Sound Processor for Digital and Analog Surround Systems

The hardware and software description in this docu-ment is valid for the DPL 4519G version A1 and follow-ing versions.

1. Introduction

The DPL 4519G processor is designed as part of theMicronas chip set for digital and analog Surround Sys-tems i. e. Dolby Digital, MPEG 2 Audio, or Dolby Pro-Logic. The combination of MAS 3528E, DPL 4519G,and MSP 44x0G is a complete 5.1 channel Dolby Digi-tal decoder and playback solution, while DPL 4519Gand MSP 44x0G alone, represent a complete DolbySurround Pro Logic system.

The DPL 4519G receives its incoming data via highlyflexible I2S interfaces. The three I2S input interfacescan be configured as three asynchronous I2S inputs ortwo synchronous and one asynchronous interface. Inthe latter case, the asynchronous interface allowsreception of 2-8 channels with arbitrary sample rateranging from 8 to 48 kHz. The synchronization is per-formed by means of an adaptive high-quality samplerate converter.

In an application together with the Dolby Digitaldecoder MAS 3528E, eight channels (left, right, sur-round left, surround right, center, subwoofer, Pro Logicencoded left, Pro Logic encoded right) are fed in andprocessed in the DPL 4519G.

Similar to the multichannel I2S input interface, the DPLis provided with an 8-channel I2S output interface,which can be connected to a MSP 44x0G. Thereforeall 8 channels can be routed to each output in bothICs.

The baseband processing including e.g. balance,bass, treble, and loudness is performed at a fixed sam-ple rate of 48 kHz.

Fig. 1–1 shows a simplified functional block diagram ofthe DPL 4519G.

The DPL 4519G is pin-compatible to members of theMSP 34xx family. This speeds up PCB developmentfor customers using MSPs.

The software interface of the DPL 4519G is alsolargely the same as for members of the MSP family.

The ICs are produced in submicron CMOS technologyand are available in PQFP80, PLQFP64 and inPSDIP64 packages.

Fig. 1–1: Simplified block diagram of the DPL 4519G

So

urc

e S

elec

t

Main

SCART1

SCART2

AUX

I2S

DAC

DAC

Main

DAC

SCART Output Select

I2S2

I2S1 I2S

I2SI2S3

SoundProcessing

AUXSound

Processing(2..8-channel)

(8-channel)

I2S

Pre

scal

e

ProLogicprocessingSCART1

SCART2

SCART4

SCART3

MONO

Subwoofer


Micronas 5

1.1. Features of the DPL 4519G

– 8-channel asynchonous I2S input interface (multichannel mode)+ 2 synchronous I2S input channels (e.g. for MSP and ADR)

or3 asynchronous two-channel I2S input interfaces

– Main and AUX channel with balance, bass, treble, loudness, volume

– 5-band graphic equalizer for Main channel

– Dolby Surround Pro Logic Adaptive Matrix

– Micronas Effect Matrix

– Micronas “3D-Panorama” virtualizer compliant to “Virtual Dolby Surround” technology

– Micronas Panorama sound mode (3D Surround sound via two loudspeakers)

– Noise Generator

– Spatial Effect for Surround

– 30-ms Surround delay

– Surround matrix control: Adaptive/Passive/Effect

– Center mode control: Normal/Phantom/Wide/Off

– Surround reproduction control: Rear speaker, Front speaker, Panorama, 3D-Panorama

– Two digital input/output pins controlled by I2C bus

Fig. 1–2 shows a typical Dolby Digital application using DPL 4519G, MSP 4450G, and MAS 3528E.


6 Micronas

1.2. Application Fields of the DPL 4519G

Fig. 1–2: Typical DPL 4519G application

DPL 4519GPro Logic Decoder

I2S_WS3I2S_CL3

6 ChannelLoop-through

orDolby

Pro LogicDecoder

I2S_1_LI2S_1_R

I2S_3_Rt

I2S_3_Lt

AUDIO_CL_OUT

SIF-IN

I2S_WSI2S_CL

Main

Aux

I2S_WSI2S_CL

Demod

SCART1_In

SCART4_InA/D2

.

.

.

I2S_2_LI2S_2_R

R

L

SL

SUB

BassTreble

BalanceVolume

BassTreble

BalanceVolume

MSP 4450GMultistandard Sound Processor

I2S_1_LI2S_1_R

I2S_2_LI2S_2_R

Sound-Process.BalanceVolume

BassTreble

BalanceVolume

Volume

Volume

18.432MHz

I2S_Inputs

1 2 3

1 2 3

I2S_Inputs

D/AanalogVolume

D/A

D/A

I2S_WS3I2S_CL3

Configuration Examples

2-8Channel

SerialInput

I2S_3_Lt

I2S_3_SL

Main

Aux

SCART1

SCART2

normal

D/AanalogVolume

D/AanalogVolume

D/AanalogVolume

Cint

Cint

LtRt

LtRt

L, R

Lext

SUBext

Dolby Digital /Pro Logic

SLSR

Cint

SUBext

L, RC, SUBSL, SRLt, Rt

Lint

Rint

Subwint

LtRt

LtRt

L, R

---

---

------

---

L

RSubw

LR

LR

L, R

Subwint

1 2

BasicTV-

Sound System

DolbyDigital

UpgradeModule

L, RC, SUBSL, SRLt, Rt

18.432MHz

Dolby Digital: (L t, Rt, L, R, SL, SR, C, SUB)Pro Logic: (Lt, Rt, L, R, C, SubW)

I2S_Out_L/R

I2S_Out_L/R

SLSR

I2S_3_R

I2S_3_SUB

S/PDIF OutPCM-Format (Lt/Rt or L/R or Lo/Ro)

or Loop-through (e.g. DTS)

18.432 MHz

I2S-Mode:Multichannel Mode auf D0(6 - 8 Channels, fs=32, 44.1 or 48 kHz,

16,18,....32 Bit)

I2S-In: Slave

LtRt

------

LtRt

2

Volume D/ASCART1

I2S_3_Rt

Rext(Cint)---

LtRt

LtRt

LR

I2S_3_L

I2S_3_SR

I2S_3_C

2-8 Ch. Input(LT, RT,L, R

SL, SR,C, SUB)

SR

C

Dolby Digital / Pro Logic ConfigurationsExample 1:- internal L, C, R- internal woofer for low freq. of L, (C), R- ext. Surround speakers SL, SR- ext. Subwoofer for SUB channel.

Example 2:- internal Left and Right used as C- internal woofer for low freq. of C- ext. L, R- ext. Surround speakers SL, SR- ext. Subwoofer for SUB channel.

MAS 3528EDolby Digital Decoder

MPEG-L2 Decoder

SICSIISID

SIC*SII*SID*

SOCSOISODSOD1SOD2SOD3Input

Buffer Dee

mph

asis

Pos

t Pro

cess

ing

Del

ay L

ines

AC-3

PCM

MPEG

LR

LtRt

LsRs

Amp./Osc.

PLL Synth.

CLKO

NoiseGen.

Mul

tipl.

C/Sub

S/PDI1

SPDO

S/PDIF In 1/2AC-3, MPEG L2, PCM or other Format

S/PDI2


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2. Functional Description

2.1. Architecture of the DPL 4519G Family

Fig. 2–1 shows a simplified block diagram of the IC.

Vol

ume

Pre

scal

e

DA

CA

_L

DA

CA

_R

I2 SC

hann

elM

atrix

Mai

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hann

elM

atri

x

Aux

Cha

nnel

Mat

rix

Vol

ume

I2S

In

terfa

ce

I2 SIn

terfa

ce

I2 SIn

terf

ace

SC

1_IN

_L

SC

1_IN

_R

SC

2_IN

_L

SC

2_IN

_R

SC

3_IN

_L

SC

3_IN

_R

SC

4_IN

_L

SC

4_IN

_R

MO

NO

_IN

Pre

scal

e

I2S

_DA

_OU

T

I2S

_DA

_IN

1

I2S

_DA

_IN

3

D

A

sync

hron

izat

ion

(syn

c. 4

8kH

z)

(asy

nc. 8

-48

kHz)

DA

CM

_L

DA

CM

_R

Vol

ume

I2 S1

I2 S3

SC

1_O

UT

_L

SC

1_O

UT

_R

SC

2_O

UT

_L

SC

2_O

UT

_R

SCART Output Select

I2 SIn

terfa

ceP

resc

ale

I2S

_DA

_IN

2I2 S

2

(syn

c. 4

8kH

z)

(syn

c. 4

8kH

z)I2S

_CL

I2S

_WS

I2S

_CL3

I2S

_WS

3

(16 h

ex)

(12 h

ex)

(11 h

ex)

(08 h

ex)

(09 h

ex)

(0B

hex)

(06 h

ex)

(00 h

ex)

Bee

per

Σ Σ

(14 h

ex)

Fig

. 2–1

:S

igna

l flo

w b

lock

dia

gram

of t

he D

PL

4519

G (

inpu

t and

out

put n

ames

cor

resp

ond

to p

in n

ames

)

Source Select

8 9 1065 7L t R

t

L R SL

SR C

SU

B

I2S_3 Resorting Matrix

(36 h

ex)

D

A

SC

AR

T1

Cha

nnel

Mat

rix

(0A

hex)

(07 h

ex)

SC

AR

T1_

L/R

Sur

roun

dC

hann

elM

atrix

(48 h

ex)

Noi

seG

ener

ator

Sur

roun

dP

roce

ssin

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Bal

ance

Bas

s/Tr

eble

/Lo

udne

ss/

Equ

aliz

er

Bal

anc

Sub

woo

-fe

r Le

vel

Adj

ust

DA

CM

_SU

B

D

A

Bas

s/Tr

eble

/Lo

udne

ss

Internal/External Switch

(36 h

ex)

(49 h

ex)

(4A

hex)

(4B

hex)

(4C

hex)

(4D

hex)

(2C

hex)

(31/

32/3

3 hex

)

(02/

03/0

4 hex

)

(01 h

ex)

(20.

.25 h

ex)

(30 h

ex)

L R SL

SR C

SU

B


8 Micronas

2.2. Preprocessing I2S Input Signals

The I2S inputs can be adjusted in level by means of theI2S prescale registers.

The I2S_3 interface is able to receive more than twochannels (see Section 2.6. on page 8). The incomingsignals can be resorted by a programmable matrix inorder to obtain a certain order, which means an unifiedpostprocessing afterwards.

Since the I2S_3 interface is asynchronous, incomingsound signals with arbitrary sample rates in the rangeof 8-48 kHz are interpolated to 48 kHz by means of anadaptive high quality sample rate converter. Thereforeall subsequent processing is calculated on a fixedsampling rate, which even can be synchronized toI2S_WS e.g. to a MSP 4450 being locked to an incom-ing NICAM signal.

2.3. Selection of Internal Processed Surround Signals

Instead of having an multichannel input via the I2S_3interface, a multichannel signal can be created by aninternal Dolby Pro Logic decoder. In that case chan-nels 3..8 of the multichannel input are replaced by theinternally generated signals.

2.4. Source Selection and Output Channel Matrix

The Source Selector makes it possible to distribute allsource signals (I2S input signals) to the desired outputchannels (Main, Aux, etc.). All input and output signalscan be processed simultaneously. Each source chan-nel is identified by a unique source address.

For each output channel, the output channel matrixcan be set to sound A (left mono), sound B (rightmono), stereo, or mono (sound left and right).

2.5. Audio Baseband Processing

2.5.1. Main and Aux Outputs

The following baseband features are implemented inthe Main and Aux output channels: bass/treble, loud-ness, balance, and volume. A square wave beeper canbe added to these outputs. The Main channel addition-ally supports an equalizer function (this is not simulta-neously available with bass/treble).

2.6. Surround Processing

2.6.1. Surround Processing Mode

Surround sound processing is controlled by three func-tions:

The "Decoder Matrix" defines which method is used tocreate a multichannel signal (L, C, R, S) out of a stereoinput.

The "Surround Reproduction" determines whether thesurround signal “S” is fed to surround speakers. If nosurround speaker is actually connected, it defines themethod that is used to create surround effects.

The “Center Mode” determines how the center signal“C” is to be processed. It can be left unmodified, dis-tributed to left and right, discarded or high pass fil-tered, whereby the low pass signals are distributed toleft and right.

2.6.1.1. Decoder Matrix

The Decoder Matrix allows three settings:

– ADAPTIVE:The Adaptive Matrix is used for Dolby Surround Pro Logic. Even sound material not encoded in Dolby Surround will produce good surround effects in this mode. The use of the Adaptive Matrix requires a license from Dolby Laboratories (See License Notice on page 3).

– PASSIVE:A simple fixed matrix is used for surround sound.

– EFFECT: A fixed matrix that is used for mono sound and spe-cial effects. With Adaptive or Passive Matrix no sur-round signal is present in case of mono, moreover in Adaptive mode even the left and right output chan-nels carry no signal (or just low frequency signals in case of Center Mode = NORMAL). If surround sound is still required for mono signals, the Effect Matrix can be used. This forces the surround chan-nel to be active. The Effect Matrix can be used together with 3D-PANORAMA. The result will be a pseudo stereo effect or a broadened stereo image respectively.


Micronas 9

2.6.1.2. Surround Reproduction

Surround sound can be reproduced with four choices:

– REAR_SPEAKER:If there are any surround speakers connected to the system, this mode should be used. Useful loud-speaker combinations are (L, C, R, S) or (L, R, S).

– FRONT_SPEAKER: If there is no surround speaker connected, this mode can be used. Surround information is mixed to left and right output but without creating the illusion of a virtual speaker. It is similar to stereo but an additional center speaker can be used. This mode should be used with the Adaptive decoder Matrix only. Useful loudspeaker combinations are (L, C, R) (Note: the surround output channel is muted).

– PANORAMA: The surround information is mixed to left and right in order to create the illusion of a virtual surround speaker. Useful loudspeaker combinations are (L, C, R) or (L, R) (Note: the surround output channel is muted).

– 3D-PANORAMA: Like PANORAMA with improved effect. This algo-rithm has been approved by the Dolby Laboratories for compliance with the "Virtual Dolby Surround" technology. Useful loudspeaker combinations are (L, C, R) or (L, R) (Note: the surround output chan-nel is muted).

2.6.1.3. Center Modes

Four center modes are supported:

– NORMAL: small center speaker connected, L and R speakers have better bass capability. Center signal is high pass filtered.

– WIDE:L, R, and C speakers all have good bass capability.

– PHANTOM:No center speaker used. Center signal is distributed to L and R (Note: the center output channel C is muted).

– OFF:No center speaker used. Center signal C is dis-carded (Note: the center output channel C is muted).

2.6.1.4. Useful Combinations of Surround Processing Modes

In principle, "Decoder Matrix", "Surround Reproduc-tion", and "Center Modes" are independent settings (all"Decoder Matrix" settings can be used with all "Sur-round Reproduction" and "Center Modes") but thereare some combinations that do not create "good"sound. Useful combinations are

Surround Reproduction and Center Modes

– REAR_SPEAKER: This mode is used if surround speakers are avail-able. Useful center modes are NORMAL, WIDE, PHANTOM, and OFF.

– FRONT_SPEAKER: This mode can be used if no surround speaker but a center speaker is connected. Useful center modes are NORMAL and WIDE.

– PANORAMA or 3D-PANORAMA:No surround speaker used. Two (L and R) or three (L, R, and C) loudspeakers can be used. Useful center modes are NORMAL, WIDE, PHANTOM, and OFF.

Center Modes and Decoder Matrix

– PHANTOM: Should only be used together with ADAPTIVE Decoder Matrix.

– NORMAL and WIDE:Can be used together with any Surround Decoder Matrix.

– OFF:This mode can be used together with the PASSIVE and EFFECT Decoder Matrix (no center speaker connected).


10 Micronas

2.6.2. Examples

Table 2–1 shows some examples of how these modescan be used to configure the IC. The list is notintended to be complete, more modes are possible.

Table 2–1: Examples of Surround Configurations

Configurations Speaker Config-uration1)

Surround Processing ModeRegister (4Bhex)

Decoder Matrix[15:8]

Surround Reproduction[7:4]

Center Mode[3:0]

Stereo

Stereo (L,R) − − −

Surround Modes as defined by Dolby Laboratories 2)

Dolby Surround Pro Logic (L,C,R,S) ADAPTIVE REAR_SPEAKER

NORMALWIDE

(L,R,S) ADAPTIVE REAR_SPEAKER

PHANTOM

Dolby 3 Stereo (L,C,R) ADAPTIVE FRONT_SPEAKER

NORMALWIDE

Virtual Dolby Surround (L,R) ADAPTIVE 3D_PANORAMA PHANTOM

Surround Modes that use the Dolby Adaptive Matrix2)

3-Channel Virtual Surround (L,C,R) ADAPTIVE 3D_PANORAMA NORMALWIDE

Passive Matrix Surround Sound

4-Channel Surround (L,C,R,S) PASSIVE REAR_SPEAKER

NORMALWIDE

3-Channel Surround (L,R,S) PASSIVE REAR_SPEAKER

OFF

2-Channel Micronas 3D Surround Sound (MSS) (L,R) PASSIVE 3D_PANORAMA OFF

3-Channel Micronas 3D Surround Sound (MSS) (L,C,R) PASSIVE 3D_PANORAMA NORMALWIDE

Special Effects Surround Sound

4-Channel Surround for mono (L,C,R,S) EFFECT REAR_SPEAKER

NORMALWIDE

2-Channel Virtual Surround for mono (L,R) EFFECT 3D_PANORAMA OFF

3-Channel Virtual Surround for mono (L,C,R) EFFECT 3D_PANORAMA NORMALWIDE

1) Speakers not in use are muted automatically.2) The implementation in products requires a license from Dolby Laboratories Licensing Corporation (see note on page 3).


Micronas 11

2.6.3. Application Tips for using 3D-PANORAMA

2.6.3.1. Sweet Spot

Good results are only obtained in a rather close areaalong the middle axis between the two loudspeakers:the sweet spot. Moving away from this positiondegrades the effect.

2.6.3.2. Clipping

For the test at Dolby Labs, it is very important to haveno clipping effects even with worst case signals. TheI2S-prescale register has to be set to values of max10hex (16dec). This is sufficient in terms of clipping.

However, it was found, that by reducing the prescale toa value lower than 16dec more convincing effects aregenerated in case of very high dynamic signals. Avalue of 10dec is a good compromise between overallvolume and additional headroom.

Test signals: sine sweep with 0 dBFS; L only, R only,L&R equal phase, L&R anti phase.

Listening tests: Dolby Trailers (train trailer, city trailer,canyon trailer...)

2.6.3.3. Loudspeaker Requirements

The loudspeakers used and their positioning inside theTV set will greatly influence the performance of the vir-tualizer. The algorithm works with the direct soundpath. Reflected sound waves reduce the effect. So it’smost important to have as much direct sound as possi-ble, compared to indirect sound.

To obtain the approval for a TV set, Dolby Laboratoriesrequire mounting the loudspeakers at the front of theset. Loudspeakers radiating to the side of the TV setwill not produce convincing effects. Good directionalityof the loudspeakers towards the listener is optimal.

The virtualizer was specially developed for implemen-tation in TV sets. Even for rather small stereo TV's, suf-ficient sound effects can be obtained. For small sets,the loudspeaker placement should be to the side of theCRT; for large screen sets (or 16:9 sets), mounting theloudspeakers below the CRT is acceptable (large sep-aration is preferred, low frequency speakers should beoutmost to avoid cancellation effects). Using externalloudspeakers with a large stereo base will not createoptimal effects.

The loudspeakers should be able to reproduce a widefrequency range. The most important frequency rangestarts from 160 Hz and ranges up to 5 kHz.

Great care has to be taken with systems that use onecommon subwoofer: A single loudspeaker cannotreproduce virtual sound locations. The crossover fre-quency must be lower than 120 Hz.

2.6.3.4. Cabinet Requirements

During listening tests at Dolby Laboratories, no reso-nances in the cabinet should occur.

Good material to check for resonances are the DolbyTrailers or other dynamic sound tracks.

2.6.4. Input and Output Levels for Dolby Surround Pro Logic

The nominal input level (input sensitivity) for the I2S-Inputs is −15 dBFS. The highest possible input level of0 dBFS is accepted without internal overflow. The I2S-prescale value should be set to values of max 0 dB(16dec).

With higher prescale values lower input sensitivitiescan be accommodated. A higher input sensitivity is notpossible, because at least 15 dB headroom is requiredfor every input according to the Dolby specifications.

A full-scale left only input (0 dBFS) will produce a full-scale left only output (at 0 dB volume). The typical out-put level is 1.37 Vrms for DACM_L. The same holdstrue for right only signals (1.37 Vrms for DACM_R). Afull-scale input level on both inputs (Lin=Rin=0 dBFS)will give a center only output with maximum level. Afull-scale input level on both inputs (but Lin and Rinwith inverted phases) will give a surround-only signalwith maximum level.

For reproducing Dolby Pro Logic according to its spec-ifications, the center and surround outputs must beamplified by 3 dB with respect to the L and R outputsignals. This can be done in two ways:

1. By implementing 3 dB more amplification for center and surround loudspeaker outputs.

2. By always selecting volume for L and R 3 dB lower than center and surround. Method 1 is preferable, as method 2 lowers the achievable SNR for left and right signals by 3 dB.

2.7. SCART Signal Routing

2.7.1. SCART Out Select

The SCART Output Select block includes full matrixswitching facilities. The switches are controlled by theACB user register (see page page 30).


12 Micronas

2.7.2. Stand-by Mode

If the DPL 4519G is switched off by first pullingSTANDBYQ low and then (after >1 µs delay) switchingoff DVSUP and AVSUP, but keeping AHVSUP (‘Stand-by’-mode ), the SCART switches maintain their posi-tion and function. This allows the copying fromselected SCART-inputs to SCART-outputs in the TVset’s stand-by mode.

In case of power on or starting from stand-by (seedetails on the power-up sequence in Fig. 4–19 onpage 52), all internal registers except the ACB register(page 30) are reset to the default configuration (seeTable 3–5 on page 17). The reset position of the ACBregister becomes active after the first I2C transmissioninto the Baseband Processing part (subaddress12hex). By transmitting the ACB register first, the resetstate can be redefined.

2.8. I2S Bus Interfaces

The DPL 4519G has two kinds of interfaces: synchronmaster/slave input/output interfaces running on 48 kHzand an asynchron slave interface.

The interfaces accept a variety of formats with differentsample width, bit-orientation, and wordstrobe timing.All I2S options are set by means of the MODUS orI2S_CONFIG register.

2.8.1. Synchronous I2S-Interface(s)

The synchronous I2S bus interface consists of thepins:

– I2S_DA_IN1, I2S_DA_IN2/3 (I2S_DA_IN2 in PQFP80 package):I2S serial data input, 16, 18...32 bits per sample.

– I2S_DA_OUT:I2S serial data output, 16, 18...32 bits per sample.

– I2S_CL:I2S serial clock.

– I2S_WS: I2S word strobe signal defines the left and right sample.

If the DPL 4519G serves as the master on the I2Sinterface, the clock and word strobe lines are driven bythe DPL 4519G. In this mode, only 16, 32 bits persample can be selected. In slave mode, these lines areinput to the DPL 4519G and the DPL 4519G clock issynchronized to 384 times the I2S_WS rate (48 kHz).An I2S timing diagram is shown in Fig. 4–21 onpage 55.

2.8.2. Asynchronous I2S-Interface

The asynchronous I2S slave interface allows thereception of digital audio signals with arbitrary samplerates from 5 to 50 kHz. The synchronization is per-formed by means of an adaptive sample rate con-verter. No oversampling clock is required.

The following pins are used for the asynchronous I2Sbus interface (serve only as input):

– I2S_WS3

– I2S_CL3

– I2S_DA_IN2/3 (I2S_DA_IN3 in PQFP80 package).

The interface accepts I2S-input streams with MSB firstand with sample widths of 16,18...32 bits. With left/right alignment and wordstrobe timing polarity, thereare additional parameters available for the adaption toa variety of formats in the I2S CONFIGURATION reg-ister.

2.8.3. Multichannel I2S-Output

Bit[0:1] of the I2S CONFIGURATION register (seepage 20) switches the output to 8 channel multichan-nel output mode. The bit resolution per channel is 32bit in master mode. While the first two channels can beselected on the source select matrix, channels 3-8 arealways connected to the I2S_3 input channels 3-8.Both, master and slave mode is possible, as long as asthe wordstrobe has only one positive edge per frame inslave mode.

2.8.4. Asynchronous Multichannel I2S-Input

The DPL 4519G supports two kinds of asynchronousmultichannel input:

– the asynchronous I2S_3 interface can be switched to multichannel mode (bit [8] of the I2S CONFIGU-RATION register is set to 1. The number of chan-nels must be even and less or equal eight.

– All I2S input lines (I2S_DA_IN1, I2S_DA_IN2 and I2S_DA_IN3 in PQFP80 package) can be switched to asynchronous two channel mode (bit[2] set to 1 in the I2S CONFIGURATION register). The common clock is I2S_WS3 and I2S_CL3. No synchronous I2S interfaces are available in this mode.


Micronas 13

2.9. Digital Control I/O Pins

The static level of the digital input/output pinsD_CTR_I/O_0/1 is switchable between HIGH andLOW via the I2C-bus by means of the ACB register(see page 30). This enables the controlling of externalhardware switches or other devices via I2C-bus.

The Modus Register can set the digital input/outputpins to high impedance (see page 19). So the pins canbe used as input. The current state can be read out ofthe STATUS register (see page page 21).

2.10. Clock PLL Oscillator and Crystal Specifications

The DPL 4519G derives all internal system clocksfrom the 18.432 MHz oscillator. In I2S-slave mode ofthe synchronous interface, the clock is phase-locked tothe corresponding source.

For proper performance, the DPL clock oscillatorrequires a 18.432-MHz crystal. Note that for thephase-locked modes (I2S-slave), crystals with tightertolerance are required. The asynchronous I2S3 slaveinterface uses a different locking mechanism and doesnot require tighter crystal tolerances.


14 Micronas

3. Control Interface

3.1. I2C Bus Interface

3.1.1. Device and Subaddresses

The DPL 4519G is controlled via the I2C bus slaveinterface.

The IC is selected by transmitting one of theDPL 4519G device addresses. In order to allow up tothree DPL or MSP ICs to be connected to a single bus,an address select pin (ADR_SEL) has been imple-mented. With ADR_SEL pulled to high, low, or leftopen, the DPL 4519G responds to different deviceaddresses. A device address pair is defined as a writeaddress and a read address (see Table 3–1).

Writing is done by sending the device write address,followed by the subaddress byte, two address bytes,and two data bytes. Reading is done by sending thewrite device address, followed by the subaddress byteand two address bytes. Without sending a stop condi-tion, reading of the addressed data is completed bysending the device read address and reading twobytes of data. Refer to Section 3.1.4. for the I2C busprotocol and to Section 3.4. “Programming Tips” onpage 34 for proposals of DPL 4519G I2C telegrams.See Table 3–2 for a list of available subaddresses.

Besides the possibility of hardware reset, the DPL canalso be reset by means of the RESET bit in the CON-TROL register by the controller via I2C bus.

Due to the internal architecture of the DPL 4519G, theIC cannot react immediately to an I2C request. The

typical response time is about 0.3 ms. If the DPL can-not accept another complete byte of data until it hasperformed some other function (for example, servicingan internal interrupt), it will hold the clock line I2C_CLLOW to force the transmitter into a wait state. Thepositions within a transmission where this may happenare indicated by “Wait” in Section 3.1.4. The maximumwait period of the DPL during normal operation modeis less than 1 ms.

3.1.2. Internal Hardware Error Handling

In case of any internal hardware error (e.g. interruptionof the power supply of the DPL), the DPL’s wait periodis extended to 1.8 ms. After this time period elapses,the DPL releases data and clock lines.

Indicating and solving the error status:

To indicate the error status, the remaining acknowl-edge bits of the actual I2C-protocol will be left high.Additionally, bit[14] of CONTROL is set to one. TheDPL can then be reset via the I2C bus by transmittingthe reset condition to CONTROL.

Indication of reset:

Any reset, even caused by an unstable reset line etc.,is indicated in bit[15] of CONTROL.

A general timing diagram of the I2C bus is shown inFig. 4–21 on page 55.

Table 3–1: I2C Bus Device Addresses

ADR_SEL Low (connected to DVSS)

High (connected to DVSUP)

Left Open

Mode Write Read Write Read Write Read

DPL device address 80hex 81hex 84hex 85hex 88hex 89hex

Table 3–2: I2C Bus Subaddresses

Name Binary Value Hex Value Mode Function

CONTROL 0000 0000 00 Read/Write Write: Software reset of DPL (see Table 3–3)Read: Hardware error status of DPL

WR_DEM 0001 0000 10 Write write address demodulator

RD_DEM 0001 0001 11 Write read address demodulator

WR_DSP 0001 0010 12 Write write address DSP

RD_DSP 0001 0011 13 Write read address DSP


Micronas 15

3.1.3. Description of CONTROL Register

3.1.4. Protocol Description

Write to DSP

Read from DSP

Write to Control

Read from Control

Note: S = I2C-Bus Start Condition from masterP = I2C-Bus Stop Condition from masterACK = Acknowledge-Bit: LOW on I2C_DA from slave (= DPL, light gray) or master (= controller dark gray)NAK = Not Acknowledge-Bit: HIGH on I2C_DA from master (dark gray) to indicate ‘End of Read’

or from DPL indicating internal error stateWait = I2C-Clock line is held low, while the DPL is processing the I2C command.

This waiting time is max. 1 ms

Table 3–3: CONTROL as a Write Register

Name Subaddress Bit[15] (MSB) Bits[14:0]

CONTROL 00 hex 1 : RESET0 : normal

0

Table 3–4: CONTROL as a Read Register (only DPL 4519G-versions from A2 on)

Name Subaddress Bit[15] (MSB) Bit[14] Bits[13:0]

CONTROL 00 hex Reset status after last reading of CONTROL:0 : no reset occured1 : reset occured

Internal hardware status:0 : no error occured1 : internal error occured

not of interest

Reading of CONTROL will reset the bits[15,14] of CONTROL. After Power-on, bit[15] of CONTROL will be set; it must be read once to be resetted.

S writedevice

address

Wait ACK sub-addr ACK addr-byte high

ACK addr-byte low

ACK data-byte-high

ACK data-byte low

ACK P

S writedevice

address

Wait ACK sub-addr ACK addr-byte high

ACK addr-byte low

ACK S readdevice

address

Wait ACK data-byte-high

ACK data-byte low

NAK P

S writedevice

address

Wait ACK sub-addr ACK data-byte high

ACK data-byte low

ACK P

S writedevice

address

Wait ACK 00hex ACK S readdevice

address

Wait ACK data-byte-high

ACK data-byte low

NAK P


16 Micronas

Fig. 3–1: I2C bus protocol (MSB first; data must be stable while clock is high)

3.1.5. Proposals for General DPL 4519G I2C Telegrams

3.1.5.1. Symbols

daw write device address (80hex, 84hex or 88hex)dar read device address (81hex, 85hex or 89hex)< Start Condition> Stop Conditionaa Address Bytedd Data Byte

3.1.5.2. Write Telegrams

<daw 00 d0 00> write to CONTROL register<daw 10 aa aa dd dd> write data into demodulator<daw 12 aa aa dd dd> write data into DSP

3.1.5.3. Read Telegrams

<daw 00 <dar dd dd> read data from CONTROL register

<daw 11 aa aa <dar dd dd> read data from demodulator<daw 13 aa aa <dar dd dd> read data from DSP

3.1.5.4. Examples

<80 00 80 00> RESET DPL statically<80 00 00 00> Clear RESET<80 12 00 08 08 20> Set Main channel

source to I2S3 - L/R<80 12 00 00 73 00> Set Main volume to 0 dB

More examples of typical application protocols arelisted in Section 3.4. “Programming Tips” on page 34.

3.2. Start-Up Sequence: Power-Up and I2C Controlling

After POWER ON or RESET (see Fig. 4–21), the IC isin an inactive state. All registers are in the reset posi-tion, the analog outputs are muted. The controller hasto initialize all registers for which a non-default settingis necessary.

3.3. DPL 4519G Programming Interface

3.3.1. User Registers Overview

The DPL 4519G is controlled by means of user regis-ters. The complete list of all user registers is given inthe following tables. The registers are partitioned intotwo sections:

1. Subaddress 10hex for writing, 11hex for reading and

2. Subaddress 12hex for writing, 13hex for reading.

Write and read registers are 16-bit wide, whereby theMSB is denoted bit[15]. Transmissions via I2C bushave to take place in 16-bit words (two byte transfers,with the most significant byte transferred first). All writeregisters, except MODUS and I2S CONFIGURATION,are readable.

Unused parts of the 16-bit write registers must be zero.Addresses not given in this table must not beaccessed.

10

S P

I2C_DA

I2C_CL


Micronas 17

Table 3–5: List of DPL 4519G Write Registers

Write Register Address(hex)

Bits Description and Adjustable Range Reset See Page

I2C Subaddress = 10hex ; Registers are not readable

MODUS 00 30 [15:0] I2S options, D_CTR_I/O modes 00 00 19

I2S CONFIGURATION 00 40 [15:0] Configuration of I2S format 00 00 20

I2C Subaddress = 12hex ; Registers are all readable by using I2C Subaddress = 13hex

Volume Main channel 00 00 [15:8] [+12 dB ... −114 dB, MUTE] MUTE 24

[7:5][4:0]

1/8 dB Stepsmust be set to 0

000bin00000bin

Balance Main channel [L/R] 00 01 [15:8] [0...100 / 100% and 100 / 0...100%][−127...0 / 0 and 0 / −127...0 dB]

100%/100% 25

Balance mode Main [7:0] [Linear / logarithmic mode] linear mode

Bass Main channel 00 02 [15:8] [+20 dB ... −12 dB] 0 dB 26

Treble Main channel 00 03 [15:8] [+15 dB ... −12 dB] 0 dB 27

Loudness Main channel 00 04 [15:8] [0 dB ... +17 dB] 0 dB 28

Loudness filter characteristic [7:0] [NORMAL, SUPER_BASS] NORMAL

Volume Aux channel 00 06 [15:8] [+12 dB ... −114 dB, MUTE] MUTE 24

[7:5][4:0]

1/8 dB Stepsmust be set to 0

000bin00000bin

Volume SCART1 output channel 00 07 [15:8] [+12 dB ... −114 dB, MUTE] MUTE 29

Main source select 00 08 [15:8] [I2S1, I2S2, I2S3 ch1&2, I2S3 ch3&4,...] undefined 23

Main channel matrix [7:0] [SOUNDA, SOUNDB, STEREO, MONO] SOUNDA 23

Aux source select 00 09 [15:8] [I2S1, I2S2, I2S3 ch1&2, I2S3 ch3&4,...] undefined 23

Aux channel matrix [7:0] [SOUNDA, SOUNDB, STEREO, MONO] SOUNDA 23

SCART1 source select 00 0A [15:8] [I2S1, I2S2, I2S3 ch1&2, I2S3 ch3&4,...] undefined 23

SCART1 channel matrix [7:0] [SOUNDA, SOUNDB, STEREO, MONO] SOUNDA 23

I2S source select 00 0B [15:8] [I2S1, I2S2, I2S3 ch1&2, I2S3 ch3&4,...] undefined 23

I2S channel matrix [7:0] [SOUNDA, SOUNDB, STEREO, MONO] SOUNDA 23

Prescale I2S3 00 11 [15:8] [00hex ... 7Fhex] 10hex 21


ACB: SCART Switches a. D_CTR_I/O 00 13 [15:0] Bits [15:0] 00hex 30

Beeper 00 14 [15:0] [00hex ... 7Fhex]/[00hex ... 7Fhex] 00/00hex 30


Mode tone control 00 20 [15:8] [BASS/TREBLE, EQUALIZER] BASS/TREB 26

Equalizer Main ch. band 1 00 21 [15:8] [+12 dB ... −12 dB] 0 dB 27





Subwoofer level adjust 00 2C [15:8] [0 dB ... −30 dB, mute] 0 dB 29


18 Micronas

Balance Aux channel [L/R] 00 30 [15:8] [0...100 / 100% and 100 / 0...100%][−127...0 / 0 and 0 / −127...0 dB]

100 %/100 % 25

Balance mode Aux [7:0] [Linear mode / logarithmic mode] linear mode

Bass Aux channel 00 31 [15:8] [+20 dB ... −12 dB] 0 dB 26

Treble Aux channel 00 32 [15:8] [+15 dB ... −12 dB] 0 dB 27

Loudness Aux channel 00 33 [15:8] [0 dB ... +17 dB] 0 dB 28

Loudness filter characteristic [7:0] [NORMAL, SUPER_BASS] NORMAL

I2S3 Resorting 00 36 [15:8] through, straight eight, l/r eight, l/r six, l/r four, 2ch through

00hex 22

Surround source select 00 48 [15:8] [I2S1, I2S2, I2S3 ch1&2, I2S3 ch3&4,...] undefined 23

Surround channel matrix [7:0] [SOUNDA, SOUNDB, STEREO, MONO] SOUNDA 23

Spatial effect for surround processing 00 49 [15:8] [0% - 100%] 00hex 31

Virtual surround effect strength 00 4A [15:8] [0% - 100%] 00hex 31

Decoder matrix 00 4B [15:8] [ADAPTIVE/PASSIVE/EFFECT] 00hex 32

Surround reproduction [7:4] [REAR_SPEAKER/FRONT_SPEAKER/PANORAMA/3D_PANORAMA]

0hex 32

Center mode [3:0] [PHANTOM/NORMAL/WIDE/OFF] 0hex 32

Surround delay 00 4C [15:0] [5...31ms] 00hex 32

Noise Generator 00 4D [15:0] [NOISEL, NOISEC, NOISER, NOISES] 00hex 32

Table 3–6: List of DPL 4519G Read Registers

Read Register Address(hex)

Bits Description and Adjustable Range See Page

I2C Subaddress = 11hex ; Registers are not writable

STATUS 02 00 [15:0] Monitoring of settings e.g. D_CTR_I/O 21

I2C Subaddress = 13hex ; Registers are not writable

DPL hardware version code 00 1E [15:8] [00hex ... FFhex] 33

DPL major revision code [7:0] [00hex ... FFhex] 33

DPL product code 00 1F [15:8] [00hex ... FFhex] 33

DPL ROM version code [7:0] [00hex ... FFhex] 33

Table 3–5: List of DPL 4519G Write Registers, continued

Write Register Address(hex)

Bits Description and Adjustable Range Reset See Page


Micronas 19

3.3.2. Description of User Registers

3.3.2.1. Write Registers on I2C Subaddress 10hex

Table 3–7: Write Registers on I2C Subaddress 10hex

RegisterAddress

Function Name

MODUS

00 30hex MODUS Register

bit[15:8] 0 undefined, must be 0

bit[7] 0/1 active/tristate state of audio clock output pinAUD_CL_OUT

bit[6] word strobe alignment (synchronous I2S)0 WS changes at data word boundary1 WS changes one clock cycle in advance

bit[5] 0/1 master/slave mode of I2S interface

bit[4] 0/1 active/tristate state of I2S output pins

bit[3] state of digital output pins D_CTR_I/O_0 and _10 active: D_CTR_I/O_0 and _1 are output pins

(can be set by means of the ACB register) 1 tristate: D_CTR_I/O_0 and _1 are input pins

(level can be read out of STATUS[4,3])

bit[2:0] 0 undefined, must be 0

MODUS


20 Micronas

I2S CONFIGURATION

00 40hex I2S CONFIGURATION Register

I2S31)

bit[11] I2S data alignment (must be 0 if bit[2] = 1)0/1 left/right aligned

bit[10] wordstrobe polarity (must be 0 if bit[2] = 1)1 0 = right, 1 = left0 1 = right, 0 = left

bit[9] wordstrobe alignment (asynchronous I2S_3)0 WS changes at data word boundary1 WS changes one clock cycle in advance

bit[8] Sample Mode0/1 Two/Multi sample

bit[7:4] Word length of each data packet = (n−2)/2bit[3]=0, bit[8]=1 (multi-sample input mode)0111 16 bit1000 18 bit...1111 32 bit

bit[3]=0, bit[8]=0 (two-sample input mode)xxxx 16...32 bit, 18-bit valid

bit[3]=1, bit[8]=1 (multi-sample output mode)1111 32 bit

bit[3]=1, bit[8]=0 (two-sample output mode)0111 16 bit1111 32 bit

bit[3] I2S3 Mode1 output (I2S3 CL/WS active)0 input (I2S3 CL/WS tristate)

I2S1/2/3

bit[2] I2S1/2/3 Timing1 I2S3 timing for all I2S inputs (1/2/3)0 default mode

I2S Out

bit[1:0] I2S_CL frequency and I2S_DA_OUT sample length00 2 * 16 bit (1.536 MHz Clk)01 2 * 32 bit (3.072 MHz Clk)10 8 * 32 bit (12.288 MHz Clk)

I2S_CONFIG

I2S3_ALIGN

I2S3_WS_POL

I2S3_WS_MODE

I2S3_MSAMP

I2S3_MBIT

I2S3_MODE

I2S_TIMING

1) I2S_CL3 frequency depends on bit[8] and bits[7:4] as follows:[8] = 0, [7:4] = 0111 f = fs*(2*16)[8] = 0, [7:4] = else f = fs*(2*32)[8] = 1 f = fs*(8*32)

Table 3–7: Write Registers on I2C Subaddress 10hex, continued

RegisterAddress

Function Name


Micronas 21

3.3.2.2. Read Registers on I2C Subaddress 11hex

3.3.2.3. Write Registers on I2C Subaddress 12hex

Table 3–8: Read Registers on I2C Subaddress 11hex

RegisterAddress

Function Name

02 00hex STATUS Register

Contains the status of the D_CTR_I/O pins

bit[15:5] undefined

bit[4] 0/1 low/high level of digital I/O pin D_CTR_I/O_1

bit[3] 0/1 low/high level of digital I/O pin D_CTR_I/O_0

bit[2:0] undefined

STATUS

Table 3–9: Write Registers on I2C Subaddress 12hex

RegisterAddress

Function Name

PREPROCESSING

00 16hex00 12hex00 11hex

I2S1 PrescaleI2S2 PrescaleI2S3 Prescale

Defines the prescale value for digital I2S input signals

bit[15:8] 00hex off10hex 0 dB gain (recommendation)7Fhex +18 dB gain (maximum gain)

PRE_I2S1PRE_I2S2PRE_I2S3


22 Micronas

I2S3 RESORTING MATRIX

00 36hex I2S3 Resorting Matrix(not mentioned bit combinations must not be used)

Resorting of multichannel inputs

bit[15:8]

0000hex : 8 channel, “through”1,2,3,4,5,6,7,8 → 1,2,3,4,5,6,7,8Lt,Rt → Lt,Rt,--,--,--,--,--,-- Lt,Rt,Lvirtual,Rvirtual → Lt,Rt,Lvirtual,Rvirtual,--,--,--,--

0001hex : 8 channel, “straight eight”1,2,3,4,5,6,7,8 → 7,8,1,2,3,4,5,6L,R,SL,SR,C,LFE,Lt,Rt → Lt,Rt,L,R,SL,SR,C,LFE

0002hex : 8 channel, “left/right eight”, “MAS 3528E”1,2,3,4,5,6,7,8 → 4,8,1,5,2,6,3,7L,SL,C,Lt,R,SR,LFE,Rt → Lt,Rt,L,R,SL,SR,C,LFE

0003hex : 6 channel, “left/right six”1,2,3,4,5,6 → -,-,1,4,2,5,3,6L,SL,C,R,SR,LFE → --,--,L,R,SL,SR,C,LFE

0004hex : 4 channel, “left/right four”, ”External ProLogic”1,2,3,4 → -,-,1,3,4,4,2,-L,C,R,S → --,--,L,R,SL,SR,C,--

0010hex : 2 channel, “through”; “Internal ProLogic”1,2 → 1,2,+,+,+,+,+,+Lt,Rt → Lt,Rt,LPL,RPL,SPL,SPL,CPL,SUBPL“+”: channel will be replaced by internally generated signal“XPL”: internally generated signal

I2S3_Sort


RegisterAddress

Function Name


Micronas 23

SOURCE SELECT AND OUTPUT CHANNEL MATRIX

00 08hex00 09hex00 0Ahex00 0Bhex00 48hex

Source for:Main OutputAux OutputSCART1 DA OutputI2S OutputSurround Processing

bit[15:8] 5 I2S1 input

6 I2S2 input

7 I2S3 input channels 1&2 (e.g. Lt,Rt)1)

8 I2S3 input channels 3&4 (e.g. L,R)1) or Pro Logic processed L, R

9 I2S3 input channels 5&6 (e.g. SL,SR)1) or Pro Logic processed S, S (both channels same signal)

10 I2S3 input channels 7&8 (e.g. C,SUB)1) or Pro Logic processed C, SUB

1) exemplary channel assignment in a Micronas digital multichannel sound sys-tem with MAS 3528E and MSP 4450G.

SRC_MAINSRC_AUXSRC_SCART1SRC_I2SSRC_DPL

00 08hex00 09hex00 0Ahex00 0Bhex00 48hex

Channel Matrix for:Main OutputAux OutputSCART1 DA OutputI2S OutputSurround Processing

bit[7:0] 00hex Sound A Mono (or Left Mono)10hex Sound B Mono (or Right Mono)20hex Stereo (transparent mode)30hex Mono (L+R)/2

Usually the matrix modes should be set to “Stereo” (transparent).

MAT_MAINMAT_AUXMAT_SCART1MAT_I2SMAT_DPL


RegisterAddress

Function Name


24 Micronas

MAIN AND AUX PROCESSING

00 00hex00 06hex

Volume MainVolume Aux

bit[15:8] volume table with 1 dB step size7Fhex +12 dB (maximum volume)7Ehex +11 dB...74hex +1 dB73hex 0 dB72hex −1 dB...02hex −113 dB01hex −114 dB00hex Mute (reset condition)FFhex Fast Mute

bit[7:5] higher resolution volume table0 +0 dB1 +0.125 dB increase in addition to the volume table...7 +0.875 dB increase in addition to the volume table

bit[4:0] not usedmust be set to 0

With large scale input signals, positive volume settings may lead to signal clipping.

The DPL 4519G Main and Aux Volume function is divided into a digital and ananalog section. With Fast Mute, volume is reduced to mute position by digitalvolume only. Analog volume is not changed. This reduces any audible DC plops.To turn volume on again, the volume step that has been used before Fast Mutewas activated must be transmitted.

VOL_MAINVOL_AUX


RegisterAddress

Function Name


Micronas 25

00 01hex00 30hex

Balance Main ChannelBalance Aux Channel

bit[15:8] Linear Mode7Fhex Left muted, Right 100%7Ehex Left 0.8%, Right 100%...01hex Left 99.2%, Right 100%00hex Left 100%, Right 100%FFhex Left 100%, Right 99.2%...82hex Left 100%, Right 0.8%81hex Left 100%, Right muted

bit[15:8] Logarithmic Mode7Fhex Left −127 dB, Right 0 dB7Ehex Left −126 dB, Right 0 dB...01hex Left −1 dB, Right 0 dB00hex Left 0 dB, Right 0 dBFFhex Left 0 dB, Right −1 dB...81hex Left 0 dB, Right −127 dB80hex Left 0 dB, Right −128 dB

bit[3:0] Balance Mode0hex linear1hex logarithmic

Positive balance settings reduce the left channel without affecting the right channel; negative settings reduce the right channel leaving the left channel unaffected.

BAL_MAINBAL_AUX


RegisterAddress

Function Name


26 Micronas

00 20hex Tone Control Mode Main Channel

bit[15:8] 00hex bass and treble is activeFFhex equalizer is active

Defines whether Bass/Treble or Equalizer is activated for the Main channel. Bass/Treble and Equalizer cannot work simultaneously. If Equalizer is used, Bass and Treble coefficients must be set to zero and vice versa.

TONE_MODE

00 02hex00 31hex

Bass Main ChannelBass Aux Channel

bit[15:8] normal range60hex +12 dB58hex +11 dB...08hex +1 dB00hex 0 dBF8hex −1 dB...A8hex −11 dBA0hex −12 dB

bit[15:8] extended range7Fhex +20 dB78hex +18 dB70hex +16 dB68hex +14 dB

Higher resolution is possible: an LSB step in the normal range results in a gain step of about 1/8 dB, in the extended range about 1/4 dB.

With positive bass settings, internal clipping may occur even with overall volume less than 0 dB. This will lead to a clipped output signal. Therefore, it is not rec-ommended to set bass to a value that, in conjunction with volume, would result in an overall positive gain.

BASS_MAINBASS_AUX


RegisterAddress

Function Name


Micronas 27

00 03hex00 32hex

Treble Main ChannelTreble Aux Channel

bit[15:8] 78hex +15 dB70hex +14 dB...08hex +1 dB00hex 0 dBF8hex −1 dB...A8hex −11 dBA0hex −12 dB

Higher resolution is possible: an LSB step results in a gain step of about 1/8 dB.

With positive treble settings, internal clipping may occur even with overall vol-ume less than 0 dB. This will lead to a clipped output signal. Therefore, it is not recommended to set treble to a value that, in conjunction with volume, would result in an overall positive gain.

TREB_MAINTREB_AUX

00 21hex00 22hex00 23hex00 24hex00 25hex

Equalizer Main Channel Band 1 (below 120 Hz)Equalizer Main Channel Band 2 (center: 500 Hz)Equalizer Main Channel Band 3 (center: 1.5 kHz)Equalizer Main Channel Band 4 (center: 5 kHz)Equalizer Main Channel Band 5 (above: 10 kHz)

bit[15:8] 60hex +12 dB58hex +11 dB...08hex +1 dB00hex 0 dBF8hex −1 dB...A8hex −11 dBA0hex −12 dB

Higher resolution is possible: an LSB step results in a gain step of about 1/8 dB.

With positive equalizer settings, internal clipping may occur even with overall volume less than 0 dB. This will lead to a clipped output signal. Therefore, it is not recommended to set equalizer bands to a value that, in conjunction with vol-ume, would result in an overall positive gain.

EQUAL_BAND1EQUAL_BAND2EQUAL_BAND3EQUAL_BAND4EQUAL_BAND5


RegisterAddress

Function Name


28 Micronas

00 04hex00 33hex

Loudness Main ChannelLoudness Aux Channel

bit[15:8] Loudness Gain44hex +17 dB40hex +16 dB...04hex +1 dB00hex 0 dB

bit[7:0] Loudness Mode00hex normal (constant volume at 1 kHz)04hex Super Bass (constant volume at 2 kHz)

Higher resolution of Loudness Gain is possible: An LSB step results in a gain step of about 1/4 dB.

Loudness increases the volume of low- and high-frequency signals, while keep-ing the amplitude of the 1-kHz reference frequency constant. The intended loud-ness has to be set according to the actual volume setting. Because loudness introduces gain, it is not recommended to set loudness to a value that, in con-junction with volume, would result in an overall positive gain.

The corner frequency for bass amplification can be set to two different values. InSuper Bass mode, the corner frequency is shifted up. The point of constant vol-ume is shifted from 1 kHz to 2 kHz.

LOUD_MAINLOUD_AUX


RegisterAddress

Function Name


Micronas 29

00 2Chex Subwoofer Level Adjustment

bit[15:8] 00hex 0 dBFFhex −1 dB...E3hex −29 dBE2hex −30 dB...80hex Mute

SUBW_LEVEL

SCART OUTPUT CHANNEL

00 07hex Volume SCART1 Output Channel

bit[15:8] volume table with 1 dB step size7Fhex +12 dB (maximum volume)7Ehex +11 dB...74hex +1 dB73hex 0 dB72hex −1 dB...02hex −113 dB01hex −114 dB00hex Mute (reset condition)

bit[7:5] higher resolution volume table0 +0 dB1 +0.125 dB increase in addition to the volume table...7 +0.875 dB increase in addition to the volume table

bit[4:0] 01hex this must be 01hex

VOL_SCART1


RegisterAddress

Function Name


30 Micronas

SCART SWITCHES AND DIGITAL I/O PINS

00 13hex ACB Register

Defines the level of the digital output pins and the position of the SCART switches

bit[15] 0/1 low/high of digital output pin D_CTR_I/O_1 (MODUS[3]=0)

bit[14] 0/1 low/high of digital output pin D_CTR_I/O_0 (MODUS[3]=0)

bit[13:5] SCART1 Output Selectxx00xx x0x SCART3 input to SCART1 output (RESET position)xx01xx x0x SCART2 input to SCART1 outputxx10xx x0x MONO input to SCART1 outputxx11xx x0x SCART1 DA to SCART1 outputxx01xx x1x SCART1 input to SCART1 outputxx10xx x1x SCART4 input to SCART1 outputxx11xx x1x mute SCART1 output

bit[13:5] SCART2 Output Select00xxxx 0xx SCART1 DA to SCART2 output (RESET position)01xxxx 0xx SCART1 input to SCART2 output10xxxx 0xx MONO input to SCART2 output01xxxx 1xx SCART2 input to SCART2 output10xxxx 1xx SCART3 input to SCART2 output11xxxx 1xx SCART4 input to SCART2 output11xxxx 0xx mute SCART2 output

The RESET position becomes active at the time of the first write transmissionon the control bus to the audio processing part. By writing to the ACB registerfirst, the RESET state can be redefined.

ACB_REG

BEEPER

00 14hex Beeper Volume and Frequency

bit[15:8] Beeper Volume00hex off7Fhex maximum volume

bit[7:0] Beeper Frequency01hex 16 Hz (lowest)40hex 1 kHzFFhex 4 kHz

BEEPER


RegisterAddress

Function Name


Micronas 31

SURROUND PROCESSING

00 49hex Spatial Effects for Surround Processing

bit[15:8] Spatial Effect Strength7Fhex Enlargement 100%3Fhex Enlargement 50%...01hex Enlargement 1.5%00hex Effect off

bit[7:0] 00hex must be 0

Increases the perceived basewidth of the reproduced left and right front chan-nels. Recommended value: 50% = 40hex.

SUR_SPAT

00 4Ahex Virtual Surround Effect Strength

bit[15:8] Virtual Surround Effect Strength7Fhex Effect 100%3Fhex Effect 50%

...01hex Effect 1.5%00hex Effect off


Strength of the surround effect in PANORAMA or 3D-PANORAMA mode. In other Surround Reproduction Modes this value must be set to 0. Recommended value: 66% = 54hex.

SUR_3DEFF


RegisterAddress

Function Name


32 Micronas

00 4Bhex Surround Processing Mode

bit[15:8] Decoder Matrix00hex ADAPTIVE (for Dolby Surround Pro Logic and Virtual

Surround)10hex PASSIVE (for MSS, Micronas Surround Sound)20hex EFFECT (used for special effects and monophonic

signals)

bit[7:4] Surround Reproduction

0hex REAR_SPEAKER: The surround signal is reproduced by rear speakers.

3hex FRONT_SPEAKER: The surround signal is redirected to the front channels. There is no physical rear speaker con-nected.

5hex PANORAMA: The surround signal is processed and redi-rected to the left and right front speakers in order to create the illusion of a virtual rear speaker, although no physical rear speaker is connected.

6hex 3D-PANORAMA: The surround signal is processed and redirected to the left and right front speakers in order to create the illusion of a virtual rear speaker, although no physical rear speaker is connected.

bit[3:0] Center Mode

0hex PHANTOM mode (no Center speaker connected)1hex NORMAL mode (small Center speaker)2hex WIDE mode (large Center speaker)3hex OFF mode (Center output of the Surround Decoder is

discarded. Useful only in special effect modes)

SUR_MODE

DEC_MAT

SUR_REPRO

C_MODE

00 4Chex Surround Delay

bit[15:8] 05hex 5 ms delay in surround path (lowest)06hex 6 ms delay in surround path...1Fhex 31 ms delay in surround path (highest))


For Dolby Surround Pro Logic designs, only 20 ms fixed or 15-30 ms variable delay must be used. This register has no effect in 3D-PANORAMA and PAN-ORAMA mode.

SUR_DELAY

00 4Dhex Noise Generator

bit[15:8] 00hex Noise generator off80hex Noise generator on

bit[7:0] A0hex Noise on left channelB0hex Noise on center channelC0hex Noise on right channelD0hex Noise on surround channel

Determines the active channel for the noise generator.

SUR_NOISE


RegisterAddress

Function Name


Micronas 33

3.3.2.4. Read Registers on I2C Subaddress 13hex

Table 3–10: Read Registers on I2C Subaddress 13hex

RegisterAddress

Function Name

DPL 4519G VERSION READOUT Registers

00 1Ehex DPL Hardware Version Code

bit[15:8] 01hex DPL 4519G-A1

A change in the hardware version code defines hardware optimizations thatmay have influence on the chip’s behavior. The readout of this register is iden-tical to the hardware version code in the chip’s imprint.

DPL_HARD

DPL Family Code

bit[7:4] 3hex DPL 4519G-A1

DPL_FAMILY

DPL Major Revision Code

bit[3:0] 7hex DPL 4519G-A1

DPL_REVISION

00 1Fhex DPL Product Code

bit[15:8] 13hex DPL 4519G - A1

By means of the DPL-Product Code, the control processor is able to decidewhich TV sound standards have to be considered.

DPL ROM Version Code

bit[7:0] 41hex DPL 4519G - A142hex DPL 4519G - A2

A change in the ROM version code defines internal software optimizations,that may have influence on the chip’s behavior, e.g. new features may havebeen included. While a software change is intended to create no compatibilityproblems, customers that want to use the new functions can identify newDPL 4519G versions according to this number.

DPL_PRODUCT

DPL_ROM


34 Micronas

3.4. Programming Tips

This section describes the preferred method for initial-izing the DPL 4519G. The initialization is grouped intofour sections: analog signal path, input processing forI2S, and output processing. See Fig. 2–1 on page 7 fora complete signal flow.

SCART Signal Path

1. Select the source for each analog SCART output with the ACB register.

I2S Inputs

1. Select preferred prescale for I2S inputs (set to 0 dB after RESET).

2. Select I2S3 Resorting matrix according to the chan-nel order of your decoding device (e.g. for MAS 3528E chose mode 02hex)

Output Channels

1. Select the source channel and matrix for each out-put.

2. Set audio baseband features

3. Select volume for each output.

3.5. Examples of Minimum Initialization Codes

Initialization of the DPL 4519G according to these list-ings reproduces sound of the selected standard on theMain output. All numbers are hexadecimal. The exam-ples have the following structure:

1. Perform an I2C controlled reset of the IC.

2. Write MODUS register

3. Set Source Selection for Main channel (with matrix set to STEREO).

4. Set Volume Main channel to 0 dB.

3.5.1. Micronas Dolby Digital chipset (with MAS 3528E)

<84 00 80 00> // Softreset

<84 00 00 00>

<84 10 00 30 00 20> // MODUS-Register: I2S slave

<84 10 00 40 01 F2> // I2S-config-Register

<84 12 00 36 00 02> // I2S3 Resorting matrix, Mode 2

<84 12 00 0B 07 20> // Source Sel. I2S_out = I2S3 - Lt/Rt

<84 12 00 08 08 20> // Source Sel. Main_out = I2S3 - L/R

<84 12 00 00 73 00> // Main Volume 0 dB


Micronas 35

4. Specifications

4.1. Outline Dimensions

Fig. 4–1:80-Pin Plastic Quad Flat Pack (PQFP80)Weight approximately 1.61 gDimensions in mm

Fig. 4–2:64-Pin Plastic Low-Profile Quad Flat Pack (PLQFP64)Weight approximately 0.35 gDimensions in mm

15 x

0.8

= 1

2.0

0.1

±

0.8

0.8

4164

241

65

80

40

25

0.13 ±0.2

SPGS705000-3(P80)/1E

23.2 0.15±

17.2

0.15

±

20 0.1±

140.

1±

23 x 0.8 = 18.4 0.1±0.17 0.04±

0.37

0.04

±

1.3 0.05±

2.7 0.1±

10 0.1±1.75

1.75

49

64

1 16

17

32

3348

D0025/3E

0.5

0.5

0.112 0.2±1.5 0.1±

1.4 0.05±

120.

2±

100.

1±

0.145 0.055±

0.22

0.05

±

15 x 0.5 = 7.5 0.1±

15 x

0.5

= 7

.50.

1±


36 Micronas

Fig. 4–3:64-Pin Plastic Shrink Dual-Inline Package(PSDIP64)Weight approximately 9.0 gDimensions in mm

1 32

3364

57.7±0.1

0.8

±0.2

3.8

±0.1

3.2

±0.2

1.778

1±0.05

31 x 1.778 = 55.1±0.1

0.48±0.0620.3±0.5

0.28±0.06

18±0.05

19.3±0.1

SPGS703000-1(P64)/1E


Micronas 37

4.2. Pin Connections and Short Descriptions

NC = not connected (leave vacant for future compatibility reasons)TP = Test Pin (leave vacant - pin is used for production test only)LV = leave vacantX = obligatory; connect as described in application circuit diagramAHVSS: connect to AHVSS

Pin No. Pin Name Type Connection(if not used)

Short Description

PQFP80-pin

PLQFP64-pin

PSDIP64-pin

1 64 8 NC LV Not connected

2 1 9 I2C_CL IN/OUT X I2C clock

3 2 10 I2C_DA IN/OUT X I2C data

4 3 11 I2S_CL IN/OUT LV I2S clock

5 4 12 I2S_WS IN/OUT LV I2S word strobe

6 5 13 I2S_DA_OUT OUT LV I2S data output

7 6 14 I2S_DA_IN1 IN LV I2S1 data input

8 7 15 TP LV Test pin



11 − − DVSUP X Digital power supply +5 V

12 − − DVSUP X Digital power supply +5 V

13 10 18 DVSUP X Digital power supply +5 V

14 − − DVSS X Digital ground

15 − − DVSS X Digital ground

16 11 19 DVSS X Digital ground

− 12 20 I2S_DA_IN2/3 IN LV I2S2/3-data input

17 − − I2S_DA_IN2 IN LV PQFP80: pin 22 separate I2S_DA_IN3


19 14 22 I2S_CL3 IN LV I2S3 clock

20 15 23 I2S_WS3 IN LV I2S3 word strobe

21 16 24 RESETQ IN X Power-on-reset

22 − − I2S_DA_IN3 IN LV I2S3-data input

23 − − NC LV Not connected

24 17 25 DACA_R OUT LV Aux out, right

25 18 26 DACA_L OUT LV Aux out, left


38 Micronas

26 19 27 VREF2 X Reference ground 2

27 20 28 DACM_R OUT LV Loudspeaker out, right

28 21 29 DACM_L OUT LV Loudspeaker out, left


30 23 31 DACM_SUB OUT LV Subwoofer output



33 25 33 SC2_OUT_R OUT LV SCART output 2, right

34 26 34 SC2_OUT_L OUT LV SCART output 2, left

35 27 35 VREF1 X Reference ground 1

36 28 36 SC1_OUT_R OUT LV SCART output 1, right

37 29 37 SC1_OUT_L OUT LV SCART output 1, left

38 30 38 CAPL_A X Volume capacitor AUX

39 31 39 AHVSUP X Analog power supply 8.0 V

40 32 40 CAPL_M X Volume capacitor MAIN



43 − − AHVSS X Analog ground

44 33 41 AHVSS X Analog ground

45 34 42 AGNDC X Analog reference voltage


47 35 43 SC4_IN_L IN LV SCART 4 input, left

48 36 44 SC4_IN_R IN LV SCART 4 input, right

49 37 45 ASG AHVSS Analog Shield Ground









Short Description

PQFP80-pin

PLQFP64-pin

PSDIP64-pin


Micronas 39




60 47 55 MONO_IN IN LV Mono input

61 − − AVSS X Analog ground

62 48 56 AVSS X Analog ground



65 − − AVSUP X Analog power supply +5 V

66 49 57 AVSUP X Analog power supply +5 V




70 53 61 TESTEN IN AVSS Test pin

71 54 62 XTAL_IN IN X Crystal oscillator

72 55 63 XTAL_OUT OUT X / LV Crystal oscillator (See also 4.3. Pin descriptions)


74 57 1 AUD_CL_OUT OUT LV Audio clock output (18.432 MHz)

- − − NC LV Not connected



77 60 4 D_CTR_I/O_1 IN/OUT LV D_CTR_I/O_1

78 61 5 D_CTR_I/O_0 IN/OUT LV D_CTR_I/O_0

79 62 6 ADR_SEL IN X I2C Bus address select

80 63 7 STANDBYQ IN X Stand-by (low-active)


Short Description

PQFP80-pin

PLQFP64-pin

PSDIP64-pin


40 Micronas

4.3. Pin Descriptions

Pin numbers refer to the 80-pin PQFP package

Pin 1, NC – Pin not connected.

Pin 2, I2C_CL – I2C Clock Input/Output (Fig. 4–8)Via this pin, the I2C-bus clock signal has to be sup-plied. The signal can be pulled down by the DPL incase of wait conditions.

Pin 3, I2C_DA – I2C Data Input/Output (Fig. 4–8)Via this pin, the I2C-bus data is written to or read from the DPL.

Pin 4, I2S_CL – I2S Clock Input/Output (Fig. 4–11)Clock line for the I2S bus. In master mode, this line isdriven by the DPL; in slave mode, an external I2S clockhas to be supplied.

Pin 5, I2S_WS – I2S Word Strobe Input/Output (Fig. 4–11)Word strobe line for the I2S bus. In master mode, thisline is driven by the DPL; in slave mode, an externalI2S word strobe has to be supplied.

Pin 6, I2S_DA_OUT1 – I2S Data Output (Fig. 4–7)Output of digital serial sound data of the DPL on theI2S bus.

Pin 7, I2S_DA_IN1 – I2S Data Input 1 (Fig. 4–9)First input of digital serial sound data to the DPL viathe I2S bus.

Pin 8, 9, 10, TP– Test pins

Pins 11, 12, 13, DVSUP* – Digital Supply VoltagePower supply for the digital circuitry of the DPL. Mustbe connected to a power supply.

Pins 14, 15, 16, DVSS* – Digital GroundGround connection for the digital circuitry of the DPL.

Pin 17, I2S_DA_IN2 – I2S Data Input 2 (Fig. 4–9)Second input of digital serial sound data to the DPL viathe I2S bus. In all packages except PQFP-80-pin thispin is also connected to the asynchronous I2S inter-face 3.

Pins 18, NC – Pin not connected.

Pins 19, I2S_CL3 – I2S Clock Input (Fig. 4–9)Clock line for the I2S bus. Since only a slave mode isavailable an external I2S clock has to be supplied.

Pins 20, I2S_WS3 – I2S Word Strobe Input (Fig. 4–9)Word strobe line for the I2S bus. Since only a slavemode is available an external I2S word strobe has tobe supplied.

Pin 21, RESETQ – Reset Input (Fig. 4–9)In the steady state, high level is required. A low levelresets the DPL 4519G.

Pin 22, I2S_DA_IN3 – I2S Data Input 3 (Fig. 4–9)Asynchronous input of digital serial sound data to theDPL via the I2S bus.

Pins 23, NC – Pin not connected.

Pins 24, 25, DACA_R/L – Aux Outputs (Fig. 4–16)Output of the aux signal. A 1 nF capacitor to AHVSSmust be connected to these pins. The DC offset onthese pins depends on the selected aux volume.

Pin 26, VREF2 – Reference Ground 2Reference analog ground. This pin must be connectedseparately to ground (AHVSS). VREF2 serves as aclean ground and should be used as the reference foranalog connections to the Main and AUX outputs.

Pins 27, 28, DACM_R/L – Main Outputs (Fig. 4–16)Output of the Main signal. A 1 nF capacitor to AHVSSmust be connected to these pins. The DC offset onthese pins depends on the selected Main volume.

Pin 29 NC – Pin not connected.

Pin 30, DACM_SUB – Subwoofer Output (Fig. 4–16)Output of the subwoofer signal. A 1-nF capacitor toAHVSS must be connected to this pin. Due to the lowfrequency content of the subwoofer output, the valueof the capacitor may be increased for better suppres-sion of high-frequency noise. The DC offset on this pindepends on the selected Main volume.

Pins 31, 32 NC – Pin not connected.

Pins 33, 34, SC2_OUT_R/L – SCART2 Outputs (Fig. 4–18)Output of the SCART2 signal. Connections to thesepins must use a 100-Ω series resistor and are intendedto be AC-coupled.

Pin 35, VREF1 – Reference Ground 1Reference analog ground. This pin must be connectedseparately to ground (AHVSS). VREF1 serves as aclean ground and should be used as the reference foranalog connections to the SCART outputs.

Pins 36, 37, SC1_OUT_R/L – SCART1 Outputs (Fig. 4–18)Output of the SCART1 signal. Connections to thesepins must use a 100-Ω series resistor and are intendedto be AC-coupled.


Micronas 41

Pin 38, CAPL_A – Volume Capacitor Aux (Fig. 4–13)A 10-µF capacitor to AHVSUP must be connected tothis pin. It serves as a smoothing filter for volumechanges in order to suppress audible plops. The valueof the capacitor can be lowered to 1-µF if fasterresponse is required. The area encircled by the tracelines should be minimized; keep traces as short aspossible. This input is sensitive for magnetic induction.

Pin 39, AHVSUP* – Analog Power Supply High Volt-agePower is supplied via this pin for the analog circuitry ofthe DPL. This pin must be connected to the +8 V sup-ply. (+5 V-operation is possible with restrictions in per-formance)

Pin 40, CAPL_M – Volume Capacitor Loudspeakers(Fig. 4–13)A 10-µF capacitor to AHVSUP must be connected tothis pin. It serves as a smoothing filter for volumechanges in order to suppress audible plops. The valueof the capacitor can be lowered to 1 µF if fasterresponse is required. The area encircled by the tracelines should be minimized; keep traces as short aspossible. This input is sensitive for magnetic induction.

Pins 41, 42, NC – Pins not connected.

Pins 43, 44, AHVSS* – Ground for Analog Power Sup-ply High VoltageGround connection for the analog circuitry of the DPL.

Pin 45, AGNDC – Internal Analog Reference VoltageThis pin serves as the internal ground connection forthe analog circuitry. It must be connected to the VREFpins with a 3.3-µF and a 100-nF capacitor in parallel.This pins shows a DC level of typically 3.73 V.


Pins 47, 48, SC4_IN_L/R – SCART4 Inputs (Fig. 4–15)The analog input signal for SCART4 is fed to this pin.Analog input connection must be AC-coupled.

Pin 49, ASG* – Analog Shield GroundAnalog ground (AHVSS) should be connected to thispin to reduce cross-coupling between SCART inputs.

Pins 50, 51, SC3_IN_L/R – SCART3 Inputs (Fig. 4–15)The analog input signal for SCART3 is fed to this pin.Analog input connection must be AC-coupled.


Pins 53, 54 SC2_IN_L/R – SCART2 Inputs (Fig. 4–15)The analog input signal for SCART2 is fed to this pin.Analog input connection must be AC-coupled.


Pins 56, 57 SC1_IN_L/R – SCART1 Inputs (Fig. 4–15)The analog input signal for SCART1 is fed to this pin.Analog input connection must be AC-coupled.

Pin 58, NC – Pin not connected


Pin 60 MONO_IN – Mono Input (Fig. 4–15)The analog mono input signal is fed to this pin AC-cou-pled.

Pins 61, 62, AVSS* – Analog Power Supply VoltageGround connection for the analog IF input circuitry ofthe DPL.


Pins 65, 66, AVSUP* – Analog Power Supply VoltagePower is supplied via this pin for the analog IF input cir-cuitry of the DPL. This pin must be connected to the+5 V supply.

Pin 67, 68, 69, NC – Pin not connected.

Pin 70, TESTEN – Test Enable Pin (Fig. 4–9)This pin enables factory test modes. For normal opera-tion, it must be connected to ground.

Pins 71, 72 XTAL_IN, XTAL_OUT – Crystal Input andOutput Pins (Fig. 4–12)These pins are connected to an 18.432 MHz crystaloscillator which is digitally tuned by integrated capaci-tances. An external clock can be fed into XTAL_IN(leave XTAL_OUT vacant in this case). The audioclock output signal AUD_CL_OUT is derived from theoscillator. External capacitors at each crystal pin toground (AVSS) are required. It should be verified bylayout, that no supply current for the digital circuitry isflowing through the ground connection point.

Pin 73, TP – This pin is needed for factory tests. Fornormal operation, it must be left vacant.

Pin 74, AUD_CL_OUT – Audio Clock Output (Fig. 4–12)This is the 18.432 MHz main clock output.


Pins 77, 78, D_CTR_I/O_1/0 – Digital Control Input/Output Pins (Fig. 4–11)General purpose input/output pins.


42 Micronas

Pin 79, ADR_SEL – I2C Bus Address Select (Fig. 4–10)This pin selects the device address for the DPL. (seeTable 3–1).

Pin 80, STANDBYQ – Stand-byIn normal operation, this pin must be High. If the DPLis switched to ‘Stand-by’-mode , the SCART switchesmaintain their position and function. (seeSection 2.7.2.)

* Application Note:

All ground pins should be connected to one low-resis-tive ground plane.

All supply pins should be connected separately withshort and low-resistive lines to the power supply.

Decoupling capacitors from DVSUP to DVSS, AVSUPto AVSS, and AHVSUP to AHVSS are recommendedas closely as possible to these pins. Decoupling ofDVSUP and DVSS is most important. We recommendusing more than one capacitor. By choosing differentvalues, the frequency range of active decoupling canbe extended. In our application boards we use: 220 pF,470 pF, 1.5 nF, and 10 µF. The capacitor with the low-est value should be placed nearest to the pins.

The ASG pins should be connected as closely as pos-sible to the IC ground. They are intended for leadingwith the SCART signals as shield lines and should notbe connected to ground at the SCART-connectoragain.


Micronas 43

4.4. Pin Configurations

Fig. 4–4: 80-pin PQFP package

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

251 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41AVSUP

AVSUP

NC

NC

NC

TESTEN

XTAL_IN

XTAL_OUT

TP

AUD_CL_OUT

NC

NC

D_CTR_I/O_1

D_CTR_I/O_0

ADR_SEL

STANDBYQ

CAPL_M

AHVSUP

CAPL_A

SC1_OUT_L

SC1_OUT_R

VREF1

SC2_OUT_L

SC2_OUT_R

NC

NC

DACM_SUB

NC

DACM_L

DACM_R

VREF2

DACA_L

NC

AVSS

AVSS

MONO_IN

NC

NC

SC1_IN_R

SC1_IN_L

ASG

NC

SC2_IN_R

SC2_IN_L ASG

SC3_IN_R

SC3_IN_L

ASG

SC4_IN_R

SC4_IN_L

NC

AGNDC

AHVSS

AHVSS

NC

NC

I2C_CL

I2C_DA

I2S_CL

I2S_WS

I2S_DA_OUT

I2S_DA_IN1

NC

NC

NC

NC

DVSUP

DVSUP DVSUP

DVSS

DVSS

DVSS

I2S_DA_IN2

NC

I2S_CL3

I2S_WS3

RESETQ

I2S_DA_IN3

NC

DACA_R

DPL 4519G


44 Micronas

Fig. 4–5: 64-pin PLQFP package

49AVSUP

50NC

51NC

52NC

53TESTEN

54XTAL_IN

55XTAL_OUT

56TP

57AUD_CL_OUT

58NC

59NC

60D_CTR_I/O_1

61C_CTR_I/O_0

62ADR_SEL

63STANDBYQ

64NC

CAPL_M32

AHVSUP31

CAPL_A30

SC1_OUT_L29

SC1_OUT_R28

VREF127

SC2_OUT_L26

SC2_OUT_R25

NC24

DACM_SUB23

NC22

DACM_L21

DACM_R20

VREF219

DACA_L18

DACA_R17

MONO_IN

NC

SC1_IN_R

SC1_IN_L

ASG

SC2_IN_R

SC2_IN_L

AVSS

ASG

SC3_IN_R

SC3_IN_L

ASG

SC4_IN_R

SC4_IN_L

AGNDC

AHVSS

I2C_DA

I2S_CL

I2S_WS

I2S_DA_OUT

I2S_DA_IN1

TP

TP

I2C_CL

TP

DVSUP

DVSS

I2S_DA_IN2/3

NC

I2S_CL3

I2S_WS3

RESETQ

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

DPL 4519G


Micronas 45

Fig. 4–6: 64-pin PSDIP package

4.5. Pin Circuits

Pin numbers refer to the PQFP80 package.

Fig. 4–7: Output Pin 6(I2S_DA_OUT)

Fig. 4–8: Input/Output Pins 2 and 3(I2C_CL, I2C_DA)

Fig. 4–9: Input Pins 7, 17, 21, 22, 70, and 80(I2S_DA_IN1..3, RESETQ, TESTEN, STANDBYQ )

Fig. 4–10: Input Pin 79 (ADR_SEL)

1AUD_CL_OUT

2NC

3NC

4D_CTR_I/O_1

5D_CTR_I/O_0

6ADR_SEL

7STANDBYQ

8NC

9I2C_CL

10I2C_DA

11I2S_CL

12I2S_WS

13I2S_DA_OUT

14I2S_DA_IN1

15TP

16TP

TP64

XTAL_OUT63

XTAL_IN62

TESTEN61

NC60

NC59

NC58

AVSUP57

AVSS56

MONO_IN55

NC54

SC1_IN_R53

SC1_IN_L52

ASG51

SC2_IN_R50

SC2_IN_L49

17TP

18DVSUP

19DVSS

20I2S_DA_IN2/3

21NC

22I2S_CL3

23I2S_WS3

24RESETQ

25DACA_R

26DACA_L

ASG48

SC3_IN_R47

SC3_IN_L46

ASG45

SC4_IN_R44

SC4_IN_L43

AGNDC42

AHVSS41

CAPL_M40

AHVSUP39

DP

L 4

519G

VREF2

DACM_R

DACM_L

NC

DACM_SUB

NC

38

37

36

35

34

33

27

28

29

30

31

32

CAPL_A

SC1_OUT_L

SC1_OUT_R

VREF1

SC2_OUT_L

SC2_OUT_R

DVSUP

P

N

GND

N

GND

ADR_SELGND

DVSUP

23 kΩ

23 kΩ


46 Micronas

Fig. 4–11: Input/Output Pins 4, 5, 77, and 78(I2S_CL, I2S_WS, D_CTR_I/O_1, D_CTR_I/O_0)

Fig. 4–12: Output/Input Pins 71, 72, and 74(XTALIN, XTALOUT, AUD_CL_OUT)

Fig. 4–13: Capacitor Pins 38 and 40 (CAPL_A, CAPL_M)

Fig. 4–14: Input Pin 60 (MONO_IN)

Fig. 4–15: Input Pins 47, 48, 50, 51, 53, 54, 56, and 57 (SC4-1_IN_L/R)

Fig. 4–16: Output Pins 24, 25, 27, 28 and 30(DACA_R/L, DACM_R/L, DACM_SUB)

Fig. 4–17: Pin 45 (AGNDC)

Fig. 4–18: Output Pins 33, 34, 36, and 37(SC_2_OUT_R/L, SC_1_OUT_R/L)

DVSUP

P

N

GND

3−30 pF

2.5 V

500 kΩ

3−30 pF

P

N

Gain=0.5

0...2 V

≈ 3.75 V24 kΩ

≈ 3.75 V40 kΩ

AHVSUP

0...1.2 mA

3.3 kΩ

≈ 3.75 V125 kΩ

26 pF

120 kΩ

300 Ω

≈ 3.75 V


Micronas 47

4.6. Electrical Characteristics

4.6.1. Absolute Maximum Ratings

Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. Thisis a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated inthe “Recommended Operating Conditions/Characteristics” of this specification is not implied. Exposure to absolutemaximum ratings conditions for extended periods may affect device reliability.

Symbol Parameter Pin Name Min. Max. Unit

TA Ambient Operating Temperature − 0 701) °C

TS Storage Temperature − −40 125 °C

VSUP1 First Supply Voltage AHVSUP −0.3 9.0 V

VSUP2 Second Supply Voltage DVSUP −0.3 6.0 V

VSUP3 Third Supply Voltage AVSUP −0.3 6.0 V

dVSUP23 Voltage between AVSUP and DVSUP

AVSUP,DVSUP

−0.5 0.5 V

PTOT Package Power DissipationPSDIP64PQFP80PLQFP64

130010009601)

mW

VIdig Input Voltage, all Digital Inputs −0.3 VSUP2+0.3 V

IIdig Input Current, all Digital Pins − −20 +20 mA2)

VIana Input Voltage, all Analog Inputs SCn_IN_s,3)

MONO_IN−0.3 VSUP1+0.3 V

IIana Input Current, all Analog Inputs SCn_IN_s,3)

MONO_IN−5 +5 mA2)

IOana Output Current, all SCART Outputs SCn_OUT_s3) 4), 5) 4), 5)

IOana Output Current, all Analog Outputs except SCART Outputs

DACp_s3) 4) 4)

ICana Output Current, other pins connected to capacitors

CAPL_p,3)

AGNDC

4) 4)

1) PLQFP64: 65 °C2) positive value means current flowing into the circuit3) “n” means “1”, “2”, “3”, or “4”, “s” means “L” or “R”, “p” means “M” or “A”4) The analog outputs are short circuit proof with respect to First Supply Voltage and ground.5) Total chip power dissipation must not exceed absolute maximum rating.


48 Micronas

4.6.2. Recommended Operating Conditions (TA = 0 to 70 °C)

4.6.2.1. General Recommended Operating Conditions

4.6.2.2. Analog Input and Output Recommendations

Symbol Parameter Pin Name Min. Typ. Max. Unit

VSUP1 First Supply Voltage(8-V Operation)

AHVSUP 7.6 8.0 8.7 V

First Supply Voltage (5-V Operation)

4.75 5.0 5.25 V

VSUP2 Second Supply Voltage DVSUP 4.75 5.0 5.25 V

VSUP3 Third Supply Voltage AVSUP 4.75 5.0 5.25 V

tSTBYQ1 STANDBYQ Setup Time before Turn-off of Second Supply Voltage

STANDBYQ,DVSUP

1 µs


CAGNDC AGNDC-Filter-Capacitor AGNDC −20% 3.3 µF

Ceramic Capacitor in Parallel −20% 100 nF

CinSC DC-Decoupling Capacitor in front of SCART Inputs

SCn_IN_s1) −20% 330 nF

VinSC SCART Input Level 2.0 VRMS

VinMONO Input Level, Mono Input MONO_IN 2.0 VRMS

RLSC SCART Load Resistance SCn_OUT_s1) 10 kΩ

CLSC SCART Load Capacitance 6.0 nF

CVMA Main/AUX Volume Capacitor CAPL_M,CAPL_A

10 µF

CFMA Main/AUX Filter Capacitor DACM_s,DACA_s1)

−10% 1 +10% nF

1) “n” means “1”, “2”, or “3”, “s” means “L” or “R”, “p” means “M” or “A”


Micronas 49

4.6.2.3. Crystal Recommendations


General Crystal Recommendations

fP Crystal Parallel Resonance Fre-quency at 12 pF Load Capacitance

18.432 MHz

RR Crystal Series Resistance 8 25 Ω

C0 Crystal Shunt (Parallel) Capacitance 6.2 7.0 pF

CL External Load Capacitance1) XTAL_IN,XTAL_OUT

PSDIP approx. 1.5P(L)QFP approx. 3.3

pFpF

Crystal Recommendations for Master-Slave Applications (DPL Clock must perform synchronization to I2S clock)

fTOL Accuracy of Adjustment −20 +20 ppm

DTEM Frequency Variation versus Temperature

−20 +20 ppm

C1 Motional (Dynamic) Capacitance 19 24 fF

fCL Required Open Loop Clock Frequency (Tamb = 25 °C)

AUD_CL_OUT 18.431 18.433 MHz

Crystal Recommendations for other Applications (No synchronization to I2S clock possible)

fTOL Accuracy of Adjustment −100 +100 ppm

DTEM Frequency Variation versus Temperature

−50 +50 ppm

fCL Required Open Loop Clock Frequency (Tamb = 25 °C)

AUD_CL_OUT 18.429 18.435 MHz

Amplitude Recommendation for Operation with External Clock Input (Cload after reset typ. 22 pF)

VXCA External Clock Amplitude XTAL_IN 0.7 Vpp

1)External capacitors at each crystal pin to ground are required. They are necessary to tune the open-loop fre-quency of the internal PLL and to stabilize the frequency in closed-loop operation. Due to different layouts, the accurate capacitor size should be determined with the customer PCB. The sug-gested values (1.5...3.3 pF) are figures based on experience and should serve as “start value”.

To define the capacitor size, reset the DPL without transmitting any further I2C telegrams. Measure the fre-quency at AUD_CL_OUT-pin. Change the capacitor size until the free running frequency matches 18.432 MHzas closely as possible. The higher the capacity, the lower the resulting clock frequency.


50 Micronas

4.6.3. Characteristics

at TA = 0 to 70 °C, fCLOCK = 18.432 MHz, VSUP1 = 7.6 to 8.7 V, VSUP2 = 4.75 to 5.25 V for min./max. valuesat TA = 60 °C, fCLOCK = 18.432 MHz, VSUP1 = 8 V, VSUP2 = 5 V for typical values,TJ = Junction TemperatureMain (M) = Main Channel, Aux (A) = Aux Channel

4.6.3.1. General Characteristics

Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions

Supply

ISUP1A First Supply Current (active)(AHVSUP = 8 V)

AHVSUP 18

12

25

17

mA

mA

Volume Main and Aux 0 dBVolume Main and Aux -30 dB

First Supply Current (active)(AHVSUP = 5 V)

12

8

17

11

mA

mA

Volume Main and Aux 0 dBVolume Main and Aux -30 dB

ISUP2A Second Supply Current (active)(DVSUP = 5 V)

DVSUP 70 85 mA

ISUP3A Third Supply Current (active) AVSUP 9 13 mA

ISUP1S First Supply Current(AHVSUP = 8 V)

AHVSUP 5.6 7.7 mA Standby ModeSTANDBYQ = low

First Supply Current(AHVSUP = 5 V)

3.7 5.1 mA

Clock

fCLOCK Clock Input Frequency XTAL_IN 18.432 MHz

DCLOCK Clock High to Low Ratio 45 55 %

tJITTER Clock Jitter (Verification not provided in Production Test)

50 ps

VxtalDC DC-Voltage Oscillator 2.5 V

tStartup Oscillator Startup Time at VDD Slew-rate of 1 V/µs

XTAL_IN,XTAL_OUT

0.4 2 ms

VACLKAC Audio Clock Output AC Voltage AUD_CL_OUT 1.2 1.8 Vpp load = 40 pF

VACLKDC Audio Clock Output DC Voltage 0.4 0.6 VSUP3 Imax = 0.2 mA

routHF_ACL HF Output Resistance 140 Ω


Micronas 51

4.6.3.2. Digital Inputs, Digital Outputs


Digital Input Levels

VDIGIL Digital Input Low Voltage STANDBYQD_CTR_I/O_0/1

0.2 VSUP2

VDIGIH Digital Input High Voltage 0.5 VSUP2

ZDIGI Input Impedance 5 pF

IDLEAK Digital Input Leakage Current −1 1 µA 0 V < UINPUT< DVSUPD_CTR_I/O_0/1: tri-state

VDIGIL ADR_SEL Input Low Voltage ADR_SEL 0.2 VSUP2

VDIGIH ADR_SEL Input High Voltage 0.8 VSUP2

IADRSEL Input Current −500 −220 µA UADR_SEL= DVSS

220 500 µA UADR_SEL= DVSUP

Digital Output Levels

VDCTROL Digital Output Low Voltage D_CTR_I/O_0D_CTR_I/O_1

0.4 V IDDCTR = 1 mA

VDCTROH Digital Output High Voltage VSUP2 − 0.3

V IDDCTR = −1 mA


52 Micronas

4.6.3.3. Reset Input and Power-Up

Fig. 4–19: Power-up sequence


RESETQ Input Levels

VRHL Reset High-Low Transition Voltage RESETQ 0.3 0.4 VSUP2

VRLH Reset Low-High Transition Voltage 0.45 0.55 VSUP2

ZRES Input Impedance 5 pF

IRES Input Pin Leakage Current -1 1 µA 0 V < UINPUT< DVSUP

VSUP2 − 10%

InternalReset

t/ms

RESETQ

AVSUPDVSUP

High

Low

t/ms

t/ms

Low-to-HighThreshold

High-to-LowThreshold

Reset Delay>2 ms

Note: The reset shouldnot reach high levelbefore the oscillator has started. This requires a reset delay of >2 ms

0.3 x VSUP2 means 1.5 Volt with VSUP2 = 5.0 V

0.45×VSUP2

0.3...0.4×VSUP2


Micronas 53

4.6.3.4. I2C-Bus Characteristics

Fig. 4–20: I2C bus timing diagram


VI2CIL I2C-BUS Input Low Voltage I2C_CL,I2C_DA

0.3 VSUP2

VI2CIH I2C-BUS Input High Voltage 0.6 VSUP2

tI2C1 I2C START Condition Setup Time 120 ns

tI2C2 I2C STOP Condition Setup Time 120 ns

tI2C5 I2C-Data Setup Time before Rising Edge of Clock

55 ns

tI2C6 I2C-Data Hold Time after Falling Edge of Clock

55 ns

tI2C3 I2C-Clock Low Pulse Time I2C_CL 500 ns

tI2C4 I2C-Clock High Pulse Time 500 ns

fI2C I2C-BUS Frequency 1.0 MHz

VI2COL I2C-Data Output Low Voltage I2C_CL,I2C_DA

0.4 V II2COL = 3 mA

II2COH I2C-Data Output High Leakage Current

1.0 µA VI2COH = 5 V

tI2COL1 I2C-Data Output Hold Time after Falling Edge of Clock

15 ns

tI2COL2 I2C-Data Output Setup Time before Rising Edge of Clock

100 ns fI2C = 1 MHz

I2C_CL

I2C_DA as input

I2C_DA as output

TI2C1 TI2C5 TI2C6 TI2C2

TI2C4 TI2C3

1/FI2C

TI2COL2 TI2COL1


54 Micronas

4.6.3.5. I2S-Bus Characteristics


VI2SIL Input Low Voltage I2S_CLI2S_WSI2S_CL3I2S_WS3I2S_DA_IN1..3

0.2 VSUP2

VI2SIH Input High Voltage 0.5 VSUP2

ZI2SI Input Impedance 5 pF

ILEAKI2S Input Leakage Current −1 1 µA 0 V < UINPUT< DVSUP

VI2SOL I2S Output Low Voltage I2S_CLI2S_WSI2S_DA_OUT

0.4 V II2SOL = 1 mA

VI2SOH I2S Output High Voltage VSUP2 − 0.3

V II2SOH = −1 mA

fI2SOWS I2S-Word Strobe Output Frequency I2S_WS 48.0 kHz

fI2SOCL I2S-Clock Output Frequency I2S_CL 1.536 3.072 12.288 MHz

RI2S10/I2S20 I2S-Clock Output High/Low-Ratio 0.9 1.0 1.1

Synchronous I2S Interface

ts_I2S I2S Input Setup Timebefore Rising Edge of Clock

I2S_DA_IN1/2I2S_CL

12 ns for details see Fig. 4–21 “I2S timing diagram (syn-chronous interface)”

th_I2S I2S Input Hold Timeafter Rising Edge of Clock

40 ns

td_I2S I2S Output Delay Time after Falling Edge of Clock

I2S_CLI2S_WSI2S_DA_OUT

28 ns CL=30 pF

fI2SWS I2S-Word Strobe Input Frequency I2S_WS 48.0 kHz

fI2SCL I2S-Clock Input Frequency I2S_CL 1.536 3.072 12.288 MHz

RI2SCL I2S-Clock Input Ratio 0.9 1.1

Asynchronous I2S Interface

ts_I2S3 I2S3 Input Setup Timebefore Rising Edge of Clock

I2S_CL3I2S_WS3I2S_DA_IN3

4 ns for details see Fig. 4–22 “I2S timing diagram (asyn-chronous interface)”

th_I2S3 I2S3 Input Hold Timeafter Rising Edge of Clock

40 ns

fI2S3WS I2S3-Word Strobe Input Frequency I2S_WS3 5 50 kHz

fI2S3CL I2S3-Clock Input Frequency I2S_CL3 3.2 MHz

RI2S3CL I2S3-Clock Input Ratio 0.9 1.1


Micronas 55

Fig. 4–21: I2S timing diagram (synchronous interface)

Data: MSB first, I2S synchronous master

R LSB L LSB

R LSB L LSB

16/32 bit right channel

L LSB

L LSB

R MSB

R MSB

Detail C

I2S_WS

I2S_CL

I2S_DA_IN*)

Detail A

MODUS[6] = 1MODUS[6] = 0

Detail B

R LSB

R LSB L MSB

L MSBI2S_DA_OUT

16/32 bit right channel16/32 bit left channel

16/32 bit left channel

1/FI2SWS

I2S_CL

Detail C

I2S_WS as INPUT

I2S_WS as OUTPUT

1/FI2SCL

Ts_I2S

Td_I2S

Detail A,B

I2S_CL

I2S_DA_OUT

Td_I2S

Data: MSB first, I2S synchronous slave

R LSB L LSB

R LSB L LSB

16, 18...32 bit right channel

L LSB

L LSB

R MSB

R MSB

Detail C

I2S_WS

I2S_CL

I2S_DA_IN*)

Detail A

MODUS[6] = 1MODUS[6] = 0

Detail B

R LSB

R LSB L MSB

L MSBI2S_DA_OUT

16, 18...32 bit right channel

16, 18...32 bit left channel

16,18...32 bit left channel

1/FI2SWS

Th_I2STs_I2S

I2S_DA_IN1)

Note: 1) I2S_DA_IN can be− I2S_DA_IN1, − I2S_DA_IN2, or− I2S_DA_IN2/3


56 Micronas

Fig. 4–22: I2S timing diagram (asynchronous interface)

4.6.3.6. Analog Baseband Inputs and Outputs, AGNDC


Analog Ground

VAGNDC0 AGNDC Open Circuit Voltage

AHVSUP = 8 V

AHVSUP = 5 V

AGNDC

3.8

2.5

V

V

Rload ≥10 MΩ

RoutAGN AGNDC Output Resistance

AHVSUP = 8 V

AHVSUP = 5 V

70

47

125

83

180

120

kΩ

kΩ

3 V ≤ VAGNDC ≤ 4 V

Analog Input Resistance

RinSC SCART Input Resistancefrom TA = 0 to 70 °C

SCn_IN_s1) 25 40 58 kΩ fsignal = 1 kHz, I = 0.05 mA

RinMONO MONO Input Resistancefrom TA = 0 to 70 °C

MONO_IN 15 24 35 kΩ fsignal = 1 kHz, I = 0.1 mA

1) “n” means “1”, “2”, “3”, or “4”; “s” means “L” or “R”

Right aligned (I2S_CONFIG[11] = 1, I2S_CONFIG[9] = 0)16 Bit data & 16...32 clocks allowed

I2S_WS3

I2S_CL3

I2S_DA_IN3

MSB

1/FI2S3WS

1/FI2S3CL

I2S_CL3

I2S_DA_IN3

I2S_WS3

Th_I2S3

Right sample (I2S_CONFIG[10] = 0)

Right sample (I2S_CONFIG[10] = 1)

Left sample (I2S_CONFIG[10] = 0)

Left sample (I2S_CONFIG[10] = 1)

MSB

LSB

MSB

MSB

LSB

I2S_DA_IN3

I2S_DA_IN3

Left aligned (I2S_CONFIG[9] = 0)

Left aligned (I2S_CONFIG[9] = 1)

16,18...32 Bit data & clocks allowed

16,18...32 Bit data & clocks allowed

Ts_I2S3

Ts_I2S3


Micronas 57

Audio Analog-to-Digital-Converter

VAICL Analog Input Clipping Level for Analog-to-Digital-Conversion(AHVSUP=8 V)

SCn_IN_s,1)

MONO_IN2.00 2.25 VRMS fsignal = 1 kHz

Analog Input Clipping Level for Analog-to-Digital-Conversion(AHVSUP=5 V)

1.13 1.51 VRMS

SCART Outputs

RoutSC SCART Output Resistance SCn_OUT_s1) 200200

330 460500

ΩΩ

fsignal = 1 kHz, I = 0.1 mA,Tj = 27°C, TA = 0 to 70°C

dVOUTSC Deviation of DC-Level at SCART Output from AGNDC Voltage

−70 +70 mV

ASCtoSC Gain from Analog Input to SCART Output

SCn_IN_s,1)

MONO_IN →SCn_OUT_s1)

−1.0 +0.5 dB fsignal = 1 kHz

frSCtoSC Frequency Response from Analog Input to SCART Output

−0.5 +0.5 dB with resp. to 1 kHz 20 Hz to 20 000 Hz

VoutSC Signal Level at SCART-Output (AHVSUP=8 V)

SCn_OUT_s1) 1.8 1.9 2.0 VRMS fsignal = 1 kHzfull scale Digital Input from I2S

Signal Level at SCART-Output(AHVSUP=5 V)

1.17 1.27 1.37 VRMS

Main and Aux Outputs

RoutMA Main/Aux Output Resistance DACp_s1) 2.12.1

3.3 4.65.0

kΩkΩ

fsignal = 1 kHz, I = 0.1 mATj = 27°C from TA = 0 to 70°C

VoutDCMA DC-Level at Main/Aux-Output(AHVSUP=8 V)

1.80 2.0461

2.28 VmV

Volume = 0 dBVolume = -30 dB

DC-Level at Main/Aux-Output(AHVSUP=5 V)

1.12 1.3640

1.60 VmV

Volume = 0 dBVolume = -30 dB

VoutMA Signal Level at Main/Aux-Output(AHVSUP=8 V)

1.23 1.37 1.51 VRMS fsignal = 1 kHzfull scale Digital Input from I2SVolume = 0 dBSignal Level at Main/Aux-Output

(AHVSUP=5 V)0.76 0.90 1.04 VRMS

1) “n” means “1”, “2”, “3”, or “4”; “s” means “L” or “R”; “p” means “M” or “A”



58 Micronas

4.6.3.7. Power Supply Rejection

4.6.3.8. Analog Performance


PSRR: Rejection of Noise on AHVSUP at 1 kHz

PSRR AGNDC AGNDC 80 dB

From Analog Input to I2S Output MONO_IN,SCn_IN_s1)

70 dB

From Analog Input to SCART Output

MONO_IN,SCn_IN_s1)

SCn_OUT_s1)

70 dB

From I2S Input to SCART Output SCn_OUT_s1) 60 dB

From I2S Input to Main/Aux Output DACp_s1) 80 dB



Specifications for AHSUP=8 V

SNR Signal-to-Noise Ratio

from Analog Input to I2S Output MONO_IN,SCn_IN_s1)

90 93 dB Input Level = −20 dB with resp. to VAICL, fsig = 1 kHz, A-weighted 20 Hz...20 kHz

from Analog Input to SCART Output

MONO_IN,SCn_IN_s1)

→SCn_OUT_s1)

93 96 dB Input Level = −20 dB, fsig = 1 kHz, A-weighted 20 Hz...20 kHzVolume = 0 dB

from I2S Input to SCART Output SCn_OUT_s1) 90 93 dB

from I2S Input to Main/Aux-Output DACp_s1) 90 93 dB

THD Total Harmonic Distortion


0.01 0.03 % Input Level = −3 dBr with resp. to VAICL, fsig = 1 kHz, unweighted20 Hz...20 kHz


MONO_IN,SCn_IN_s →SCn_OUT_s1)

0.01 0.03 % Input Level = −3 dBr,fsig = 1 kHz, unweighted 20 Hz...20 kHz

from I2S Input to SCART Output SCn_OUT_s1) 0.01 0.03 %

from I2S Input to Main or Aux Out-put

DACA_s,DACM_s1)

0.01 0.03 %



Micronas 59

Specifications for AHSUP=5 V

SNR Signal-to-Noise Ratio


87 90 dB Input Level = −20 dB with resp. to VAICL, fsig = 1 kHz, A-weighted 20 Hz...20 kHz


MONO_IN,SCn_IN_s1)

→SCn_OUT_s1)

90 93 dB Input Level = −20 dB, fsig = 1 kHz, A-weighted 20 Hz...20 kHzVolume = 0 dB

from I2S Input to SCART Output SCn_OUT_s1) 87 90 dB

from I2S Input to Main/Aux-Outputfor Analog Volume at 0 dBfor Analog Volume at −30 dB

DACp_s1)

8775

9080

dBdB

THD Total Harmonic Distortion


0.03 0.1 % Input Level = −3 dBr with resp. to VAICL, fsig = 1 kHz, unweighted20 Hz...20 kHz


MONO_IN,SCn_IN_s →SCn_OUT_s1)

0.1 % Input Level = −3 dBr,fsig = 1 kHz, unweighted 20 Hz...20 kHz

from I2S Input to SCART Output SCn_OUT_s1) 0.1 %

from I2S Input to Main or Aux Out-put

DACA_s,DACM_s1)

0.1 %




60 Micronas

Crosstalk Specifications

XTALK Crosstalk Attenuation Input Level = −3 dB, fsig = 1 kHz, unused analog inputs connected to ground by Z < 1 kΩ

between left and right channel within SCART Input/Output pair (L→R, R→L)

SCn_IN → SCn_OUT1)

SC1_IN or SC2_IN → I2S Output

SC3_IN → I2S Output

I2S Input → SCn_OUT1)

80

80

80

80

dB

dB

dB

dB

unweighted 20 Hz...20 kHz

between left and right channel withinMain or Aux Output pair

I2S Input → DACp1) 75 dB

unweighted 20 Hz...20 kHz

between SCART Input/Output pairs1)

D = disturbing programO = observed program

D: MONO/SCn_IN → SCn_OUT O: MONO/SCn_IN → SCn_OUT1)

D: MONO/SCn_IN → SCn_OUT or unsel.O: MONO/SCn_IN → I2S Output

D: MONO/SCn_IN → SCn_OUTO: I2S Input → SCn_OUT1)

D: MONO/SCn_IN → unselectedO: I2S Input → SC1_OUT1)

100

95

100

100

dB

dB

dB

dB

(unweighted 20 Hz...20 kHz)same signal source on left and right disturbing chan-nel, effect on each observed output channel

Crosstalk between Main and Aux Output pairs

I2S Input DSP → DACp1) 90 dB


XTALK Crosstalk from Main or Aux Output to SCART Output and vice versa

D = disturbing programO = observed program

D: MONO/SCn_IN/DSP → SCn_OUTO: I2S Input → DACp1)

D: MONO/SCn_IN/DSP → SCn_OUT O: I2S Input → DACp1)

D: I2S Input → DACpO: MONO/SCn_IN → SCn_OUT1)

D: I2S Input → DACMO: I2S Input → SCn_OUT1)

80

85

95

95

dB

dB

dB

dB


SCART output load resis-tance 10 kΩ

SCART output load resis-tance 30 kΩ




Micronas 61

5. Appendix A: Application Information

5.1. Phase Relationship of Analog Outputs

The analog output signals: Main, Aux, and SCART2 allhave the same phases. The SCART1 output has oppo-site phase.

Using the I2S-outputs for other DSPs or D/A convert-ers, care must be taken to adjust for the correct phase.

Fig. 5–1: Phase diagram of the DPL 4519G

SCART1

SCART1

SCART2

SCART4

SCART3

MONO

Main

Audio

SCARTOutput Select

BasebandProcessing

Aux

SCART1-Ch.

SCART2

I2S_OUT1/2I2S_IN1/2/3

MONO, SCART1...4


62 Micronas

5.2. Application Circuit

SC1_OUT_L (37) 37

SC1_OUT_R (36) 36

SC2_OUT_L (34) 34

SC2_OUT_R (33) 33

39 (

39)

AH

VS

UP

43 (

41)

AH

VS

S

66 (

57)

AV

SU

P

13 (

18)

DV

SU

P

16 (

19)

DV

SS

21 (

24)

RE

SE

TQ

62 (

56)

AV

SS

35 (

35)

VR

EF

1

26 (

27)

VR

EF

2

5 V 5 V 8 V

AV

SS

5 V

5 V

CA

PL_

M (

40)

40

CA

PL_

A (

38)

38

AG

ND

C (

42)

45

XT

AL_

IN (

62)

71

XT

AL_

OU

T (

63)

72

DPL 4519G

D_CTR_I/O_0 (5) 78

D_CTR_I/O_1 (4) 77

AUD_CL_OUT (1) 74

TESTEN (61) 70

+

100 Ω

100 Ω

100 Ω

100 Ω

22 µF

22 µF

22 µF

22 µF

+

+

+

1 nF

1 nF

1 nF

DACM_SUB (31) 30

DACM_R (28) 27

DACM_L (29) 28

1 µF

1 µF

1 µF

right

+

3.3 µF

100 nF

8 V(5 V)

18.432MHz

++

10 µF 10 µF

60 (55) MONO_IN

56 (52) SC1_IN_L

57 (53) SC1_IN_R

55 (51) ASG

53 (49) SC2_IN_L

54 (50) SC2_IN_R

52 (48) ASG

50 (46) SC3_IN_L

51 (47) SC3_IN_R

49 (45) ASG

47 (43) SC4_IN_L

48 (44) SC4_IN_R

80 (7) STANDBYQ

79 (6) ADR_SEL

3 (10) I2C_DA

2 (9) I2C_CL

5 (12) I2S_WS

4 (11) I2S_CL

7 (14) I2S_DA_IN1

17 (20) I2S_DA_IN2

6 (13) I2S_DA_OUT

220 pF

AHVSS

AHVSS

AHVSS

330 nF

330 nF

330 nF

330 nF

330 nF

330 nF

330 nF

330 nF

330 nF

DVSS

DVSS

AHVSS

C s. section 4.6.2.

RESETQ

(from Controller, see section 4.6.3.3.)

Note: Decoupling capacitors from − DVSUP to DVSS, − AVSUP to AVSS, and − AHVSUP to AHVSS are recommended as closelyas possible to supply pins (seeapplication note on page 42).

1.5 nF

470 pF

10 µF

1.5 nF

470 pF

10 µF

1.5 nF

470 pF

10 µF

(5 V) AH

VS

S

AH

VS

S

AH

VS

S

DACA_R (25) 24

1 nF

1 nF

DACA_L (26) 25

1 µF

1 µF

Note: Pin numbers refer to the PQFP80 package, numbers in brackets refer to the PSDIP64 package.

Subwoofer

left

Center

Surround


Micronas 63

All information and data contained in this data sheet are without anycommitment, are not to be considered as an offer for conclusion of acontract, nor shall they be construed as to create any liability. Any newissue of this data sheet invalidates previous issues. Product availabilityand delivery are exclusively subject to our respective order confirmationform; the same applies to orders based on development samples deliv-ered. By this publication, Micronas GmbH does not assume responsibil-ity for patent infringements or other rights of third parties which mayresult from its use.Further, Micronas GmbH reserves the right to revise this publication andto make changes to its content, at any time, without obligation to notifyany person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on aretrieval system, or transmitted without the express written consent ofMicronas GmbH.


64 Micronas

Micronas GmbHHans-Bunte-Strasse 19D-79108 Freiburg (Germany)P.O. Box 840D-79008 Freiburg (Germany)Tel. +49-761-517-0Fax +49-761-517-2174E-mail: [email protected]: www.micronas.com

Printed in GermanyOrder No. 6251-512-1PD

6. Data Sheet History

1. Preliminary data sheet: "DPL 4519G Sound Proces-sor for Digital and Analog Surround Systems", Oct. 31, 2000, 6251-512-1PD. First release of the preliminary data sheet.

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