MICROELECTRONICS PACKAGING HANDBOOK - Springer978-1-4615-4086-1/1.pdf · MICROELECTRONICS PACKAGING...

MICROELECTRONICS

PACKAGING

HANDBOOK

MICROELECTRONICS

PACKAGING

HANDBOOK

Technology Drivers

PART 1

Second Edition

Edited by Rao R. Tummala

Georgia Institute of Technology

Eugene J. Rymaszewski Rensselaer Polytechnic Institute

Alan G. Klopfenstein A GK Enterprises

SPRINGER-SCIENCE+BUSINESS MEDIA, B.V.

Library of Congress Cataloging-in-Publication

Microelectronics packaging handbook / edited by Rao R. Tummala, Eugene J. Rymaszewski, Alan G. Klopfenstein.

p. cm. Includes bibliographical references and index.

Contents: pt. 1. Technology drivers--pt. 2. Semiconductor packaging--pt. 3. Subsystem packaging.

ISBN 978-1-4613-6829-8 ISBN 978-1-4615-4086-1 (eBook) DOI 10.1007/978-1-4615-4086-1

1. Microelectronic packaging--Handbook, manuals, etc. II. Rymaszewski, Eugene J. III. Klopfenstein, Alan G.

I. Tummala, Rao R., 1942--.

TK7874.M485 1996 621.381 '046--dc21

British Library Cataloguing in Publication Data available

Copyright @ 1997 by Springer Science+Business Media Dordrecht OriginalIy published by Chapman & HalI in 1997 Softcover reprint ofthe hardcover 2nd edition 1997 Third Printing 2001 by Kluwer Academic Publishers

This printing is a digital duplication of the original edition.

%-37CXJ7 CIP

AII rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, mechanical, photo-copying, recording, Of otherwise, without the prior written permission of the publisher, Springer-Science+Business Media, B.V.

Printed an acid-free paper.

FOREWORD

Electronics has become the largest industry, surpassing agriCUlture, auto. and heavy metal industries. It has become the industry of choice for a country to prosper, already having given rise to the phenomenal prosperity of Japan. Korea. Singapore. Hong Kong. and Ireland among others. At the current growth rate, total worldwide semiconductor sales will reach $300B by the year 2000.

The key electronic technologies responsible for the growth of the industry include semiconductors. the packaging of semiconductors for systems use in auto, telecom, computer, consumer, aerospace, and medical industries. displays. magnetic, and optical storage as well as software and system technologies. There has been a paradigm shift, however, in these technologies. from mainframe and supercomputer applications at any cost. to consumer applications at approximately one-tenth the cost and size. Personal computers are a good example. going from $500IMIP when products were first introduced in 1981, to a projected $lIMIP within 10 years. Thin. light portable. user friendly and very low-cost are. therefore. the attributes of tomorrow's computing and communications systems.

Electronic packaging is defined as interconnection. powering, cooling, and protecting semiconductor chips for reliable systems. It is a key enabling technology achieving the requirements for reducing the size and cost at the system and product level.

The recent paradigm shifts in packaging processes such as direct flip-chip attach to organic board. the ability to increase wiring in the organic board away from expensive drilled technology by the direct deposition of thin organic and metal films. the achievement of reliability without hermeticity previously achieved only in ceramic packaging, and the potential integration of all passive components within the interconnect board are expected to lead to revolutionary products in all segments of electronics.

To describe the status and future developments in these technologies, editors Profs. Tummala and Rymaszewski and Mr. Klopfenstein have assembled an outstanding team of 74 packaging practitioners from across the globe. Together, they produced in three parts the Microelectronics

I-vi FOREWORD

Packaging Handbook, an unmatched book needed by industry and universities. It is equally appropriate both as an introduction to those just entering the field, and as an up-to-date reference for those already engaged in packaging design, first and second level packages and their interconnections, test, assembly, thermal management, optoelectronics, reliability, and manufacturing.

I applaud the authors and editors for their great contributions and hope that this book will help focus the attention of outstanding faculty, students, and industry researchers on the complex packaging challenges that they face in the 21 st century.

Bertrand Cambou Motorola Senior Vice-President

Sector Technology Semiconductor Productor Sector

PREFACE

"This book reflects a need based on an ever-increasing realization by the microelectronics community that while the semiconductors continue to be improved upon relentlessly for performance, cost, and reliability, it is the packaging of these microelectronic devices that may limit the systems performance. In response to this need, the academic community began to ask its industrial counterparts what packaging is all about, and what scientific and technological areas should be pursued in collaboration with industry. As a result of these discussions, a number of universities in the United States and throughout the world already have research and! or teaching programs in various aspects of packaging, ranging from materials, assembly, electrical, and thermal modeling, thin films, and many others. The multidisciplinary nature of packaging technology clearly poses challenges not only to this community, but also to industrial colleagues who will have to use scientific fundamentals from a cross section of disciplines to bring about advanced products." That's the way we began the preface of the 1st edition of the Microelectronics Packaging Handbook in 1989. The first sentence is true today; however, two additional factors have become more important: cost and size. This is readily apparent when one considers consumer electronics. The use of packaged microelectronics has increased tremendously in a great variety of applications-television, computers, communications, navigation, automotive, avionics, medical, and so forth. Perhaps the biggest change is the degree to which universities have embraced the field of microelectronics and established major research and teaching programs. Also, the growth in coverage of microelectronics packaging by technical societies-both in technical symposia and in tutorial sessions-has been dramatic.

While the book is not intended to be a classic textbook for any course in packaging, it does attempt to define what microelectronics packaging is all about, including the current state of the technology across all engineering and scientific disciplines, and the fundamental areas that could impact the industrial needs. It also provides a comprehensive source of information on all aspects of microelectronics packaging.

I-viii PREFACE

Packaging of electronic circuits is the science and art of establishing interconnections and a suitable operating environment for primarily electronic circuits to process and store information. Accordingly, microelectronics packaging in this book is assumed to mean those designs and interconnection technologies necessary to support electrically, optically, thermally, mechanically, and chemically those semiconductor devices with micron and submicron dimensions that are often referred to as integrated circuits. Electronic components and their packaging are the building blocks for a vast variety of equipment. Customer demand and competition among equipment suppliers result in continuing enhancements and evolution of these building blocks, particularly in terms of cost, performance, quality, and reliability.

Since publishing the first edition of this book, a number of paradigm shifts have taken place in the electronics industry. For one, the emphasis on systems has changed from mainframe computers to personal computers and portable, wireless systems requiring ultra low-cost, thin, light, and portable packages. Second, the semiconductor technologies have shifted emphasis from bipolar to CMOS. A number of paradigm shifts have taken place in packaging as well. Direct chip attach was possible in 1989 only to such inorganic substrates as alumina and silicon. Today, chips can be bonded and used directly on printed wiring boards. The board itself is undergoing major change, allowing very high density wiring by photolithograpic processes in contrast to mechanical drilling, which became expensive and obsolete. The very high reliability that was achieved previously only with ceramic packages is now beginning to be achieved with organic packages and boards without hermeticity. This book is written with these changes in mind and consistent with the needs of the industry.

This collection of books is organized into three parts. Part 1 includes chapters 1 through 6 and covers the driving forces of microelectronics packaging-electrical, thermal, and reliability. In addition, Part 1 introduces the technology developer to aspects of manufacturing that must be considered during product development. Part 2, chapters 7 through 14, covers the interconnection of the IC chip to the first level of packaging and all first level packages. Part 2 also includes electrical test as well as sealing and encapsulation technologies. Part 3, chapters 15 through 20, covers board level packaging as well as connectors, cables, and optical packaging. The general overview of packaging is repeated in each part as chapters 1, 7, and 15.

The main problem of creating a handbook in any field is obvious: by the time the book is completed, much of the information in it may require updating. This is particularly true with microelectronics packaging, which is one of the fastest, if not the fastest, growing of all technologies. The first edition was a beginning and this 2nd edition is long overdue. Further development and refinement, based on the comments and sugges-

PREFACE J-ix

tions of the users, can appear in future editions. The book in its present state reflects what we believe the community wants currently. We are exploring new ways of providing the information on a more current basis including electronic publishing and interchange.

The first edition was written entirely by IBMers. We tried to include as many non-IBM technologists as possible and to minimize the use of IBM jargon. This 2nd edition includes 74 authors, each an expert in his or her own field, from many companies, universities, and countries. We believe that this second edition provides a very representative and comprehensive look at the field of microelectronics packaging.

Any handbook requires the dedication of a number of individuals involved in writing, typing, graphics preparation, manuscript reviewing, copyediting, and publishing, and managing all these operations in such a way that the final book is available in a timely manner. Above all, a free and stimulating attitude on the part of all the participants is necessary. In addition to the chapter authors, we would like to acknowledge the work of Debra Kelley in helping to keep us on track and for her efforts in preparing some of the manuscripts. It should be pointed out that extensive use of the Internet permitted us to work together more easily and cost effectively. Our thanks to Jim Geronimo and Barbara Tompkins for the preparation of numerous drafts, extensive copy editing, and their willingness to be sure that all appropriate authors had timely copies to review. Also to Kristi Bockting and the staff at WoridComp for the monumental job of incorporating all author comments into the final "camera-ready" manuscript. Our greatest thanks go to our wives, Anne Tummala and Jean Rymaszewski, and Mary Ann Klopfenstein for their patience and full support. We thank Bertrand Cambou, Motorola Senior VicePresident for the insightful Foreword.

Rao R. Tummala Eugene J. Rymaszewski

Alan G. Klopfenstein

Part 1

TABLE OF CONTENTS*

FOREWORD I-v

PREFACE I-vii

CONVERSION FACTORS I-xix

SUMMARY CONTENTS I-xxiii

PART 1. MICROELECTRONICS PACKAGING HANDBOOK: TECHNOLOGY DRIVERS I-I

CHAPTER 1. MICROELECTRONICS PACKAGING-AN OVERVIEW 1-3 1.1 INTRODUCTION 1-3

1.1.1 Packaged Electronics 1-8 I. 1.2 Packaging Functions and Hierarchy 1- Il 1.1.3 Evolving Trends 1-14

1.1.3.1 Product Applications 1-14 1.1.3.2 Semiconductors 1-16 1.1.3.3 Future Packaged-Electronics Considerations 1-17

1.2 TECHNOLOGY DRIVERS 1-21 1.2.1 Wireability, Number of Terminals, and Rent's Rule 1-22 1.2.2 Electrical Design Considerations 1-24

1.2.2.1 General 1-25 1.2.2.2 Electromagnetic Properties of Signal Wire 1-26 1.2.2.3 Signal Degradation 1-27 1.2.2.4 Cross-Coupling Noise 1-27 1.2.2.5 Switching (tlJ) Noise I-28 1.2.2.6 Signal Reflections 1-29

1.2.3 Electrical Performance-Power Distribution I-29 1.2.3.1 Rigorous Analysis 1-30 1.2.3.2 Very Rough Estimate of Acceptable Lead Inductance

L = 4,,, 1-31 1.2.4 Thermal Design Considerations 1-33 1.2.5 Reliability 1-35 1.2.6 Manufacturability and Quality 1-37

*See Summary of Contents for 3 part set, p. xxiii.

I-xii TABLE OF CONTENTS

1.2.7 Testability 1-38 1.2.8 Memory Packaging 1-40 1.2.9 Personal Computers and Workstations 1-42

1.2. IO Portable and Mixed-Signal Equipment 1-44 1.2. I 1 High-Performance Processors 1-45 1.2.12 Optical Interconnects 1-48 1.2.13 Summary of Packaging Performance Considerations and

Evolution 1-48 1.2.13.1 Power-Time Product Theory 1-48 1.2.13.2 Reduction of VBReB by LSI Technology I-50 1.2.13.2 System LSI in Chips and Packages I-53 1.2.13.3 Media Delay Factor I-58

1.3 PACKAGING TECHNOLOGIES 1-62 1.3.1 Packaging Evolution 1-63

1.3. I.I Packaging in the Past 1-67 1.3.1.2 Packaging in the Future 1-71

1.4 CHIP-LEVEL INTERCONNECTIONS 1-7 I 1.4.1 Wirebond 1-72 1.4.2 TAB 1-74 1.4.3 Flip Chip 1-76

1.5 FIRST-LEVEL PACKAGES 1-78 1.5.1 Single-Chip Packages 1-78 1.5.2 Chip-Scale or Chip-Size Packages 1-82 1.5.3 Single-Chip Package Markets 1-86 1.5.4 Plastic Packages 1-88

1.5.4.1 Process Controls 1-89 1.5.5 Plastic PGA Technology 1-90 1.5.6 Lead-Frame Fabrication 1-90 1.5.7 Logic and Memory Applications 1-91 1.5.8 Ceramic Packaging Technologies 1-91 1.5.9 BGA Packages 1-93

1.5. IO Package Trade-offs 1-96 1.5.11 First-Level Multichip Packaging 1-99

1.5.1 I.I Definition 1-100 1.5.11.2 Functions of Multichip Package 1-100 1.5.11.3 Packaging Efficiency 1-101 1.5.11.4 Electrical Performance 1-102 1.5.11.5 Reliability 1-103 1.5.11.6 Leverages 1-104 1.5.11.7 Types of Multichips 1-104 1.5.11.8 Cost 1-104 1.5. 11.9 Applications 1-106

1.6 PACKAGE-TO-BOARD INTERCONNECTIONS 1-106 1.7 SECOND-LEVEL PACKAGES 1-114 1.8 PACKAGING COOLING 1-119 1.9 PACKAGE SEALING AND ENCAPSULATION 1-123

1.10 BOOK ORGANIZATION AND SCOPE 1-125 1.11 REFERENCES 1-127

TABLE OF CONTENTS I-xiii

CHAPTER 2. PACKAGE WIRING AND TERMINALS 1-129 2.1 I:--.lTRODUCTION 1-129

2.1.1 The Packaging Hierarchy 1-131 2.1.2 Wiring Constraints and Dimensions 1-132 2.1.3 Influence of Physical-Design Tools on Package Wiring 1-136 2.1.4 The Need for a Model of Wiring 1-137 2.1.5 Goals for Quantitative Prediction 1-138 2.1.6 Standardization of Wiring Terminology 1-138

2.2 THE WIRING MODEL AND ITS VARIABLES 1-139 2.2.1 Basic Wireability Analysis 1-139 2.2.2 Rent's Rule and the Average Wire Length 1-142 2.2.3 Terminal Counts and Rent's Rule 1-146 2.2.4 The Wiring Distribution 1-148 2.2.5 Topological Constraints on Interconnections 1-149 2.2.6 Probabilistic Model for Wiring Congestion and Completion 1-152

2.3 RESULTS OF CHIP CIRCUIT PLACEMENT AND WIRING VERSUS MODEL PREDICTIONS 1-155

2.3.1 Direct Comparisons with Experiment 1-155 2.3.2 Influence of Logic Changes During Design 1-159 2.3.3 Influence of Gate Depopulation in Gate-Array Chips 1-159 2.3.4 Influence of the Use of Macros on Chips 1-161 2.3.5 Influence of Multilevel Wiring on Chip Wireability 1-162 2.3.6 Effects of Custom Design 1-164

2.4 WIREABILITY OF HIGHER-LEVEL PACKAGES 1-165 2.4.1 Package Wireability Studies 1-167 2.4.2 Package Wireability Constraints 1-172 2.4.3 Influence of Via Availability and Wiring-Track Accessibility on

Package Wireability 1-177 2.4.4 A Quantitative Model for Overflow Prediction 1-185 2.4.5 Applications of Wireability Analysis to

Higher-level Packaging 1-187 2.5 CONCLUSIONS AND CHALLENGES FOR FUTURE WORK 1-191

2.5.1 Overall Value of Wireability Analysis 1-191 2.5.2 Preplacement and Prewiring Influences 1-193 2.5.3 Mixed-Signal Wiring 1-193 2.5.4 Challenges for Design Tools 1-194

2.6 REFERENCES 1-195

CHAPTER 3. PACKAGE ELECTRICAL DESIGN 1-199 3.1 TNTRODUCTIOl\" 1-199 3.2 CIRCUIT ATTRIBUTES 1-205

3.2.1 Receivers 1-206 3.2.1.1 Transmitted Noise Tolerance 1-206 3.2.1.2 Self-Generated Noise Tolerance 1-209 3.2.1.3 Composite Noise Tolerance 1-210 3.2.1.4 Receiver Input Stability 1-211

I-xiv TABLE OF CONTENTS

3.2.2 Drivers 1-212 3.2.2.1 Driver Output Levels 1-213 3.2.2.2 Driver Slew Rate 1-214 3.2.2.3 Driver Output Impedance 1-215

3.3 SIGNAL DISTRIBUTION 1-216 3.3.1 Slow Package Design 1-216 3.3.2 Lossy Signal Lines 1-218 3.3.3 Design Methodology for Digital Signal Transmission Nets 1-220

3.3.3.1 Discretely Loaded and Distributed Nets 1-224 3.3.3.2 Example for Generation of a Wiring Rule 1-227 3.3.3.3 Example for Generation of a Delay Equation 1-229 3.3.3.4 Structural Design Considerations 1-230 3.3.3.5 Active Terminator 1-230

3.4 POWER DISTRIBUTION 1-232 3.5 NOISE CONTAINMENT 1-235

3.5.1 The Meaning of Leff 1-237 3.5.1.1 Power-Supply Impedance at High Frequency 1-241

3.5.2 Switching or M Noise 1-245 3.5.2.1 Coupled Noise or Cross-Talk 1-252

3.5.3 The Most Severe Case: Coupled and M Noise Together 1-256 3.6 LOW-LOSS TRANSMISSION SYSTEMS 1-258

3.6.1 Signal Design 1-259 3.6.1.1 Low-Loss Line Behavior 1-261

3.6.2 Noise Design for Thin-Film Structures 1-268 3.6.2.1 Coupled Noise 1-268 3.6.2.2 Switching Noise 1-270

3.7 PACKAGE MODELING 1-270 3.7.1 Fundamental Principles 1-272 3.7.2 Frequency Effects 1-283 3.7.3 Time-Domain Waveform Distortion 1-286 3.7.4 Package-Modeling Techniques 1-288

3.7.4.1 Modeling Tips 1-293 3.8 THE DESIGN SPACE 1-298

3.8.1 Delay-Adder Dependency on Zo (Line Characteristic Impedance) 1-298 3.8.2 Noise Dependency on Zo 1-299 3.8.3 Acceptable Range for Zo 1-300

3.9 SYSTEM IMPACT 1-302 3.10 PACKAGE IMPROVEMENTS 1-306 3.11 SUMMARY 1-308 3.12 ACKNOWLEDGMENTS 1-309 3.13 REFERENCES 1-309 3.14 APPENDIX: CALCULATION OF PEAK AVERAGE CURRENT SLEW

RATE 1-312

CHAPTER 4. HEAT TRANSFER IN ELECTRONIC PACKAGES 1-314 4.1 INTRODUCTION 1-314 4.2 HEAT-TRANSFER FUNDAMENTALS 1-322

4.2.1 Conduction 1-322 4.2.1.1 Thermal Conductivity 1-323

TABLE OF CONTENTS I-xv

4.2.1.2 Thennal Resistance 1-325 4.2.1.3 Extended Surfaces 1-330 4.2.1.4 Numerical Methods 1-332 4.2.1.5 Statistical Approaches 1-337 4.2.1.6 Thermal Contact Resistance 1-339

4.2.2 Convection 1-343 4.2.2.1 Dimensionless Numbers 1-343 4.2.2.2 Natural Convection 1-346 4.2.2.3 Forced Convection 1-349

4.2.3 Boiling 1-360 4.2.4 Radiation 1-369

4.3 EXPERIMENTAL TECHNIQUES AND INSTRUMENTATION 1-370 4.3.1 Chip Temperature Measurement 1-370 4.3.2 Determining Internal Resistance 1-371 4.3.3 Detennining External Resistance 1-373 4.3.4 Vendor Thermal Data 1-375 4.3.5 Pressure Drop and Airflow 1-377

4.4 TYPICAL COOLING DESIGNS 1-378 4.5 RECENT PACKAGING HEAT TRANSFER DEVELOPMENTS 1-392 4.6 SUMMARY 1-396 4.7 NOMENCLATURE 1-397 4.8 REFERENCES 1-399

CHAPTER 5. PACKAGE RELIABILITY 1-404 5.1 INTRODUCTION 1-404 5.2 RELIABILITY METROLOGY 1-407 5.3 CONTACT RESISTANCE 1-423 5.4 ENVIRONMENTAL INTERACTIONS 1-432

5.4.1 Package Environments 1-432 5.4.2 Package Configurations 1-433 5.4.3 Chemical Failure Mechanisms 1-434 5.4.4 Electrochemical Processes 1-436

5.4.4.1 Electrochemical Fundamentals and Modeling 1-436 5.4.5 Principles of Chemical Thennodynamics 1-439 5.4.6 Electrolyte Film Fonnation 1-446 5.4.7 Failure Rate Prediction 1-450 5.4.8 Statistical Distribution of Electrochemical Failures 1-453

5.4.8. I Applications and Examples 1-453 5.4.9 Corrosion Control in Microelectronic Packages 1-453

5.4.10 Polymer-Failure Mechanisms 1-456 5.5 THERMAL MISMATCH AND THERMAL FATIGUE 1-457

5.5.1 Evaluation Techniques 1-460 5.5.l.l Thennal Stress Evaluation-Analytical Tools 1-461

5.5.1.1.1 Classical Stress Analysis 1-461 5.5.1.1.2 Numerical Analysis; Finite Element

Modeling 1-462 5.5.1.1.3 Distributional Analysis 1-465

5.5.1.2 Thennal Stress Evaluation-Experimental Tools 1-466 5.5.1.2.1 Strain Gauges 1-466

I-xvi TABLE OF CONTENTS

5.5.1.2.2 Moire Interferometry 1-467 5.5.1.2.3 Other Experimental Techniques 1-468

5.5.1.3 Thermal, Power, and Mechanical Cycling 1-469 5.5.1.3.1 Thermal Cycling 1-469 5.5.1.3.2 Power Cycling 1-470 5.5.1.3.3 Mechanical Cycling 1-471

5.5.1.4 Theories of Fatigue 1-471 5.5.1.4.1 Coffin-Manson-Type Relationships 1-473 5.5.1.4.2 Miner's Rule 1-476 5.5.1.4.3 Energy Methods 1-477 5.5.1.4.4 Fracture Mechanics 1-478

5.5.1.5 Statistics 1-481 5.5.2 The Major Occurrences of Thermal Mismatch Fatigue 1-483

5.5.2.1 First-Level Packaging: Die Attach 1-483 5.5.2.1.1 Die Cracking 1-484 5.5.2.1.2 Adhesive Fatigue 1-486 5.5.2.1.3 Minimizing the Risk 1-487

5.5.2.2 First-Level Packaging: Flip Chip 1-487 5.5.2.2.1 Characteristics of Thermal Cycle

Failures 1-488 5.5.2.2.2 How Fatigue Has Been Studied 1-490 5.5.2.2.3 Factors Which Influence Fatigue

Performance 1-491 5.5.2.3 Second-Level Packaging: Pin-in-Hole 1-494

5.5.2.3.1 Characteristics of Thermal-Cycle Failures 1-494

5.5.2.3.2 How Fatigue Has Been Studied 1-496 5.5.2.3.3 Factors Which Influence Fatigue

Performance 1-496 5.5.2.3.4 Unfilled Holes 1-497

5.5.2.4 Second Level Packaging: Surface Mount Technology 1-497 5.5.2.4.1 Leadless Chip Carriers 1-498 5.5.2.4.2 Leaded Chip Carriers 1-500 5.5.2.4.3 Ball Grid Arrays 1-504 5.5.2.4.4 Chip-on-Board 1-506

5.5.3 Conclusion 1-508 5.6 MECHANICAL LOADING 1-508 5.7 TRIBOLOGICAL DEGRADATION 5.8 HEAT-TRANSFER DEGRADATION 5.9 SUMMARY

5.10 REFERENCES 1-530

1-533

1-519 1-524

5.11 APPENDIX-PROBABILITY DENSITY TABLE 1-551

CHAPTER 6. PACKAGE MANUFACTURE 1-556 6.1 INTRODUCTION 1-556 6.2 QUALITY IN PRODUCT AND PROCESS DESIGN 1-561

6.2.1 Tools for Quality Design 1-562

TABLE OF CONTENTS I-xvii

6.2.2 Quality Function Deployment 1-563 6.2.2.1 A Case History of QFD in Package Design 1-565

6.2.3 Taguchi Robust DOE 1-567 6.2.3.1 Seven Steps of DOE 1-568 6.2.3.2 Importance of Variation 1-578 6.2.3.3 A Case History of QFD in Package Design-

Continued 1-578 6.2.4 Robust Process Design 1-582 6.2.5 Quality in Product and Process Design-Summary 1-584

6.3 PRODUCT QUALIFICATION 1-584 6.3.1 Qualification of New Products 1-585

6.3.l.I Feasibility Phase (Checkpoint A) 1-586 6.3.1.2 Development Phase (Checkpoint B) 1-587 6.3.1.3 Field Performance (Checkpoint C) 1-589

6.4 MANUFACTURING LINE MODELING AND SIMULATION 1-590 6.5 PROCESS CONTROL 1-592

6.5.1 Factors Required for Process Control 1-594 6.5.1.1 Documented Process 1-594 6.5.1.2 Quantified and Qualified Capability 1-596 6.5.1.3 Documented and Available Work Instructions 1-497 6.5.1.4 Operators Certified in Their Operations 1-599 6.5.1.5 Process Monitors 1-599 6.5.1.6 Equipment Calibrated and Monitored 1-600 6.5.1.7 Requalification Process 1-601 6.5.1.8 Incoming Materials Under Control 1-602 6.5.1.9 Work-in-Process (WIP) Control 1-604

6.5.1.10 Internal Audits 1-605 6.5.1.11 Closed-Loop Management Review 1-606

6.5.2 Process Control Summary 1-607 6.6 WORLDWIDE QUALITY STANDARD-ISO 9608 1-608

6.6.1 Steps to ISO 9610 Registration 1-610 6.6.1.1 Establish Responsibility and Authority 1-610 6.6.1.2 Generate a Quality Manual 1-611 6.6.1.3 Document "What You Do" 1-611 6.6.1.4 Deploy the System 1-612 6.6.1.5 Establish a Measurement System, Prepare for Assessment,

and Determine Readiness 1-613 6.6.1.6 Contract with a Registrar 1-614 6.6.1.7 Celebrate 1-614

6.7 SUMMARY 6.8 REFERENCES

1-614 1-614

6.9 APPENDIX: THE 20 ELEMENTS OF ISO 9001 1-618

GLOSSARY AND SYMBOLS 1-621

AUTHORS' BIOGRAPHIES 1-667

INDEX 1-689

CONVERSION FACTORS

Length 1 m = 1010 A 1 A = 1O- IO m

1 nm = 10-9 m 1 J,Lm = 10-6 m 1 mm = 10-3 m

1 m = 109 nm 1 m = 106 J,Lm

1 m = 103 mm I m = 102 em

1 mm = 0.0394 in. 1 em = 0.394 in. I m = 3.28 ft

1 m2 = 104 em2

I mm2 = 10-2 em" I m" = 10.76 ft"

Area

1 em2 = 0.1550 in. 2

1 em = 10- 2 m 1 in. = 25.4 mm 1 in. = 2.54 em 1 ft = 0.3048 m

1 em" = 10-4 m" I em" = 102 mm"

I ft2 = 0.093 m2

I in. 2 = 6.452 em2

Volume 1 m3 = 106 em3

1 mm3 = 10-3 em3

1 m3 = 35.32 ft3 1 em} = 0.0610 in. 3

1 Mg = IQ3 kg 1 kg = IQ3 g 1 kg = 2.205 Ibm

Mass

I em3 = 10-6 m3

I em3 = 103 mm3

1 ft3 = 0.0283 m3

I in. 3 = 16.39 em3

I kg = 10-3 Mg I g = 10-3 kg

1 g = 2.205 X IO-} Ibm I Ibm = 0.4536 kg 1 Ibm = 453.6 g

1 kg/m3 = 10-3 g/em3

1 Mg/m3 = 1 g/em3

1 kg/m3 = 0.0624 Ibm/ft3 1 g/em3 = 62.4 Ibm/ft 3

I g/em3 = 0.0361 Ibm/in.3

Density 1 g/em3 = IQ3 kg/m3

I g/em3 = I Mg/m3

1 Ibm/ft3 = 16.02 kg/m3 I Ibm/ft3 = 1.602 x 10-2 g/em3

I Ibm/in. 3 = 27.7 g/em3

I-xx CONVERSION FACTORS

Unit conversion factors begin on previous page.

Force 1 N = lOS dynes 1 dyne = IO-s N I N = 0.2248 Ibr I Ibr = 4.448 N

Stress I MPa = 145 psi I MPa = 0.102 kg/mm2

I Pa = 10 dynes/cm2

I kg/mm2 = 1422 psi

1 psi = 6.90 x 10-3 MPa I kg/mm2 = 9.806 MPa

I dyne/cm2 = 0.10 Pa I psi = 7.03 x 10-4 kg/mm2

Fracture Toughness I psi Yin. = 1.099 X 10-3 MPaVrn I MPa Vrn = 910 psi Yin.

Energy I J = 107 ergs I J = 6.24 X 10 18 eV 1 J = 0.239 cal 1 J = 9.48 X 10-4 Btu I J = 0.738 ft-Ib r

I eV = 3.83 x 10-20 cal I cal = 3.97 x 10-3 Btu

1 erg = 10-7 J I eV = 1.602 x 10- 19 J 1 cal = 4.184 J

I Btu = 1054 J 1 ft-Ibr = 1.356 J

1 cal = 2.61 x 10 19 eV I Btu = 252.0 cal

Power I W = 0.239 calls 1 calls = 4.184 W I W = 3.414 Btu/h 1 Btu/h = 0.293 W

I calls = 14.29 Btu/h I Btu/h = 0.070 calls

Viscosity I Pa-s = 10 PIP = 0.1 Pa-s

Temperature, T T(K) = 273 + T(°C) T(K) = i[T(°F) - 32] + 273 T(°C) = i[T(OF) - 32]

T(OC) = T(K) - 273 T(°F) = i[T(K) - 273] + 32 T(°F) = feT(°C)] + 32

Specific Heat I J/kg-K = 2.39 x 10-4 cal/g-K I J/kg-K = 2.39 x 10-4 Btullbm-OF

I cal/g_OC = 1.0 Btullbm-oF

I cal/g-·C = 4184 J/kg-K I Btullbm-oF = 4184 J/kg-K I Btu/lbm-oF = 1.0 cal/g-K

Thermal Conductivity 1 W/m-K =2.39 x 10-3 callcm-s-K 1 callcm-s-K = 418.4 W/m-K I W/m-K = 0.578 Btu/ft-h_oF I Btu/ft-h_oF = 1.730 W/m-K

1 cal/cm-s-K = 241.8 Btu/ft-h-oF 1 Btu/ft-h_oF = 4.136 x 10-3 callcm-s-K

CONVERSION FACTORS

Unit Abbreviations

A == ampere A == angstrom

Btu == British thermal unit C == Coulomb

°C == degrees Celsius cal == calorie (gram) cm == centimeter eV == electron volt of == degrees Fahrenheit ft == foot

in. == inch J == joule

K == degrees Kelvin kg == kilogram lbr == pound force

Ibm == pound mass m == meter

g == gram

Mg == megagram mm == millimeter mol == mole

MPa == megapascal

SI Multiple and Submuldple Prefixes

Factor by Which Multiplied Prefix

109 giga 106 mega 103 kilo 10-2 centia

10-3 milli 10-6 micro 10-9 nano 10- 12 pico

U Avoided when possible.

N == newton nm == nanometer

P == poise Pa = pascal

s == second

I-xxi

T == temperature f.Lm = micrometer

(micron) W == watt psi = pounds per square

inch

Symbol

G M k c m

f.L n p

Parts 1, 2, and 3

SUMMARY OF CONTENTS

PART 1. MICROELECTRONICS PACKAGING HANDBOOK: TECHNOLOGY DRIVERS

CHAPTER 1. MICROELECTRONICS PACKAGING-AN OVERVIEW TECHNOLOGY DRIVERS PACKAGING TECHNOLOGIES CHIP-LEVEL INTERCONNECTIONS FIRST-LEVEL PACKAGES PACKAGE-TO-BOARD INTERCONNECTIONS SECOND-LEVEL PACKAGES PACKAGING COOLING PACKAGE SEALING AND ENCAPSULATION BOOK ORGANIZATION AND SCOPE

CHAPTER 2. PACKAGE WIRING AND TERMINALS THE WIRING MODEL AND ITS VARIABLES RESULTS OF CHIP CIRCUIT PLACEMENT AND WIRING VERSUS MODEL

PREDICTIONS WIREABILITY OF HIGHER-LEVEL PACKAGES CONCLUSIONS AND CHALLENGES FOR FUTURE WORK

CHAPTER 3. PACKAGE ELECTRICAL DESIGN CIRCUIT ATTRIBUTES SIGNAL DISTRIBUTION POWER DISTRIBUTION NOISE CONTAINMENT LOW-LOSS TRANSMISSION SYSTEMS PACKAGE MODELING THE DESIGN SPACE SYSTEM IMPACT PACKAGE IMPROVEMENTS APPENDIX: CALCULATION OF PEAK AVERAGE CURRENT SLEW RATE

CHAPTER 4. HEAT TRANSFER IN ELECTRONIC PACKAGES HEAT-TRANSFER FUNDAMENTALS EXPERIMENTAL TECHNIQUES AND INSTRUMENTATION

I-xxiv SUMMARY OF CONTENTS

TYPICAL COOLING DESIGNS RECENT PACKAGING HEAT TRANSFER DEVELOPMENTS

CHAPTER 5. PACKAGE RELIABILITY RELIABILITY METROLOGY CONTACT RESISTANCE ENVIRONMENTAL INTERACTIONS THERMAL MISMATCH AND THERMAL FATIGUE MECHANICAL LOADING TRIBOLOGICAL DEGRADATION HEAT-TRANSFER DEGRADATION APPENDIX-PROBABILITY DENSITY TABLE

CHAPTER 6. PACKAGE MANUFACTURE QUALITY IN PRODUCT AND PROCESS DESIGN PRODUCT QUALIFICATION MANUFACTURING LINE MODELING AND SIMULATION PROCESS CONTROL WORLDWIDE QUALITY STANDARD-ISO 9608 APPENDIX: THE 20 ELEMENTS OF ISO 9001

PART 2. MICROELECTRONICS PACKAGING HANDBOOK: SEMICONDUCTOR PACKAGING


CHAPTER 8. CHIP-TO-PACKAGE INTERCONNECTIONS CHIP-LEVEL INTERCONNECTION EVOLUTION FLIP-CHIP SOLDER-BUMP CONNECTIONS WIREBONDING TAPE AUTOMATED BONDING PRESSURE CONNECTS ADHESIVE BONDING ELECTRICAL PARAMETERS OF INTERCONNECTIONS DENSITY OF CONNECTIONS

CHAPTER 9. CERAMIC PACKAGING EARLY CERAMIC PACKAGING ALUMINA CERAMIC PACKAGING

SUMMARY OF CONTENTS

STATE-OF-THE-ART ALUMINA PACKAGING AND APPLICATIONS RECENT DEVELOPMENTS IN CERAMIC PACKAGING LOW-TEMPERATURE CERAMIC OR GLASS + CERAMIC PACKAGING STATE OF THE ART IN LOW-TEMPERATURE CERAMIC PACKAGING CHIP ATTACHMENT AND THERMAL DISSIPATION OF CERAMIC

SUBSTRATES CERAMIC PACKAGE RELIABILITY FUTURE CERAMIC PACKAGING

CHAPTER 10. PLASTIC PACKAGING MOLDING COMPOUNDS AND LEAD FRAME MATERIALS CHARACTERIZATION OF MOLDING-COMPOUND PROPERTIES THE TRANSFER-MOLDING PROCESS PACKING AND HANDLING QUALITY AND RELIABILITY FUTURE DEVELOPMENTS IN PLASTIC PACKAGES HEAT TRANSFER IN PLASTIC PACKAGES DIE ADHESIVES

CHAPTER 11. POLYMERS IN PACKAGING HISTORICAL PERSPECTIVE POL YMER THIN-FILM REQUIREMENTS FOR PACKAGING AND

SEMICONDUCTORS POLYMERIC DIELECTRICS POLYIMIDES COMMERCIAL PREIMIDIZED POL YIMIDE FILMS HIGH TEMPERATURE NON-POLYIMIDE DIELECTRICS PHOTOSENSITIVE POL YIMIDES IONIC BONDED-TYPE PSPIs PREIMIDIZED NONSHRINKING PHOTOSENSITIVE POL YIMIDES POSITIVE PHOTOSENSITIVE POL YIMIDES PHOTOSENSITIVE BENZOCYCLOBUTENE PHOTOSENSITIVE EPOXY MICROELECTRONIC APPLICATIONS OF PSPIs RESEARCH DEVELOPMENTSIFUTURE POLYMERS

CHAPTER 12. THIN·FILM PACKAGING ELECTRICAL PERFORMANCE THIN-FILM VERSUS THICK-FILM PACKAGES THIN-FILM MATERIALS AND PROCESSES YIELD/COST CONSIDERATIONS RELIABILITY COMMERCIAL APPLICATIONS OF THIN-FILM PACKAGING EMERGING COMMERCIAL TECHNOLOGIES IN THIN-FILM PACKAGING INTEGRATED PASSIVES IN THIN-FILM PACKAGING FUTURE DIRECTIONS OF THIN-FILM MATERIALS AND PROCESSES

CHAPTER 13. PACKAGE ELECTRICAL TESTING SUBSTRATE TEST SUBSTRATE TEST METHODS

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I-xxvi

COMPARISON OF TEST METHODS CONTACTS AND PROBES OPENS AND SHORTS TEST IMPLEMENTATION

SUMMARY OF CONTENTS

FUTURE ISSUES AND CHALLENGES IN SUBSTRATE TESTING FUNCTIONAL TESTS FUTURE ISSUES AND CHALLENGES IN FUNCTIONAL TESTING RECENT AND FUTURE DEVELOPMENTS

CHAPTER 14. PACKAGE SEALING AND ENCAPSULATION HERMETIC VERSUS NONHERMETIC PACKAGING IC FAILURE MECHANISMS PACKAGE SEALING AND ENCAPSULATION TYPES OF HERMETIC PACKAGES TYPES OF HERMETIC SEALS TESTING OF HERMETIC PACKAGES RELIABILITY TESTING RECENT ADVANCES IN SEALING AND ENCAPSULATION FUTURE DEVELOPMENTS

PART 3. MICROELECTRONICS PACKAGING HANDBOOK: SUBSYSTEM PACKAGING


CHAPTER 16. PACKAGE-TO-BOARD INTERCONNECTIONS SURFACE-MOUNTED PACKAGES SOLDER AND SOLDER JOINING FINE-PITCH TECHNOLOGY SOLDER PASTE AND ITS DEPOSITION RELIABILITY SURFACE-MOUNT ARRAY CONNECTIONS LEAD-FREE SOLDERS CONDUCTIVE ADHESIVES FUTURE DEVELOPMENT

CHAPTER 17. PRINTED-WIRING BOARD PACKAGING PRINTED-CIRCUIT STRUCTURES AND PROCESSES INTERCONNECTION TECHNOLOGY CONSIDERATIONS

SUMMARY OF CONTENTS

MATERIALS AND PROCESSES RELIABILITY AND CONTROLS RECENT DEVELOPMENTS IN PRINTED-CIRCUIT BOARDS FUTURE TRENDS IN PRINTED-CIRCUIT BOARDS

CHAPTER 18. COATED-METAL PACKAGING GENERAL CONSIDERATIONS METALS AND INSULATOR SUBSTRATES INSULATORS METALLIZATION METHODS SUBSTRATE FABRICATION AND ASSEMBLY PROCESSES PROPERTIES OF COATINGS DESIGN RULES NEW OPPORTUNITIES

CHAPTER 19. CONNECTOR AND CABLE PACKAGING TYPES OF CONNECTORS CONNECTOR REQUIREMENTS APPROACHES TO MCM LEVEL-2 INTERCONNECTIONS OPTICAL-FIBER CONNECTORS CONNECTOR RELIABILITY CONNECTOR STANDARDS ACTIVITIES CABLES CABLE SIGNAL THEORY FUTURE CONNECTORS AND CABLES

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CHAPTER 20. PACKAGING OF OPTOELECTRONICS WITH ELECTRONICS OPTOELECTRONIC DEVICES AND INTERCONNECTION MEDIA TECHNIQUES FOR INTEGRATING OPTOELECTRONICS WITH ELECTRONICS SYSTEM APPLICATIONS FOR OPTOELECTRONICS INTEGRATED WITH

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