Microcontroller Specification Final

CSE 320 Micro-controller Specification DuoLu

Outline Themicrocontroller(similartoMicrochipPIC12,simplifiedextensively,notcompatibleininstructionset)inthisprojectisa3cyclenonpipeline8bitHarvardstructuremicrocontroller,illustratedasthefollowingblockdiagram.Thestagegroupincludescomponentsworkinginthatstage.Datapathisshownasblackarrows,andcontrolsignalsareredarrows.

Thefollowingtwotypeofcomponentsholdprogrammingcontext.

Programcounter,programmemory,datamemory,accumulator,statusregister(greenboxes).Theyareprogrammervisibleregistersandmemories.

Instructionregisteranddataregister(purpleboxes).Theyareprogrammerinvisibleregisters.

Thefollowingtwotypeofcomponentsarebooleanlogicsthatdotheactualcomputationwork.Theyarestateless

ALU,MUX1,MUX2,Adder(blueboxes),usedasfunctionalunit. ControlLogic(yellowbox),usedtodenoteallcontrolsignals(redsignal)

Thetimingandstatetransitionisshowninthefollowingdiagram.

Eachinstructionneeds3clockcyclestofinish,i.e.FETCHstage,DECODEstage,andEXECUTEstage.Notethatitisnotpipelined.TogetherwiththeinitialLOADstate,itcanbeconsideredasaFSMof3states(technically4states).States:

1. LOAD(initialstate):loadprogramtoprogrammemory,whichtakes1cycleperinstructionloaded

2. FETCH(firstcycle):fetchcurrentinstructionfromprogrammemory3. DECODE(secondcycle):decodeinstructiontogeneratecontrollogic,readdata

memoryforoperand4. EXECUTE(ofthirdcycle):executeinstruction

Transitions:

1. LOAD>FETCH(initializationfinish)

a. ClearcontentofPC,IR,DR,Acc,SRDMemisnotrequiredtobecleared.2. FETCH>DECODE(risingedgeofsecondcycle)

a. IR=PMem[PC]3. DECODE>EXECUTE(risingedgeofthirdcycle)

a. DR=DMem[IR[3:0]]4. EXECUTE>FETCH(risingedgeoffirstcycleandfourthcycle)

a. Fornonbranchinstruction,PC=PC+1forbranchinstruction,ifbranchistaken,PC=IR[7:0],otherwisePC=PC+1

b. ForALUinstruction,iftheresultdestinationisaccumulator,Acc=ALU.Outiftheresultdestinationisdatamemory,DMem[IR[3:0]]=ALU.Out.

c. ForALUinstruction,SR=ALU.StatusThetransitionscanbesimplifiedusingenableportofcorrespondingregisters,e.g.assignALU.OuttoAccateveryclockrisingedgeifAcc.Eissetto1.SuchcontrolsignalsasAcc.Earegeneratedasabooleanfunctionofbothcurrentstateandthecurrentinstruction.

Components Registers Themicrocontrollerhas3programmervisibleregister:

1. ProgramCounter(8bit,denotedasPC):containstheindexofcurrentexecutinginstruction.

2. Accumulator(8bit,denotedasAcc):holdsresultand1operandofthearithmeticorlogiccalculation.

3. StatusRegister(4bit,denotedasSR):holds4statusbit,i.e.Z,C,S,O.a. Z(zeroflag,SR[3]):1ifresultiszero,0otherwise.b. C(carryflag,SR[2]):1ifcarryisgenerated,0otherwise.c. S(signflag,SR[1]):1ifresultisnegative(as2scomplement),0otherwise.d. O(overflowflag,SR[0]):1ifresultgeneratesoverflow,0otherwise.

Eachoftheseregistershasanenableport,asaflagforwhetherthevalueoftheregistershouldbeupdatedinstatetransition.TheyaredenotedasPC.E,Acc.E,andSR.E.Themicrocontrollerhas2programmerinvisibleregister(i.e.theycannotbemanipulatedbyprogramer):

1. InstructionRegister(12bit,denotedasIR):containsthecurrentexecutinginstruction.2. DataRegister(8bit,denotedasDR):containstheoperandreadfromdatamemory.

Similarly,eachoftheseregistershasanenableportasaflagforwhetherthevalueoftheregistershouldbeupdatedinstatetransition.TheyaredenotedasIR.E,andDR.E.

Program memory Themicrocontrollerhasa256entryprogrammemorythatstoresprograminstructions,denotedasPMem.Eachentryis12bits,theithentryisdenotedasPMem[i].Theprogrammemoryhasthefollowinginput/outputports.

Enableport(1bit,input,denotedasPMem.E):enablethedevice,i.e.ifitis1,thentheentryspecifiedbytheaddressportwillbereadout,otherwisenothingisreadout.

Addressport(8bit,input,denotedasPMem.Addr):specifywhichinstructionentryisreadout,connectedtoPC.

Instructionport(12bit,output,denotedasPMem.I):theinstructionentrythatisreadout,connectedtoIR.

3specialportsareusedtoloadprogramtothememory,notusedforexecutinginstructions.

Loadenableport(1bit,input,denotedasPMem.LE):enabletheload,i.e.ifitis1,thentheentryspecifiedbytheaddressportwillbeloadwiththevaluespecifiedbytheloadinstructioninputportandtheinstructionportissuppliedwiththesamevalueotherwise,theentryspecifiedbytheaddressportwillbereadoutoninstructionport,andvalueoninstructionloadportisignored.

Loadaddressport(8bit,input,denotedasPMem.LA):specifywhichinstructionentryisloaded.

Loadinstructionport(12bit,input,denotedasPMem.LI):theinstructionthatisloaded.Forexample,iftheaddresspointissuppliedwith8b0000_0011andenableissetto1,thefourthentryisreadoutoninstructionport.Notethatprogramloadonlytakeseffectonclockrisingedge,whileinstructionreadouthappensallthetime.

Data memory Themicrocontrollerhasa16entrydatamemory,denotedasDMem.Eachentryis8bits,theithentryisdenotedasDMem[i].Theprogrammemoryhasthefollowinginput/outputports.

Enableport(1bit,input,denotedasDMem.E):enablethedevice,i.e.ifitis1,thentheentryspecifiedbytheaddressportwillbereadoutorwritteninotherwisenothingisreadoutorwrittenin.

Writeenableport(1bit,input,denotedasDMem.WE):enablethewrite,i.e.ifitis1,thentheentryspecifiedbytheaddressportwillbewrittenwiththevaluespecifiedbythedatainputportandthedataoutputportissuppliedwiththesamevalueotherwise,theentryspecifiedbytheaddressportwillbereadoutondataoutputport,andvalueondatainputportisignored.

Addressport(4bit,input,denotedasDMem.Addr):specifywhichdataentryisreadout,connectedtoIR[3:0].

Datainputport(8bit,input,denotedasDMem.DI):thevaluethatiswrittenin,connectedtoALU.Out.

Dataoutputport(8bit,output,denotedasDMem.DO):thedataentrythatisreadout,connectedtoMUX2.In1.

Forexample,iftheaddresspointissuppliedwith80000_0011,datainputportissuppliedwith80000_0000,enableissetto1,andwriteenableissetto1,thefourthentryofthedatamemoryiswrittenwithvalue0andthedataoutputportshows80000_0000.Asanotherexample,iftheaddresspointissuppliedwith80000_0011,datainputportissuppliedwith80000_0000,enableissetto1,whilewriteenableissetto0,thefourthentryofthedatamemoryisreadoutondataoutputport.Notethatwriteonlytakeseffectonclockrisingedge,whilereadhappensallthetime,similartoprogrammemory.

PC adder PCadderisusedtoaddPCby1,i.e.movetothenextinstruction.Thiscomponentispurecombinational.Ithasthefollowingport.

Adderinputport(8bit,input,denotedasAdder.In):connectedtoPC. Adderoutputport(8bit,output,denotedasAdder.Out):connectedtoMUX1.In2.

MUX1 MUX1isusedtochoosethesourceforupdatingPC.Ifthecurrentinstructionisnotabranchoritisabranchbutthebranchisnottaken,PCisincrementedby1otherwisePCissettothejumpingtarget,i.e.IR[7:0].Ithasthefollowingport.

MUX1input1port(8bit,input,denotedasMUX1.In1):connectedtoIR[7:0]. MUX1input2port(8bit,input,denotedasMUX1.In2):connectedtoAdder.Out. MUX1selectionport(1bit,input,denotedasMUX1.Sel):connectedtocontrollogic. MUX1outputport(8bit,output,denotedasMUX1.Out):connectedtoPC.

ALU ALUisusedtodotheactualcomputationforthecurrentinstruction.Thiscomponentispurecombinational.Ithasthefollowingport.ThemodeofALUislistedinthefollowingtable.

ALUoperand1port(8bit,input,denotedasALU.Operand1):connectedtoAcc. ALUoperand1port(8bit,input,denotedasALU.Operand2):connectedtoMUX2.Out. ALUenableport(1bit,input,denotedasALU.E):connectedtocontrollogic. ALUmodeport(4bit,input,denotedasALU.Mode):connectedtocontrollogic. Currentflagsport(4bit,input,denotedasALU.CFlags):connectedtoSR. ALUoutputport(8bit,output,denotedasALU.Out):connectedtoDMem.DI.

ALUflagsport(4bit,output,denotedasALU.Flags):theZ(zero),C(carry),S(sign),O(overflow)bits,fromMSBtoLSB,connectedtostatusregister.

mode(binary) mode(hex) function comments(instructions)

0000 0 Out=Operand1+Operand2

0001 1 Out=Operand1Operand2

0010 2 Out=Operand1 forMOVAM

0011 3 Out=Operand2 forMOVMAandMOVIA

0100 4 Out=Operand1ANDOperand2

0101 5 Out=Operand1OROperand2

0110 6 Out=Operand1XOROperand2

0111 7 Out=Operand2Operand1

1000 8 Out=Operand2+1

1001 9 Out=Operand21

1010 A Out=(Operand28Operand1[2:0])

forROTATEL

1011 B Out=(Operand2>>Operand1[2:0])|(Operand2>Operand1[2:0] arithmeticshiftright

1111 F Out=0Operand2 2scomplement

MUX2 MUX1isusedtochoosethesourceforoperand2ofALU.IfthecurrentinstructionisMtype,operand2ofALUcomesfromdatamemoryifthecurrentinstructionisItype,operand2ofALUcomesfromtheinstruction,i.e.IR[7:0].Ithasthefollowingport.

MUX2input1port(8bit,input,denotedasMUX2.In1):connectedtoIR[7:0]. MUX2input2port(8bit,input,denotedasMUX2.In2):connectedtoDR. MUX2selectionport(1bit,input,denotedasMUX2.Sel):connectedtocontrollogic. MUX2outputport(8bit,output,denotedasMUX2.Out):connectedtoALU.Operand2.

Instruction Set Eachinstructionis12bits.Thereare3typesofinstructionsbyencoding,shownasfollowing:

1. Mtype:oneoperandisaccumulator(sometimesignored)andtheotheroperandisfromdatamemorytheresultcanbestoredintoaccumulatororthedatamemoryentry(sameentryasthesecondoperand).

2. Itype:oneoperandisaccumulatorandtheotheroperandisimmediatenumberencodedininstructiontheresultisstoredintoaccumulator.

3. Stype:specialinstruction,nooperandrequired.(e.g.NOP)Theinstructionencodingspaceisshowninthefollowingtable.

codespace(binary)

codespace

(hex)

instructions #ofins

comments

0000_0000_00000000_1111_1111

0000FF

specialinstructions(Stype) 256 CurrentlyonlyNOPused,255freeslots

0001_0000_00000001_1111_1111

1001FF

unconditionaljump(Itype) 1 GOTO

0010_0000_00000011_1111_1111

2003FF

ALUinstructions(Mtype) 32 16instructions,2destinationchoiceseach

0100_0000_00000111_1111_1111

4007FF

conditionaljump(Itype) 4 JZ,JC,JS,JC

1000_0000_00001111_1111_1111

800FFF

ALUinstructions(Itype) 8 Currently7used,1freeslot

Theseinstructionscanbegroupedinto4categorybyfunction.

1. ALUinstruction:usingALUtocomputeresult2. Unconditionalbranch:theGOTOinstruction3. Conditionalbranch:theJZ,JC,JS,JOinstruction

4. Specialinstruction:theNOP.

M type instructions ThegeneralformatofMtypeinstructionisshownasfollowing.

ThefollowingtablecontainsthedetailedinformationofeachMtypeinstruction.Notethataaaaencodesthe4bitaddressofdatamemory,andthedbitmeansdestinationoftheresult,i.e.ifd=1,resultiswrittentoAcc,otherwisetheresultiswrittentothesamememorylocationastheoperand.NotethatallMtypeinstructionsareALUinstructions.

instructionmnemonics

function encoding(binary)

statusaffected

example(encoding)(assembly)(meaning)

ADD addamemoryentrywithaccumulator

001d_0000_aaaa Z,C,S,O 0011_0000_0001ADDAcc,Acc,DMem[1](Acc=Acc+DMem[1])

SUBAM subtractaccumulatorbyamemoryentry

001d_0001_aaaa Z,C,S,O 0011_0001_0000SUBAMAcc,Acc,DMem[0](Acc=AccDMem[0])

MOVAM movethevalueofaccumulatortoamemoryentry

0010_0010_aaaa none 0010_0010_0000MOVAMDMem[0],Acc(Acc=DMem[0])

MOVMA movethevalueofamemoryentrytoaccumulator

0011_0011_aaaa none 0011_0011_0000MOVMAAcc,DMem[0](DMem[0]=Acc)

AND bitwiseANDamemoryentrywithaccumulator

001d_0100_aaaa Z 0010_0100_0000ANDDMem[0],Acc,DMem[0](DMem[0]=DMem[0]ANDAcc)

OR bitwiseORamemoryentrywithaccumulator

001d_0101_aaaa Z 0010_0101_0000ORDMem[0],Acc,DMem[0](DMem[0]=DMem[0]ORAcc)

XOR bitwiseXORamemoryentrywithaccumulator

001d_0110_aaaa Z 0010_0110_0000XORDMem[0],Acc,DMem[0](DMem[0]=DMem[0]XORAcc)

SUBMA subtractamemoryentrybyaccumulator

001d_0111_aaaa Z,C,S,O 0010_0001_0000SUBAMDMem[0],DMem[0],Acc(DMem[0]=DMem[0]Acc)

INC incrementamemoryentry 0010_1000_aaaa Z,C,S,O 0011_1000_0000INCDMem[0](DMem[0]=DMem[0]+1)

DEC decrementamemoryentry 0010_1001_aaaa Z,C,S,O 0011_1001_0000DECDMem[0](DMem[0]=DMem[0]1)

ROTATEL circulativeshiftleftamemoryentry,bythenumberofbitsspecifiedbyaccumulator

0010_1010_aaaa none 0010_1010_0000ROTATELDMem[0](seecommentsbelow)

ROTATER circulativeshiftleftamemoryentry,bythenumberofbitsspecifiedbyaccumulator

0010_1011_aaaa none 0010_1011_0000ROTATERDMem[0](seecommentsbelow)

SLL shiftamemoryentryleft,bythenumberofbitsspecifiedbyaccumulator

0010_1100_aaaa Z,C 0010_1100_0000SLLDMem[0](seecommentsbelow)

SRL shiftamemoryentryright,logical(fill0),bythenumberof

0010_1101_aaaa Z,C 0010_1101_0000SRLDMem[0]

bitsspecifiedbyaccumulator (seecommentsbelow)

SRA shiftamemoryentryright,arithmetic(filloriginalMSB),bythenumberofbitsspecifiedbyaccumulator

0010_1110_aaaa Z,C,S 0010_1110_0000SRADMem[0](seecommentsbelow)

COMP take2scomplementofamemoryentry,i.e.0subtractedbythememoryentry

0010_1111_aaaa Z,C,S,O 0010_1111_0000COMPDMem[0](DMem[0]=DMem[0])

Comments:

1. Forcirculativeshift,onlytheoperandfrommemoryentryisrotated,i.e.flagsarenotinvolved.Forexample,if8b1000_0000isshiftedleftcirculativefor1bit,itbecomes8b0000_0001,andnoflagisaffected.

2. Forlogicalshiftinstructions,0isalwaysfilledin,andCflagissettothelastbitthatisshiftedout.Forexample,if8b1000_0000isshiftedleftlogicallyfor1bit,itbecomes8b0000_0000,andC=1.Anotherexample,if8b0000_0100isshiftedrightlogicallyfor3bit,itbecomes8b0000_0000,andC=1.Ifnobitisshiftedout,ZflagandCflagarenotaffected.

3. Forarithmeticshiftrightinstructions,theMSBisfilledin,andCflagissettothelastbitthatisshiftedout.Forexample,if8b1000_0001isshiftedrightarithmeticallyfor1bit,itbecomes8b1100_0000,andC=1.Anotherexample,if8b0000_0100isshiftedrightarithmeticallyfor3bit,itbecomes8b0000_0000,andC=1.Ifnobitisshiftedout,ZflagandCflagarenotaffected.

I type instructions ThegeneralformatofMtypeinstructionisshownasfollowing.

ThefollowingtablecontainsthedetailedinformationofeachMtypeinstruction.NotethatItypeinstructionscontainsunconditionalbranch,conditionalbranch,andALUinstructions.


function encoding statusaffected

example(encoding)(assembly)(meaning)

GOTO unconditionalbranch 0001_xxxx_xxxx none 0001_0000_0111GOTO7(gotothe8thinstruction)

JZ jumptotheinstructionindexedbytheimmediatenumber,ifZflagis1

0100_xxxx_xxxx none 0100_0000_0111JZ7(gotothe8thinstructionifSR[3]==1)

JC jumptotheinstructionindexedbytheimmediatenumber,ifCflagis1

0101_xxxx_xxxx none 0101_0000_0111JC7(gotothe8thinstructionifSR[2]==1)

JS jumptotheinstructionindexedbytheimmediatenumber,ifSflagis1

0110_xxxx_xxxx none 0110_0000_0111JS7(gotothe8thinstructionifSR[1]==1)

JO jumptotheinstructionindexedbytheimmediatenumber,ifOflagis1

0111_xxxx_xxxx none 0111_0000_0111JO7(gotothe8thinstructionifSR[0]==1)

ADDI addaccumulatorwithimmediatenumber

1000_xxxx_xxxx Z,C,S,O 1000_0000_1000ADDIAcc,Acc,8(Acc=Acc+8)

SUBAI subtractaccumulatorbyimmediatenumber

1001_xxxx_xxxx Z,C,S,O 1001_0000_1000SUBAIAcc,Acc,8(Acc=Acc8)

RSV (reserved,donothing)(actuallyitmovethevalueofaccumulatortoaccumulator)

1010_xxxx_xxxx none

MOVIA moveimmediatenumbertoaccumulator

1011_xxxx_xxxx none 1011_0000_0000MOVIAAcc,0(Acc=0)

ANDI bitwiseANDaccumulatorwithimmediatenumber

1100_xxxx_xxxx Z 1100_0000_1111ANDIAcc,Acc,0x0F(Acc=AccAND0x0F)

ORI bitwiseORaccumulatorwithimmediatenumber

1101_xxxx_xxxx Z 1101_1111_0000ORIAcc,Acc,0xF0(Acc=AccOR0xF0)

XORI bitwiseXORaccumulatorwithimmediatenumber

1110_xxxx_xxxx Z 1110_0000_1111XORIAcc,Acc,0x0F(Acc=AccXOR0x0F)

SUBIA subtractaccumulatorbyimmediatenumber

1111_xxxx_xxxx Z,C,S,O 1111_0000_1000SUBIAAcc,8,Acc(Acc=8Acc)

S type instructions ThegeneralformatofStypeinstructionisshownasfollowing.

ThereisonlyoneStypeinstruction,i.e.theNOPinstruction.


function encoding statusaffected

example

NOP nooperation 0000_0000_0000 none NOP

Control Signal Controlsignalisderivedfromthecurrentstateandcurrentinstruction.Thecontrollogiccomponentispurelycombinational.Thereareintotal12controlsignals,listedasfollowing.

PC.E:enableportofprogramcounter(PC) Acc.E:enableportofaccumulator(Acc) SR.E:enableportofstatusregister(SR) IR.E:enableportofinstructionregister(IR) DR.E:enableportofdataregister(DR) PMem.E:enableportofprogrammemory(PMem) DMem.E:enableportofdatamemory(DMem) DMem.WE:writeenableportofdatamemory(DMem) ALU.E:enableportofALU ALU.Mode:modeselectionportofALU MUX1.Sel:selectionportofMUX1

MUX2.Sel:selectionportofMUX2Thefollowingtabledocumentsthedetailofhowthesecontrolsignalsaregenerated.importantsignalsaremarkedinred.

Ins Stage PC.E

Acc.E

SR.E

IR.E

DR.E

PMem.E

DMem.E

DMem.WE

ALU.E

ALU.Mode

MUX1.Sel

MUX2.Sel

NOP

(0000)

FETCH 0 0 0 1 0 1 0 0 0 x x x

DECODE 0 0 0 0 0 0 0 0 0 x x x

EXECUTE 1 0 0 0 0 0 0 0 0 x 1 x

GOTO

(0001)

FETCH 0 0 0 1 0 1 0 0 0 x x x

DECODE 0 0 0 0 0 0 0 0 0 x x x

EXECUTE 1 0 0 0 0 0 0 0 0 x 0 x

ALU

MType

(001x)

FETCH 0 0 0 1 0 1 0 0 0 x x x

DECODE 0 0 0 0 1 0 1 0 0 x x x

EXECUTE 1 R[8]I 1 0 0 0 IR[8] IR[8] 1 R[7 ]I : 4 1 1

JZ,JC,JS,JO

(01xx)

FETCH 0 0 0 1 0 1 0 0 0 x x x

DECODE 0 0 0 0 0 0 0 0 0 x x x

EXECUTE 1 0 0 0 0 0 0 0 0 x SR* x

ALU

IType

(1xxx)

FETCH 0 0 0 1 0 1 0 0 0 x x x

DECODE 0 0 0 0 0 0 0 0 0 x x x

EXECUTE 1 1 1 0 0 0 0 0 1 R[10 ]I : 8 1 0

Comments:

1. NotethatinEXECUTEstateofconditionalbranchinstructions,thevalueofMUX1.SelisactuallySR[IR[9:8]]

2. NotethatinEXECUTEstageofALUItypeinstruction,thevalueofALU.Modeisactually{0,IR[10:8]}.Inthetableabove0extensionisassumed.

3. BecarefulthatPMem.LEisnotshowninthistable.IftheprocessorisnotinLOADstate,PMem.LEisalwayssetto0.

Thetypeandcategoryofinstructioncanbeidentifiedbythefirst4bitsoftheinstruction,i.eIR[11:8],asdenotedinthefirstcolumnoftheabovetable.Besides,whenloadingtheprogram,thecontrolsignalisgeneratedasbelow.

State PMem.LE

PC.E

Acc.E

SR.E

IR.E

DR.E

PMem.E

DMem.E

DMem.WE

ALU.E

ALU.Mode

MUX1.Sel

MUX2.Sel

LOAD 1 0 0 0 0 0 1 0 0 0 x x x

IftheprocessorisinLOADstate,PMem.LEisalwayssetto1.

Sample Testing Program

Test1: Pogram loading, accumulator, and memory loading, GOTO

# instruction(binary)

instruction(assembly)

instruction(meaning)

0 0000_0000_0000 NOP (nooperation)

1 1011_0000_0001 MOVIAAcc,1 Acc=1

2 0010_0010_0000 MOVAMDMem[0],Acc DMem[0]=Acc=1

3 1011_0000_0000 MOVIAAcc,0 Acc=0

4 0011_0011_0000 MOVMAAcc,DMem[0] Acc=DMem[0]=1

5 0001_0000_0101 GOTO5 (jumptoitself,i.e.infiniteloop)

Test2: Addition and subtraction (M type)





1 1011_0000_0001 MOVIAAcc,1 Acc=1

2 0010_0010_0000 MOVAMDMem[0],Acc DMem[0]=Acc=1

3 0011_0000_0000 ADDAcc,Acc,DMem[0] Acc=Acc+DMem[0]=1+1=2

4 0010_0000_0000 ADDDMem[0],Acc,DMem[0] DMem[0] =Acc+DMem[0]=1+2=3

5 0011_0001_0000 SUBAMAcc,Acc,DMem[0] Acc=AccDMem[0]=23=1

6 0010_0001_0000 SUBAMDMem[0],Acc,DMem[0] DMem[0]=AccDMem[0]=(1)3=4

7 0011_0111_0000 SUBMAAcc,DMem[0],Acc Acc=DMem[0]Acc=(4)(1)=3

8 0010_0111_0000 SUBMADMem[0],DMem[0],Acc DMem[0]=DMem[0]Acc=(4)(3)=1

9 0001_0000_1001 GOTO9 (jumptoitself,infiniteloop)

Test3: Logic operation (M type)





1 1011_0000_0101 MOVIAAcc,0x05 Acc=0x05

2 0010_0010_0000 MOVAMDMem[0],Acc DMem[0]=Acc=0x05



5 1011_0000_0011 MOVIAAcc,0x03 Acc=0x03

6 0010_0100_0000 ADDDMem[0],Acc,DMem[0] DMem[0]=AccANDDMem[0]=0x03AND0x05=0x01

7 0010_0101_0001 ORDMem[1],Acc,DMem[1] DMem[1]=AccORDMem[1]=0x03OR0x05=0x07

8 0010_0110_0010 XORDMem[2],Acc,DMem[2] DMem[2]=AccXORDMem[2]=0x03XOR0x05=0x06


Test4: Addition, subtraction, logic operation (I type)





1 1011_0000_0001 MOVIAAcc,1 Acc=1

2 1010_0000_0000 RSV (reservedinstruction,donothing)

3 1000_0000_0111 ADDIAcc,Acc,7 Acc=Acc+7=1+7=8

4 1001_0000_0110 SUBAIAcc,Acc,6 Acc=Acc6=86=2

5 1111_0000_0111 SUBIAAcc,7,Acc Acc=7Acc=72=5

6 1100_0000_0011 ANDIAcc,Acc,0x03 Acc=AccAND0x03=0x05AND0x03=0x01

7 1101_0000_0101 ORIAcc,Acc,0x05 Acc=AccOR0x05=0x01OR0x05=0x05

8 1110_0000_0011 XORAcc,Acc,0x03 Acc=AccXOR0x03=0x05XOR0x03=0x06


Microcontroller Specification Final

Documents

Transcript of Microcontroller Specification Final