Micro transductors ’08 CMOS Basics Dr.-Ing. Frank Sill Department of Electrical Engineering,...

Micro transductors ’08Micro transductors ’08 CMOS CMOS BasicsBasics

Dr.-Ing. Frank SillDepartment of Electrical Engineering, Federal University of Minas Gerais,

Av. Antônio Carlos 6627, CEP: 31270-010, Belo Horizonte (MG), Brazil

[email protected]

http://www.cpdee.ufmg.br/~frank/

Micro transductors ‘08, CMOS Basics 2Copyright Sill, 2008

AnnouncementAnnouncement

Next class: Thursday, 13. March

Room 308 CCE


Optional TopicsOptional Topics

Please, choose 2 out of the following 4 topics

Final date: 14th of March

1. Future trends in VLSI design

2. Basics of Hspice-Simulations

3. Effects in nanometer CMOS circuits

4. Reliability problems in current and future designs


GoalsGoals

Where do we find Integrated Ciruits? History and Trends CMOS: basic ideas Logic gates Delay estimation Sizing


Where do we find chips?Where do we find chips?

Motivation Performance Flexibility Mobility

~ 2 % are processors ~ 6.5 Billion processors per year ~ 40 % of all parts are used in the PC area

0%

20%

40%

60%

80%

100%

Units Revenue

Processors

Memory

Logic

Analog

Discretes

Optoelectronics/ Sensors/Bipolar

Source: WSTS ‘02

„Computer are the workhorses of the semiconductors industry.“


ScenariosScenarios

Obviously tasks High performance demands Fast execution


Scenarios cont’dScenarios cont’d

Hidden helper Low performance demands


HistoryHistory

1906 – Semiconductors used to detect radio signals 1925 – FET concept patent by J. Lilienfeld 1941 – Z3 by Konrad Zuse – first computer 1946 – ENIAC – first electronic computer 1947 – Transistor “Invented”

AT&T ignores Lilienfeld Bardeen, Brattain and Schockley, AT&T, Nobel Prize in 1956

1958 – Integrated Circuit Kilby & Noyce (died 1990) Kilby - Noble Prize in 2000

1960 - MOSFET manufactured and patented 1963 - CMOS logic invented

Resistors replaced by transistors


History cont’dHistory cont’d

Zuse Z3 – First computer* (1941)

First working programmable, fully automatic computing machine

2,000 Relays Clock frequency of ~5 - 10 Hz Word length of 22 bits Programmed by punched film

stock Addition, Multiplication,

Division, Square root

* Elected at “1st International Conference on the History of Computing" in Paderborn, Germany, 1998



Electronic Numerical Integrator And Computer

At Moore School of Electrical Engineering, University of Pennsylvania

17,468 vacuum tubes, 7,200 diodes (+ ca. 80k resistors & capacitors)

5 Million hand-soldered joints

ENIAC – First electronic computer (1946)



Vacuum Tubes in ENIAC


Source: Weste,“CMOS VLSI design”,2003

(a) First transistor (1947, Bardeen & Brattain, Bell labs)

(b) First integrated circuit (1958, Kilby, AT&T)



Moore‘s LawMoore‘s Law

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

Log

2ofth

eN

um

ber

ofC

om

ponents

Per

Inte

gra

ted

Function

Year

1959

1960

1961

1962

1963

1964

1965

1966

1967

1968

1969

1970

1971

1972

1973

1974

1975

YearSource: Moore, 1665

Log

2 o

f num

ber

of c

omp

one

nts

per

inte

gra

ted

func

tion

Prediction by Gordon Moore in 1965

Semiconductor technology will double its effectiveness every 18 months


Moore’s Law cont’dMoore’s Law cont’d

Source: Moore, ISSCC 2003


Trend: Cost per functionTrend: Cost per functionP

rice

of a

tra

nsis

tor


Trend: PerformanceTrend: Performance

0,01

0,1

1

10

100

1000

10000

100000

1000000

1970 1980 1990 2000 2010 2020

MIPS

1 TIPS

8080

8086

386 Pentium® proc

Pentium® 4 proc



Trend: PowerTrend: Power



Trend: Power DensityTrend: Power Density

40048008

80808085

8086

286386

486Pentium®

P4

1

10

100

1000

10000

1970 1980 1990 2000 2010

Year

Po

wer

Den

sity

(W

/cm

2)

Hot Plate

NuclearReactor

RocketNozzle

Sun’sSurface

Prescott Pentium®



DimensionsDimensions

1 m10 cm1 cm1 mm100 µm

10 µm100 nm

„65 nm“-Transistor Source: Intel

Source: „Spektrum der Wissenschaften“


The CMOS TechnologyThe CMOS Technology

CMOS = Complementary Metal Oxide Semiconductor

Currently most applied logic family Main advantages:

Low Power (compared to other technologies) Very good scalability High Speed High packaging density


The CMOS Technique cont’dThe CMOS Technique cont’d

Main Idea: Combination of two complementary switches Switches are metal-oxide-semiconductor field-effect

transistors (MOSFET) Realization of logic gates (AND, NAND, …)

“Metal–Oxide–Semiconductor“: Physical structure of MOSFETs (metal gate electrode,

oxide insulator, semiconductor material) Today: polysilicon instead of metal


What is a transistor?What is a transistor?

Source: Rabaey,“Digital Integrated Circuits”,1995

S D


PMOS and NMOSPMOS and NMOS

g

s

d

g = 0

s

d

g = 1

s

d

g

s

d

s

d

s

d

nMOS

pMOS

OFF ON

ON OFF



NMOS-TransistorNMOS-Transistor

@NMOS: Body is (commonly) tied to ground (0 V)

@PMOS: Body is (commonly) tied to VDD

n+

p

GateSource Drain

bulk Si

SiO2

Polysilicon

n+D

G

S



NMOS-Transistor (2)NMOS-Transistor (2)

n+ n+

p-type body

polysilicongate

Gate length

L


Gate-widthW

SiO2 gate oxide(good insulator, eox = 3.9

tox – thickness of oxide layer

tox



Cross section of NMOS and PMOSCross section of NMOS and PMOS


Layout Mask SetLayout Mask Set

Transistors and wires are defined by masks Cross-section taken along dashed line

GND VDD

Y

A

substrate tap well tapnMOS transistor pMOS transistor


Drain

Gate

Source

Vds

Vgs

Ids

I-V Curves of NMOSI-V Curves of NMOS



Gate

Vgs < Vth

DrainSource

Gate

Vgs > Vth

DrainSource

Threshold Voltage VThreshold Voltage Vthth

Transistor characteristic

If: „Gate-Source“-Voltage Vgs higher than Vth

Channel under Gate Current between Drain and Source

If: Vgs lower than Vth

No current

Source Drain

Gate

Ids


Logic GatesLogic Gates

Task (e.g. calculation)

Transfer into Logic Gates (Synthesis)

Gate characteristics: Delay Power dissipation more ...

Gates realized by transistors

Transistors determine gate characteristics

Y = A+B


Example: Half-adderExample: Half-adder

How do you add the two bits A0 and B0 in binary logic?

So called Half-adder:

A0 B0 Result Carry Sum

0 0 00 0 0

1 0 01 0 1

0 1 01 0 1

1 1 10 1 0

HA

A0 B0

Sum

CarryIn1 (A0) In2 (B0) AND XOR

0 0 0 0

1 0 0 1

0 1 0 1

1 1 1 0

A0 B0

Carry

Sum


CMOS SchemeCMOS Scheme

OUT

PUN

PDN

IN1 …INx

PUN – Pull-up Network

PDN – Pull-down Network

VDD (supply voltage)

GND (ground)


CMOS InverterCMOS Inverter

OUTIN1

IN1 OUT

0 (GND) 1 (VDD)

1 (VDD) 0 (GND)

OUT

IN1

VDD

GND


Transistor as Water-tapTransistor as Water-tap


Transistor as Water-tap cont’dTransistor as Water-tap cont’d

Voltage (Volt, V) Water pressure (bar)

Current (Ampere, A) Water quantity (liter)

-

0 Volt

1 Volt

0 Volt

1 Volt

1 Volt

0 Volt

-

1 Volt

? Volt

-

1 Volt

1 Volt

-

1 Volt

0 Volt? Volt1 Volt

Source: Timmernann, 2007


VDD VDD

In1In2

GND

Out

T3 T2

T1

T0

NAND GateNAND Gate

In1

In2Out

Pull-up Network

Pull-down Network

In1 In2 PUN PDN Out

1 1 OFF ON 0

0 1 ON OFF 1

1 0 ON OFF 1

0 0 ON ON 1

X X

X

X


VDD

In1

In2

GND

Out

T3

T2

T1 T0

GND

NOR GateNOR Gate

Pull-up Network

Pull-down Network

In1 In2 PUN PDN Out

1 1 OFF ON 0

0 1 OFF ON 0

1 0 OFF ON 0

0 0 ON OFF 1

X

X

X X


AND and OR GateAND and OR Gate

In1 In2 OutAND OutNAND

1 1 1 0

0 1 0 1

1 0 0 1

0 0 0 1

In1 In2 OutOR OutNOR

1 1 1 0

0 1 1 0

1 0 1 0

0 0 0 1

AND

OR

NAND INV

NOR INV


Delay DefinitionsDelay Definitions

t

Vout

Vin

inputwaveform

outputwaveform

t

50%

tpHL

50%

tpLH

tf

90%

10%

tr

signal slopes

Vin Vout

Propagation delay tp


RC-Delay ModelRC-Delay Model

Simple but effective delay model Use equivalent circuits for MOS transistors

Ideal switch Transistor capacitances ON resistance ( = when transistor is conducting (=ON)

channel between Drain to Source acts as resistor) Delay t ~ R*C


MOSFET capacitancesMOSFET capacitances

Source Drain

Gate

CSB CDB

CGB

Bulk

CGS CGD

Any two conductors separated by an insulator create a capacitor

MOS capacitances have three origins: The basic MOS structure The channel charge The pn-junctions depletion regions

Bulk


X

RC-Delay Model: InverterRC-Delay Model: Inverter

Cout

CP,gate

CN,gate

RP,DS

Rising Slope


X

RC-Delay Model: InverterRC-Delay Model: Inverter

Cout

CP,gate

CN,gate

RN,DS

Falling Slope


RC-Delay Model: Inverter cont’dRC-Delay Model: Inverter cont’d

CP,DB

Where does Cout come from? Input capacitance (= gate capacitances) of following gate Diffusion capacitances (Drain-Bulk) of PMOS- and NMOS

transistors

CN,DB Cout

CP,gate

CN,gate


RC-Delay Model: WidthRC-Delay Model: Width

Gate width W can be changed by Designer (L, Tox, VDD… are fixed)

Capacitance proportional to width: C ~ W Resistance inversely proportional to width: R ~1 / W Resistance of NMOS approx. two times smaller than

PMOS with same width:

WN RN

WP = WN RP = 2*RN

WP = 2*WN RP = RN CP = 2*CN!


RC-Delay Model: RC-Delay Model: FanoutFanout

f=2

W1/L1

W2/L2

W3/L3

W1=W2=W3

L1=L2=L3

: load

in

Cfanout f

C


RC-Delay Model: Rising SlopeRC-Delay Model: Rising Slope

, , ,

2

22 3

23 1

P DS N DB P DB load

N P inP

t RC R C C C

RC W C W f C

W

RnC nC nfC

nf R C

XCload

CP,gate

CN,gate

WN=n

CP,DB, ,

, ,

, ,

2,

,

,

N DS P DSN P

N DB N N gate N

P DB P P gate P

R RR R

W W

C C W C C W

C C W C C W

WP=2n

CN,DB


RC-Delay Model: Falling SlopeRC-Delay Model: Falling Slope

, , ,

2 3

3 1

N DS P DB N DB load

P N inN

t RC R C C C

RC W C W f C

W

RnC nC nfC

nf R C

XCload

CP,gate

CN,gate

WN=n

CP,DB, ,

, ,

, ,

2,

,

,

N DS P DSN P

N DB N N gate N

P DB P P gate P

R RR R

W W

C C W C C W

C C W C C W

WP=2n

CN,DB


RC-Delay Model: ExamplesRC-Delay Model: Examples

Delay of an Inverter with a fanout of 64:

3 1

3(1 64)

195

t f R C

R C

R C


RC-Delay Model: Examples cont’dRC-Delay Model: Examples cont’d Chain of Inverters with Cload = 192 C□ and Cin=3 C□

,3 2 1

,

, 3 , 2 , 1 , , 3 , 2

3 2 1 3 2

64

, , , , , ,

load chainchain INV INV INV

in chain

load INV load INV load INV load chain in INV in INV

in INV in INV in INV in INV in INV in chain

Cf f f f

C

C C C C C C

C C C C C C

1 2 3

1 2 33 (1 ) (1 ) (1 )chain INV INV INV

INV INV INV

t t t t

R C f f f

Cload=192 C□Cin=3 C□

INV1 INV2 INV3


RC-Delay Model: Examples cont’dRC-Delay Model: Examples cont’d Chain of Inverters with Cload = 192 C□ and Cin=3 C□

Cload=192 C□Cin=3 C□

INV1 INV2 INV3

1 2 3

4,4,4

4, 4, 4

45INV INV INV

chain

f f f

t R C

1 2 3

1,1,64

1, 1, 64

207INV INV INV

chain

f f f

t R C

Chain of Inverters: Optimum result (for speed) at equal fanout!


Chains of InvertersChains of Inverters


SizingSizing

Increasing Width Resistance get down Increasing current

Decreasing delay

BUT Capacitance increase too

Internal capacitances increase + Output load of previous gates increases


Sizing for PerformanceSizing for Performance

Sizing (W↑) auch interne Kapazität (Cdb,PMOS, Cdb,NMOS) = > größer

Effekt von Sizing sinkt!

Source: Irwan, PSU, 2001


Alpha Power Law ModelAlpha Power Law Model

risePMOS

fallNMOS

L DD

DD TH ,PMOS

L DD

DD TH ,NMOS

k' C Vt

(W / L ) (V V )

k' C Vt

(W / L ) (V V )

OutIn

WPMOS

WNMOS CL


Source: Harris ‘05

Logical Effort


Logical Effort (LE) cont’dLogical Effort (LE) cont’d

allGates

sum ii

LE LE

LEfLEC

Cgain

in

out **

fanout of the whole circuit: fsum = Cout / Cin,firstGate

gain of the whole circuit: gainsum = LEsum * fsum

LE of the whole circuit:

Cin,firstGate

Cout


Logical Effort (LE) cont‘dLogical Effort (LE) cont‘d

, 1,

gate in gateout gate

gate

gain CC

LE

for every gate (starting at the last gate):

sum sumgain gain


BACKUP


Moore‘s Law (3)Moore‘s Law (3)

from Rabaey ‘05


Holt 05


Off-Chip/On-Board Bus

Processor Cache

RF

3DGraphic

Bluetooth

Audio

Video

MemoryController

I/O

Memory

Off-Chip/On-Board Bus

Processor Cache

RF

3DGraphic

Bluetooth

Audio

Video

MemoryController

I/O

Memory

1958 Kilby: IC

1981 IBM: 5150 PC1948 Shockley: Transistor

SOC-AgePC-AgeMainframe-Age

~2000: On-chip integration

Performance / Integration

density

Display

Memory

Processor

Mainframe

Keyboard

Terminal

I/O

...

Further Terminals

Display

Memory

Processor

Mainframe

Keyboard

Terminal

I/O

...

Further Terminals

Memory

On-Chip Bus

Processor Cache

RF

3DGraphic

Bluetooth

Audio

Video

MemoryController

I/O

Memory

On-Chip Bus

Processor Cache

RF

3DGraphic

Bluetooth

Audio

Video

MemoryController

I/O

Pic changed, NoC is “our”

new approach, later


Metal LayersMetal Layers

Conductors (Aluminum / Copper)

OxideDielectric

TungstenTungstenPlugsPlugs

THE DEVICETHE DEVICE


0.0 1.0 2.0 3.0 4.0 5.0

VDS (V)

1

2

I D (

mA

)

0.0 1.0 2.0 3.0VGS (V)

0.010

0.020

÷

I D

VT

SubthresholdCurrent

Triode Saturation

VGS = 5V

VGS = 3V

VGS = 4V

VGS = 2V

VGS = 1V

(a) ID as a function of VDS

(b) IDas a function of VGS

(for VDS = 5V)

Sq

ua

re D

ep

end

en

ce

VDS = VGS-VT

(NMOS Enhancement Transistor: W = 100µm, L = 20 µm)

nMOS I-V SummarynMOS I-V Summary

from Rabaey '95


nMOS CutoffnMOS Cutoff

No channel Ids = 0

+-

Vgs = 0

n+ n+

+-

Vgd

p-type body

b

g

s d

from Harris


nMOS LinearnMOS Linear

Channel forms Current flows from

d(rain) to s(ource) => e- from s to d

Ids increases with Vds

Similar to linear resistor

from Harris

+-

Vgs > Vt

n+ n+

+-

Vgd = Vgs

+-

Vgs > Vt

n+ n+

+-

Vgs > Vgd > Vt

Vds = 0

0 < Vds < Vgs-Vt

p-type body

p-type body

b

g

s d

b

g

s d Ids


nMOS SaturationnMOS Saturation

Channel pinches off Ids independent of Vds

We say current saturates Similar to current source

+-

Vgs > Vt

n+ n+

+-

Vgd < Vt

Vds > Vgs-Vt

p-type body

b

g

s d Ids

from Harris


Inverter - Schaltverhalten Inverter - Schaltverhalten

Vout

Vin1 2 3 4 5

12

34

5

NMOS linPMOS off

NMOS satPMOS sat

NMOS offPMOS lin

NMOS satPMOS lin

NMOS linPMOS sat

OutIn

PMOS

NMOS CLoad


Delay (2)Delay (2)

from Rabaey ‘05


Inverter-Kette (2)Inverter-Kette (2)

nRCRCff

RCfRCfRCft

m

m

3)...(3

)1(3...)1(3)1(3

1

21

mfff *...**64 21

mff ...1

11 ... xxx ii mm

im

i

xm

x

m m

ii x

m

xm

*

xf 64

Gesucht ist minimales t, d.h. minimal

bei: gilt: denn:

d.h., wenn alle xi gleich sind, dann ist (in diesem Fall) die Summe am kleinsten.

d.h. alle fanouts müssen gleich sein, somit gilt:

(x = Anzahl der Inverter)

m

mi

mi

xm

x

Micro transductors ’08 CMOS Basics Dr.-Ing. Frank Sill Department of Electrical Engineering,...

Documents

Transcript of Micro transductors ’08 CMOS Basics Dr.-Ing. Frank Sill Department of Electrical Engineering,...