Micro Power Meter for Energy Monitoringof Wireless Sensor Networks at Scale

Xiaofan Jiang, Prabal Dutta, David Culler, and Ion StoicaDept. of Computer Science, University of California, Berkeley

Berkeley, California 94720fxjiang,prabal,culler,istoica@cs.berkeley.edu

ABSTRACTWe present SPOT, a scalable power observation tool that en-ables in situ measurement of nodal power and energy over adynamic range exceeding four decades or a temporal resolu-tion of microseconds. Using SPOT, every node in a sensornetwork can now be instrumented, providing unparalleledvisibility into the dynamic power profile of applications andsystem software. Power metering at every node enables pre-viously impossible empirical evaluation of low power designsat scale. The SPOT architecture and design meet challengesunique to wireless sensor networks and other low power sys-tems, such as orders of magnitude difference in current drawsbetween sleep and active states, short-duration power spikesduring periods of brief activity, and the need for minimumperturbation of the system under observation.

Categories and Subject Descriptors: B.8.2 [Performanceand Reliability]: Performance Analysis and Design Aids

General Terms: Measurement, Performance, Design.

Keywords: Power, energy, meter, monitoring, scalable, dy-namic range, embedded, wireless sensor networks

1. INTRODUCTIONEnergy-efficiency has pervaded nearly every aspect of wire-

less sensor network (“sensornet”) research, from platformdesigns [11, 3, 6], to MAC layers [17, 10], to routing proto-cols [12, 13, 16], to applications [18, 5], and across a rangeof duty cycles [2, 15, 7]. What is missing is a method to em-pirically evaluate the energy-efficiency claims of this growingcorpus of literature. On one hand, simple approximationsof nodal energy usage derived from estimates of node dutycycle and communication rates [4] do not capture the low-level system power profile. On the other hand, simulatorsthat extrapolate system macrobenchmarks – the large-scale,long-term, and system-wide behavior of a sensor network –from models based on microbenchmarks of a single nodecannot assure the accuracy of their generalizations [14].

Motivated by roboticist Rodney Brooks’ famous observa-

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Figure 1: A typical nodal current profile consistsof long periods of low-current sleep punctuated byshort, periodic bursts of high-current activity.

tion that “the real world is its own best model,” we suggestthat what is now needed are empirical measurements of insitu energy usage at scale to calibrate existing models, char-acterize their variance, and validate their generality. How-ever, characteristics unique to sensornets make their powerand energy monitoring challenging. Figure 1 shows the cur-rent profile of a typical sensornet application. Long periodsof low-current sleep are punctuated by short, periodic burstsof high-current activity.

Since more than three orders of magnitude separate thecurrent draw in the sleep and active states, it might seemreasonable to ignore the energy usage in the sleep state.However, because sensornets operate at very low duty cyclesranging between 0.1% to 1%, both the sleep and active states

Figure 2: The scalable power observation tool(SPOT) consists of a sense resistor, amplifier,voltage-to-frequency converter, and two counters.

account for non-trivial fractions of the system power budget.This suggests that a metering system must have a dynamicrange that significantly exceeds three orders of magnitude tocapture sleep current with sufficient resolution.

Figure 1 shows that a node may be active for a short time,on the order of 20 ms, before returning to the sleep state.However, the node’s current draw is not constant during this20 ms period. Rather, the current profile includes two largetransients lasting tens of microseconds, four different levels,and oscillations during some level transitions. Such featuresin nodal current profiles are common and reflect the widevariety of system components and the sum of their variouspower states and state transitions. This suggests that sam-pling rates approaching tens of kHz or even MHz may beneeded to faithfully capture these ephemeral features.

To prevent excessive perturbation of the system undertest, the metering system should be minimally invasive: itshould require low computational and storage resources fromthe host node, and it should be able to operate in a stand-alone manner with limited host interaction. Finally, in situmetering at scale requires small size and low cost.

Our solution to this metering problem is shown in Fig-ure 2. This system, a scalable power observation tool (SPOT),enables in situ measurement of nodal power and energywith a dynamic range exceeding 10000:1 and a temporalresolution in the order of microseconds. SPOT accumu-lates current internally and exports digital I/O lines to en-able/disable metering and calibration, analog lines to mea-sure instantaneous current, and an I2C interface to read theaccumulated current (energy) and reset the counter. The re-mainder of this paper presents more detailed design require-ments and technical challenges, followed by SPOT’s designanalysis and evaluation. We conclude with a discussion ofthe research enabled by this work and our future plans.

2. PROBLEM FORMULATIONThis section presents the four basic requirements of our

micropower meter for sensornet nodes (“motes”): dynamicrange, sampling rate, perturbation, and ease-of-integration.

Figure 3: The power spectral density of a node cur-rent profile shown in Figure 1.

2.1 Dynamic RangeA sensornet node can exhibit a bewildering array of power

profiles, depending on its application profile. For example, asimple sense-and-send application with a 0.5 Hz duty cyclemight exhibit the profile shown in Figure 1. In contrast,a sense-and-store application may sample sensors in a fewmilliseconds every five minutes, buffer these sensor readingsin RAM, write them to flash once a day, and attempt toupload the samples once a week. The current profile for suchan application would be starkly different from that shown inFigure 1. Since SPOT is to be used in a testbed, we cannotassume a particular application profile a priori, implyingthe system needs to have a wide dynamic range spanningthe entire spectrum of possible current draws.

2.2 Sampling RateWireless sensor nodes are pulsing applications. Their pulse

width, or the active cycle time, needs to be considered whendetermining the appropriate sampling rate. If the durationof an active pulse is shorter than the sampling rate of theenergy meter, the energy in that pulse may be missed. Inaddition, the spectral content within a active pulse shouldalso be sampled at a rate that satisfies the Nyquist rate.

While we can estimate the minimum active cycle time byobservation, we cannot guarantee that the spectral contentwill be band-limited to a particular range. In our exam-ple, the width of an active cycle is approximately 20ms.However, it’s power spectral density (PSD) exhibits energyacross the entire spectrum, and therefore it is necessaryto bandlimit the signal with a low pass filter (LPF). Thecutoff frequency for the LPF should be the highest fre-quency in the PSD that still contains significant energy.The cutoff frequency in our example is around 20kHz, asshown in Figure 3. This implies a minimum sampling rateof 20kHz × 2 = 40kHz per Nyquist’s theorem.

Intuitively, we can see that to capture most of the energycontent in the 20ms active cycle in Figure 1, especially theoscillations at 6ms and 21ms, we will need to sample at leastevery 0.1ms, which implies a sampling frequency of 10kHz.

2.3 PerturbationEnergy monitoring should not affect the actual energy

consumption of the mote under study (hereby referred toas the device under test, or DUT). When the user of theenergy monitor is separate from the DUT, accessing datafrom the energy monitor should not affect the energy con-sumption; when the user of the energy monitor is part ofthe DUT itself, then accessing the energy monitor shouldpresent a minimal perturbation to the DUT.

The energy monitoring device should not affect the mea-sured power of the DUT. This implies that the the energymonitor should be powered from a separate power source;however, if it must share the same power supply as the DUT,the point of measurement should be confined to the DUT.

The energy monitor should not require the DUT to per-form extensive computation, if any. This implies that forthe case when the user and the DUT are the same mote,a meter that can only provide power measurements is outof the question because to obtain an energy measurement,the DUT will need to constantly read from the meter to ac-cumulate energy measurement. Instead, this computationshould be offloaded to the energy monitor to minimize theenergy and CPU usage of the DUT.

2.4 Ease-of-IntegrationOne of the goals for this project is for every mote on a

network to be equipped with an energy meter. This sug-gests that the system needs to be easy to integrate, bothelectrically and mechanically, into a sensornet node. To bepractical, the meter must be inexpensive, or perhaps com-parable in cost to the sensornet nodes.

3. RELATED WORKMany commercially available energy meters operate by

measuring the voltage drop around a shunt resistor R tied tothe power supply of the circuit under observation, as shownin Figure 4. The voltage drop is proportional to the currentand can be multiplied by a voltage from a separate chan-nel to obtain the true power usage. The voltage across theresistor is usually first magnified by an amplifier, and thenundergoes an analog-to-digital conversion (ADC). The restof the computations, such as dividing by the resistance andmultiplying by the voltage, are usually done in the digitaldomain. This power computation occurs many times in asecond (from a few Hz to MHz) and is summed in an inte-grator to obtain energy. The results are stored in registersand presented at the output either as PWMs (pulse widthproportional to energy) or in digital form.

Oscilloscopes are often used to capture the power profileof a system at bench scales since their high sampling rates,often in the GHz range, can provide very fine temporal res-olution. However, their high cost makes them unsuitable forlarge scale usage. But, even if cost were not an issues, oscil-loscopes would not be suitable. First, most oscilloscopes arelimited to milliamp-level vertical sensitivities, rather thanthe needed microamp levels. Although a pre-amplifier canbe used, this adds cost and complexity. Second, the are noteasy to integrate with typical sensornet nodes.

Sensornet-specific solutions have been proposed as well.For example, the DS2438 [8] is a battery monitor IC used inthe HelioMote [6]. This is an 8-pin IC with a simple 1-Wireinterface and integrated temperature sensing. However, the

Figure 4: Architecture of a typical energy meteringcircuit.

on-board ADC is only 10-bits, providing a theoretical max-imum dynamic range of 1000:1, which is far below require-ments for motes (10000:1). It samples at a frequency of36.41Hz, also far below the 20kHz needed to capture inter-esting spikes.

Commercially available integrated circuits are not designedto meet our dynamic range and sampling requirements si-multaneously. For example, battery monitoring ICs such asthe Maxim Semiconductor’s BQ2019 are targeted towardslong term measurement of batteries and provides low tempo-ral resolution. Multi-function metering ICs such as the Ana-log Devices’ ADE7753 [1] have maximum dynamic ranges ofaround 1000:1, failing our vertical resolution requirement.Microchip’s MCP3906 [9], an energy measurement IC sup-porting the IEC 62053 international energy metering speci-fication, offers a dynamic range of only 1000:1 and has offsetcurrents that exceed node sleep currents by an order of mag-nitude, making it unsuitable for our purposes.

A very different approach, proposed by Shnayder et al.,is to simulate power draw using an empirically-generatedmodel of hardware behavior [14]. The simulator, called Pow-erTOSSIM, characterized its underlying model by instru-menting and profiling a single node. While PowerTOSSIMtakes an important step toward providing better visibilityinto nodal power profiles, since its model is based on mi-crobenchmarks of a single node taken in particular envi-ronment, it also raises several questions about the model’sgenerality: How representative is the node that was instru-mented to calibrate PowerTOSSIM’s model? How does in-teraction with the physical environment shape energy usage?How do temperature variations affect leakage currents? Howmuch variance occurs within a single node, and across differ-ent nodes, for the same operation? These questions can onlybe answered by instrumenting an entire network of nodes insitu and at scale.

4. SPOT ARCHITECTUREIn this section, we present the SPOT architecture and

highlight some of its key features. A more detailed analysisis presented in Section 5. Our architecture consists of fourstages: sensing, signal conditioning, digitization, and energyoutput, as shown in Figure 5. This configuration shows theDUT and the user of the energy meter to be the same mote,which need not be the case. In the sensing stage, a shuntresistor is put in series with the mote (DUT), converting cur-rent to voltage. This voltage is proportional to the power

Figure 5: Architecture and Primary Components

consumption of the mote. In the conditioning stage, a differ-ential amplifier and a low pass filter is used to amplify andband-limit the signal, respectively. In the digitization stage,a voltage-to-frequency converter (VFC) is used to convertvoltage into a periodic wave with a frequency proportionalto the input voltage, which is also proportional to the power.In the energy output stage, pulses from the output of theVFC are summed (i.e. integrated) in a counter to obtain en-ergy measurements while a separate counter is used to keepa time-base; finally, the values of the counters are read backby the mote via I2C.

4.1 Differential AmplifierWhile differential amplifier is simple in principle, it is more

of an art to correctly use one in practice. Because we config-ured our shunt resistor at the high-side of the mote (see Sec-tion 5.1), the common-mode voltage is equal to Vcc (3.3V).This signifies that not only does our amplifier needs to havea high common-mode input range, we need to introduce asecond voltage supply (e.g. 5.5V) to correctly biased theamplifier.

Due to variations in device sizing, amplifiers have offsetvoltages (i.e. output is non-zero even if input is zero) andit’s different for every amplifier. This presents us with acalibration problem. To compensate, we included a calibra-tion switch which zeros the input at startup and records thecounter value (corresponding to the offset). This value isstored in the MCU and used in the calibration curve.

Because we are trying to amplify a very small signal, anynoise is significant. We placed multiple RC filters (for differ-ent frequencies) around sensitive areas (e.g. voltage suppliesof IC chips). Furthermore, we observed that the oscillatorfor the digital portion of our circuit introduces significantnoise to the amplifier. To solve this problem, we carefullyplaced separate ground rings in the board to separate theanalog portion of the circuits from the digital portion (seeFigure 2).

4.2 Voltage-to-Frequency ConverterTo achieve the desired dynamic range, we choose a novel

approach of using a voltage-to-frequency converter as theanalog front end (AFE). It converts the signal from the ana-log to the digital domain. While VFC has a clocked input,the voltage to frequency conversion is entirely analog in the

sense that any arbitrarily small voltage is integrated insidean analog integrator and will eventually trigger an outputpulse. This essentially gives the VFC infinite resolution,limited only by noise. In contrast, traditional ADCs willfail to capture voltage levels smaller than the specified bitresolution. Please refer to Section 5.3 for details.

4.3 Energy Counter and Internal TimebaseTo minimize MCU overhead, we use an internal 32-bit

counter to accumulate the power readings to provide directenergy measurement. The counter is free-running at a max-imum rate of 0.9MHz or 0.9 million counts per second. It

overflows in roughly 232

220 = 212 seconds or about once anhour. This implies that the MCU will only need to readonce every hour if long term energy is all the applicationneeds. But it can read as fast as I2C bus speed allows toobtain a fine-grain power profile by differentiating the en-ergy readings.

To find the energy consumption for a given time window,we can read the energy counter at the beginning and againat the end. For this to work, we need some way of keepingthe elapsed time. This can be done in the MCU by usingthe MCU’s timer. However, this introduces MCU overheadand the time will not be accurate because many cycles willhave elapsed from timer fired() to an actual read from theenergy counter. Instead, we included another counter dedi-cated to be the time-base. This counter is triggered by thesame oscillator (1MHz) that provides the base frequency tothe VFC. We wired the I2C bus address such that one com-mand can atomically capture the two counter readings at theexact same time. This method has the additional benefit ofnullifying any jitter in the oscillator due to temperature.

4.4 Power IntrospectionBecause SPOT provides power and energy measurements

without significant MCU perturbation, it is perfectly rea-sonable for a mote to use SPOT to monitor its own powerand energy consumption, allowing the application to per-form power adaptation.

5. DESIGN ISSUES AND TRADEOFFSIn this section, we revisit the SPOT architecture with an

eye toward design issues and tradeoffs in the sensing, signalconditioning, digitization, and accumulation.

5.1 SensingAs with most sensing systems, the first stage is the sensor

itself. In the case of energy monitoring, the physical quan-tity we are trying to measure is power, which is a productof voltage and current. For the purposes of this paper, weassume that the voltage is fixed and known a priori, or canbe measured separately. Of course, current can be measuredin several ways. We chose to use a shunt resistor, which isone common method. A small resistor is placed in serieswith the power supply and the voltage across this resistor,which is proportional to the current, is measured.

There are several design considerations with this approach.The resistor can be placed between the mote and either thepositive power supply or the negative power supply (ground).The former is called “high-side current sensing” while thelatter is called “low-side current sensing”. Low-side sens-ing is desirable because the differential voltage across theresistor is equal to the voltage measured, with respect to

ground, at the connection between the resistor and the mote.This simplifies the amplification stage because there is nocommon-mode voltage. However, low-side sensing also cre-ates a problem known as ground bounce – as the currentdraw fluctuates, the negative supply of the system also fluc-tuates. This is undesirable because many electronic compo-nents are sensitive to ground fluctuations. This is also whythe resistance must be kept small since the magnitude ofthis fluctuation is proportional to the resistance.

High-side current sensing places the resistor between thepositive supply rail and mote’s power input. By placingthe resistor on the positive supply side, the voltage fluctua-tions are shifted from the negative supply side to the posi-tive side. This is more desirable because most componentsare more resilient to fluctuations in the positive supply rail.However, this introduces common-mode voltage because thevoltage on both sides of the resistor, measured with respectto ground, is non-zero. The presence of significant common-mode voltage can cause problems for amplifiers, as we dis-cuss in Section 5.2.

We place a 1Ω resistor R between the positive supply rail(Vcc) and the mote’s positive supply in a high-side config-uration, as shown in Figure 5. The value of 1Ω was chosento limit the supply voltage fluctuation. Assuming a maxi-mum current of 40mA, typical of current mote technology,the maximum drop is 40mV, which is reasonable.

5.2 Signal Amplification and ConditioningThe current draw of a typical mote, such as Telos [11],

ranges from 2µA to 40mA.1 Using a 1Ω resistor, the mini-mum voltage needed to capture is 2µA×1Ω = 2µV , which istoo small for signal processing. Therefore, we first amplifythis signal using differential amplifier, as shown in Figure 5.

The gain of the differential amplifier is set such that themaximum input voltage of 40mV, multiplied by the amplifiergain, is equal to the maximum input of the next stage andless than the maximum output of the amplifier. In this case,the input of the next stage is limited by the supply voltage,which is commonly 3.3V or 5V. Therefore, a reasonable gainis 3.3V

40mA= 82.5. The remainder of this section explores some

of the design and implementation challenges of this stage.

5.2.1 Dynamic RangeThe required dynamic range is one of the key challenges

in our system. We cannot artificially increase the amplifiergain because it is limited by the maximum input range ofthe next stage. With a gain of 82.5, a 2µV input translatesto 0.165mV output, which is still quite small. At this point,we can either defer this problem to the next stage or try toalleviate it through some sort of signal processing.

One way to “decrease” the dynamic range requirement isto use a low pass filter (LPF) to lower the amplitude andwiden the pulses. However, because LPFs are not energypreserving, they require software compensation and presenttiming difficulties during measurements. We chose to pre-serve the signal integrity and let the next stage deal withthe dynamic range requirement.

5.2.2 Common Mode VoltageAmplifiers are composed of MOSFET transistors. To op-

erate correctly, transistors need to be biased into the satu-

12µA can be obtained by lowering the supply voltage belowrecommended values.

ration region. The voltage level of the input signal, which ispropagated through the gates of MOSFETs, needs to have asufficient potential difference with respect to the drain andthe source. The drains and sources are tied to the voltagesource and ground respectively. This implies that the DCcomponent – the common-mode voltage – of the input sig-nal needs to be lower than the supply voltage by a smallmargin but higher than ground by a small margin as well.Because we chose high-side current sensing configuration,our common-mode voltage is the same as Vcc. Hence, weintroduced a second power supply that delivers 5.5V to biasthe amplifier.

5.2.3 Reference VoltageThe reference voltage of a differential amplifier is the base-

line voltage to which input and output voltages are refer-enced. The reference voltage also plays a role in biasingthe amplifier and must be chosen carefully. For example,for the amplifier we are using, if the common-mode voltageis around 4V and the supply is 5.5V, the reference inputneeds to be greater than 3V, as required by the specifica-tions. The exact requirement on the reference voltage variesacross different chips. It is desirable to experimentally de-termine the limits. Reference voltage also allows us to adjustor even cancel out the internal offset so that the output isalways positive. The internal offset due to sizing differencesand manufacturing variations may be positive or negative.Because the next stage may not cope well with negativevoltages, it is desirable to offset this value so that the totaloffset is always positive. This does not eliminate the need forcalibration because the total offset still varies across chips.

Additionally, a reference voltage can give us the flexibilityto measure power in both directions (i.e. consumption andrecharging). For example, if we set the reference voltage toV cc2

(see Figure 7), we can record the nominal (zero powerin either direction) voltage by setting the input to zero andcapturing the counter values (or rather how fast the counterincrements). A reverse flow in current (e.g. recharging) willsimply cause the counter to count slower than this nominalrate. This will cut the resolution in half but provide a signedrather than unsigned value for metering.

5.2.4 Input and Output OffsetDifferential amplifiers consists of pairs of CMOS gates.

Due to process variations, the sizing of these gates are usu-ally not perfectly matched. As a result, there will be non-zero output even when the input is zero, called offset. Thereare two types of offset, input offset and output offset. In-put offset is multiplied by the gain while output offset isdirectly added on the amplified signal. Because our appli-cation is concerned with very small voltages, even a smallvariation in offset will skew our results. Therefore we needto calibrate the amplifier in order to eliminate the offsets.

There are typically two ways to calibrate offsets. Onemethod involves purely using analog circuits, but this methodis expensive both in terms of cost and power. The alterna-tive, and the method we choose, is to do it digitally. Asseen in Figure 6, we added a digitally controlled switch tothe resistor’s load. The switch is nominally at A, allowingnormal measurement. During calibration, the mote togglesthe switch line to B, which results in a zero voltage dropacross the resistor. The mote then takes a reading at thisconfiguration before returning the switch to A.

Figure 6: SPDT Switch for Calibration. In oneconfiguration, current flow bypasses the shunt re-sistor, allowing the input offset to be measured. Inthe other configuration, current passes through theshunt resistor, allowing the mote current to be mea-sured.

Figure 7: A simplified representation of the analogportion of schematic.

5.2.5 Effect of NoiseAs discussed in Section 4.1, the differential amplifier is

quite sensitive to noise. Figure 8 shows the effect of the os-cillator on the amplifier before any filtering. To reduce noise,we have placed multiple filters around chip power supplies asseen in Figure 7, and separated analog circuits from digitalcircuits using slotted ground guard rings as seen in Figure 2.We also employ separate analog and digital ground planeswhich meet directly under the VFC. The guard ring slotscan be used to attach separate metal shields to the analogand digital portions of the circuit, although we have not yetneeded to do so.

5.2.6 Lowpass FilteringAs previously discussed in Section 2.2, energy content is

present across the entire spectrum. To avoid false readingsdue to high frequency components in our signal, we cutoffthe frequency content at the point where the energy contentdrops significantly such that it will not adversely affect ourenergy readings. In our system, this point occurs at 20kHz

Figure 8: Noised introduced by the VFC oscilla-tor requires analog lowpass filtering, ground guardrings, separate analog and digital ground planes, anddecoupling capacitors to contain.

as seen in Figure 3. We place a single LPF between thedifferential amplifier and the VFC to achieve this purpose,as shown in Figure 7.

5.3 DigitizationDigitization is the stage that converts the analog signal to

the digital domain, allowing digital signal processing (DSP)to be applied and eventually interfaced with a digital system(MCU). This is one of the central stages in most meteringsystems and is where some of the original signal informationis lost due to the finite resolution of digital systems.

Analog-to-digital converters (ADC) are the most com-monly used digitization device. ADC takes an input voltageand outputs a digital signal with a specified bit resolution.For example, a 12-bits ADC means that for an input rangeof 0-40mV, the minimum voltage level that can be capturedis 40mV

212 = 9.8µV . Furthermore, 12-bits means there are 212

discrete steps over the input range and any value betweenthe steps will need to be rounded.

Our dynamic range requires at least 14-bits of resolution(Section 2.1). We considered several different designs:

• Internal ADC of the MCU is inadequate because theyare usually only 12-bits. Furthermore, it incurs signif-icant MCU overhead.

• 16-bit ADCs are slightly more expensive but not un-common. However, one of our goals is to internallyintegrate power to obtain energy. If our power mea-surement (output of the ADC) is already in a puredigital format (e.g. parallel bus, I2C, SPI), we willneed a compatible device to integrate the digital signal.This implies either a DSP or MCU. A separate DSPor MCU chip adds unnecessary complexity and cost.On the other hand, using the same mote as the inte-grating MCU would incur significant CPU and poweroverhead.

• IC chips that integrates 16-bit ADC with counters areessentially energy monitoring ICs. However, as dis-cussed in Section 3, we have not found a single ICthat satisfies all of our requirements.

• Voltage-to-frequency converter (VFC) is a low costanalog digitization device in the sense that the out-put is a simple digital-compatible pulse train insteadof a full fledged digital bus as in the case of ADC. Wefurther investigate VFC below.

Figure 9: The architecture of a VFC.

Figure 10: The VFC transfer function shows outputfrequency is proportional to input voltage.

A VFC operates by integrating the input voltage and feed-ing the output of the integrator to a comparator as seen inFigure 9. As soon as the charge accumulated in the inte-grator exceeds the reference voltage (Vref), the comparatoroutputs a pulse, which also acts as negative feedback to“balance” the charge inside the integrator. The net effectis a pulse train whose frequency is proportional to the in-put voltage. It is different from ADC because any arbitrarilysmall voltage can be captured via the analog integrator. Thetransfer function for the VFC we chose is:

fOUT = 0.1fCLKIN + 0.8(VIN/VREF )fCLKIN (1)

where fCLKIN is the 1MHz clock input and Vref is 3.3V. Amore graphical representation is shown in Figure 10.

While the resolution of VFC is infinite in theory sinceit’s analog, the actual fidelity of the signal is limited bythe internal noise. The VFC we are using has a maximumpeak-to-peak noise of 100µV . Assuming the gain of ouramplifier is around 80 and our lowest input voltage is 2µV ,the smallest input to the VFC is then 80 × 2µV = 160µV ,which is barely above the noise. While this places stringentnoise filtering requirement on our design, the actual signal-to-noise ratio (SNR) is not bad since the specified 100µVis the maximum peak-to-peak noise (as opposed to RMSnoise).

Our choice of using VFC is also due its easily-integratableoutput. As mentioned before, we need to sum the outputof the VFC to obtain energy and we want minimal pertur-bation of the DUT. ADC usually require a DSP or MCUat the output to “interpret” the digital output. If the samemote is used to read ADC’s output, it will incur significantoverhead because power readings need to be read at a fairlyhigh frequency. To reduce complexity, perturbation, and

cost, we favor VFC’s elegant pulse train output, which canbe easily accumulated using simple counters (see Section 5.4for details).

5.4 Energy OutputThe last stage is energy accumulation and digital output.

To provide the user with a direct energy value, we will needto integrate the power readings from the previous stage:

E(t) =

Z t

t0

P (τ)dτ

If the previous stage uses an ADC, we will need a DSPor MCU, which either incurs significant complexity/cost orperturbation, as explained in the previous section.

Fortunately, we can use simple counters to sum the pulsetrain output from the previous stage. Every rising or fallingedge of a pulse in the pulse train increments the counterby one. Higher power consumption leads to more frequentpulses, which in turn leads to faster counter increments.The difference in counter values between t0 and t1 repre-sents the energy consumption during time t1 − t0. How-ever, counters have a finite range, represented by its bits.To prevent counters from overflowing, the MCU needs toread and reset the counters periodically. This presents over-head, but it can be minimized by using a large counter thatoverflows infrequently. We choose to use a 32-bit counter.From equation 1, we find that the VFC has a maximumoutput frequency of 0.9MHz (assuming VFC is maximumwhen VIN = VREF and fCLKIN = 1MHz). This impliesthat the counter will overflow roughly once every hour (seeSection 4.3), which is infrequent.

Finally, for the user of SPOT (e.g. the mote) to read thecounter values, we need a compatible digital output format.Parallel output is not possible because 32 bits require toomany pins. Serial output such as I2C or SPI is desired.Since our data rate is low, I2C is more than sufficient.

Additionally, to relieve the MCU of time-keeping respon-sibilities and to precisely measure elapsed time, we includedanother 32-bit counter dedicated to time-keeping and is trig-gered by the same oscillator that drives the VFC. Pleaserefer to Section 4.3 for preliminary descriptions. For thisscheme to work, we need some way of reading the two counterchips at the exact same time. Fortunately, one valid com-mand to the counters that we use is “capture”, which es-sentially takes a snapshot of the counter values and storesthem in registers. Furthermore, because the addresses forthe counter chips can be dynamically changed, we can wirethe I2C addresses for the two chips to be the same duringa “capture” command, then re-wire the addresses to be dif-ferent and read back the captured values individually.

5.5 SPOT Application Programming InterfaceWe provide a high-level application programming inter-

face to SPOT to make using it simple for TinyOS developers.Our API is shown in Figure 11.

6. EVALUATIONIn this section, we evaluate SPOT’s accuracy as a tool

for metering energy and power for a typical sensornet work-load. In particular, we evaluate SPOT’s dynamic range, res-olution, and stability, which represent the most challengingrequirements for an embedded power meter.

// Initialize the counters and calibrate the system.result_t init();

// Signals end of initialization phase.event void initDone();

// Read both energy and time counters at the same time.// 1. Configure addresses to be the same// 2. Issue I2C command to capture counter values// 3. Configure addresses to be different// 4. Read from time counter// 5. Read from energy counter// 6. Signal readDonecommand result_t readCounter();

// Signals the completion of reading the counters// Returns the two 32-bit counter values.event void readDone(uint32_t time, uint32_t energy);

// Enable or disable the counters from counting.command result_t setEnable(bool enable);

// Performs calibration.command result_t cal();

// Signals end of calibration.event void calDone();

Figure 11: The SPOT application programming in-terface includes commands to initialize, calibrate,enable, read, and reset the meter.

6.1 Dynamic Range and ResolutionA principal requirement of our system is a dynamic range

exceeding 10000:1 with current resolution of at least 2µA.To evaluate SPOT’s resolution, we loaded a 3.3V powersource with resistors of different value in the MΩ range tocreate currents of 1.08, 2.07, and 3.48µA. In addition, weloaded the power source with a TelosB mote in sleep mode,which draws 9.09µA, to provide an additional data point.

Table 1: Snapshots of SPOT’s uncalibrated, free-running Time and Energy counters taken approxi-mately every 40 ms (first two columns).

Time Count Energy Count Counts/Sec397369588 2535884271 161804.7903397424011 2535893077 161806.5891397453917 2535897916 161806.9953397489646 2535903697 161801.3378

For each data point, we take 600 consecutive readings fromSPOT. An example of the uncalibrated readings that SPOToutput is shown in Table 1 in the first two columns. The firstcolumn lists counter values from the Time Counter and thesecond column lists counter values from the Energy Counter.The elapsed time between readings is the sum of the I2Caccess time (I2C is running at 100kHz) and the radio packettransmit time (one packet is transmitted for each reading).

For simplicity, we will refer to values in the table using theinitials of the column heading plus the row number in sub-script (starting at 1). For example, the second Energy Countis designated as EC2. The uncalibrated data shown in Ta-ble 1 can be used in several ways. For example, we can deter-mine the energy the mote consumed between the 1st readingand the 4th reading simply by computing EC4 − EC1; thisenergy corresponds to an elapsed time of (TC4−TC1)/106 =0.12 seconds, since the Time Counter increments at 1MHz.Since power is the derivative of energy, we can estimate the

average power over an interval by simply taking the dif-ference of the energy counts. The third column shows thepower in units of counts/second. For example, C/S2 is ob-tained by computing (EC2−EC1)/(TC2−TC1)×106. Thisvalue is linearly proportional to power and current, sincevoltage is constant.

Figure 12: SPOT current resolution. SPOT can re-solve currents at the microamp level.

Power values (counts/sec) for each current are plotted inFigure 12 in boxplots to show their distributions. The powerfor 0µA current is not zero due to the amplifier non-zerooffset voltage and the VFC minimum frequency of 0.1MHz.

Notice that while values between µA boundaries do over-lap, the variance is limited and the medians values sit atregular intervals from each other. This suggests that SPOTis able to resolve 2µA or smaller currents, but that it isnecessary to take multiple samples. In practice, the counterreading rate is not likely to be low, which effectively averagesthe readings over much longer runs.

A simple linear regression of the five medians shown inFigure 12 generates a useful calibration curve for SPOT.Despite being far from optimal, since this curve is generatedusing data for points between 0 and 9.09µA rather than thefull range extending to 45mA, we show that this curve isstill useful in the next section.

Because our Vcc is 3.3V and our amplifier has a gain ofaround 66, we can tolerate a maximum input current of45mA, assuming the amplifier offset does not exceed 0.3V.At the other extreme, Figure 12 shows that we can resolvecurrents at 1µA or even less. This means that SPOT has adynamic range exceeding 45mA

1µA= 45000 : 1, which surpasses

our dynamic range requirement.

6.2 Long-Term Tracking AccuracyBecause motes spend the majority of their time sleeping,

it is important to evaluate SPOT’s accuracy in monitoringa mote’s energy consumption during its sleep state. Thisis more difficult than monitoring a mote in active state be-cause the current to be monitored is four orders of magni-tude smaller.

The counter readings obtained from SPOT were calibratedusing the equation found in Section 6.1 and compared with areference curve obtained using an professional-grade current

Figure 13: Energy metering of 9.09µA load over a pe-riod of time exceeding 7 minutes. The accumulatederror is 0.1mJ or 3% of the actual energy usage.

meter, as shown in Figure 13. The mote under observation,a TelosB [11], is drawing approximately 9µA of current.2

As seen in Figure 13, SPOT is able to closely track energyusage, but with a small drift. After 6 minutes, the erroris less than 0.1mJ or 3%. The absolute error accumulatesover time but the relative error should stay constant, whichmay be acceptable for most applications. If more accuratecalibration is required, additional calibration points will beneeded.

6.3 Energy and Power TrackingMost sensornet applications are duty-cycled, waking up

occasionally to take a sensor sample or send a message, andsleeping the remainder of the time. To evaluate SPOT’stracking accuracy in monitoring motes with relatively lowduty-cycles, we now consider a typical workload. The moteunder observation is a TelosB mote running at slightly higherthan 2Hz duty-cycle. The reference curve is generated byintegrating the measured power signals collected using ahigh-end digital storage oscilloscope. Because the oscillo-scope does not have enough dynamic range to resolve activestate power and sleep power at the same time, we will focuson only the active state power in this experiment, since theprevious section demonstrated SPOT’s ability to track sleepstate power.

The top graph in Figure 14 shows the energy monitoredby SPOT and the oscilloscope. The flat portions of the curverepresent energy consumed by the mote during sleep whilethe sharp rises between flat steps represent energy consumedduring active cycles. The change in energy during active cy-cles is approximately 0.4mJ while there is no observable en-ergy change during sleep states. An interesting observationis that energy consumed during different active cycles areall slightly different. This is likely due to random backoff inthe medium access control layer, which causes the variationsin active cycle time. This also explains why SPOT does notmatch the oscilloscope more closely, since the SPOT andoscilloscope measurements are taken at different times.

29µA represents a typical sleep state current for TelosB pow-ered at 3.3V voltage supply.

Figure 14: Energy and power tracking of duty-cycling TelosB mote using SPOT compared witha digital storage oscilloscope. The flat portions ofthe top graph represent energy consumed by themote during sleep while the sharp rises betweenflat steps represent energy consumed during activecycles. The bottom graph shows the power drawrecorded by SPOT by differencing successive energyusage readings.

The bottom graph of Figure 14 shows the power drawrecorded by SPOT.3 Note that the observed resolution isquite low. This is because we wait for the radio on ev-ery sample. However, because SPOT samples the signal at1MHz internally, even-though we are not reading the coun-ters as fast, the energy measured is still quite accurate.

7. ENABLED RESEARCHAlthough the SPOT system itself represents a unique,

mixed-signal, hardware-software design, its true impact willbe measured by the novel research it enables. It this section,we outline our near-term plans for this system and speculateon how SPOT may affect future sensornet research.

SPOT, as described in this paper, is a single-sided, lead-less chip carrier (LCC) that can be treated as a modularcircuit component and directly soldered to a printed circuitboard. To be useful, the module must intercept the powerline between the power supply and the node under test. Wehave built a Mica2/MicaZ carrier board that incorporates

3The terms “power” and “current” are used interchange-ably because the voltage is constant and therefore power isdirectly proportional to current.

the SPOT module, all needed power supplies, a real-timeclock, extra counters, and power line intercept, as shown inFigure 15. A Telos [11] version of the carrier board is underdevelopment. We plan to instrument an entire testbed withthese modules.

Figure 15: The SPOT module attached to its MicaZcarrier board.

Recall that state-of-the-art simulators like PowerTOSSIMbase their models on microbenchmarks of a single node takenin a particular environment. An instrumented testbed willallow us to answer a number of questions about the gener-ality of these models: How representative is the node thatwas instrumented to calibrate PowerTOSSIM’s model? Howdoes interaction with the physical environment shape en-ergy usage? How do temperature variations affect leakagecurrents?

Beyond the simple verification of mote power models, webelieve the high impact research enabled by SPOT will bemacrobenchmarking the energy-efficiency claims existing net-work protocols as well as implementations of similar or iden-tical protocols from different TinyOS distributions.

We envision two variations on SPOT that would pro-vide still greater visibility into nodal power profiles. First,it would be simple to allow the node under test to ad-just its supply voltage, within bounds, and multiply, in theanalog domain, the voltage and current to create a truepower/energy meter. This would allow profiling nodal powerdraw across a range of voltages, as is common when runningon batteries. Second, the instantaneous power output ofthe preceding system could be digitized using a high-speedADC, collected in a deep FIFO, and read out more slowlyby the node under test. This would allow captures of veryfine-grained node power profiles.

8. CONCLUSIONWe presented the requirements, architecture, design trade-

offs, and preliminary evaluation of SPOT – an accurate andsensitive meter for monitoring wireless sensor network powerprofiles and energy usage patterns at scale. We showed thatSPOT is able to meet or exceed challenging requirementsunique to wireless sensor networks and other low power sys-tems, as summarized in Table 2. SPOT employs an sim-ple architecture that uses a pure analog sampling front endto provide a large dynamic range, and a dual counter en-ergy accumulation stage to provide high temporal resolution.These features are useful for profiling a range of systems –like pagers, PDAs, and cellphones – which exhibit highlybimodal or widely varying power profiles. SPOT will enableheretofore impossible empirical evaluations of low power de-signs at scale, and it will enable a new class of sensornet

research in which applications can integrate the dynamicpower profile of a system into the application logic.

Metric Requirement SPOTDynamic Range > 10000 : 1 45000 : 1Resolution < 2µA < 1µASampling Rate > 20kHz Internally at 1MHz

Output at I2C speedPerturbation Minimal 1Ω additional load to DUT

Energy measurement via I2CAt least one read per hour

Integration Easy 1.35”x1” all-in-oneCost < $25 Off-the-shelf ICs

Table 2: SPOT satisfies the power and energy me-tering needs of sensornet nodes in situ and at scale.

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