Name: Osuoji Dave Aguguo

Index No. : 5891411

COE 381 – Introduction to Microprocessors

Assignment I

TO BUILD A 1-BIT ARITHMETIC LOGIC UNIT (ALU)

Operations for an ALU

The ALU can perform many different kinds of operations: arithmetic (+, -, *, /), logic operations (AND, OR, Negate (NOT)), and shift and rotate operation, but we will be dealing with the following in this assignment:

f1 f0 Operation

0 0 a + b + cin

0 1 NOT a

1 0 a AND b

1 1 a OR b

The table shows the following operations:

adding a and b, and the carry in, cin

negating a bitwise ANDing a and b bitwise ORing a and b

The ability of the ALU to do the different kinds of operations is derived from a many-to-one switch - the multiplexer. The ALU performs every possible operation on its inputs and then uses multiplexers to pick out the desired result.

THE DESIGN

To implement this 1-bit ALU, we will have the following inputs and outputs:

Three data inputs: a, b, and cin, which is the carry in (needed to do addition). Two control inputs: f1, f0. Two outputs: zi (the result of the operation) and cout, the carry out (needed to do

addition).

Since we want to choose between one of four possible operations, we can use a 4-1 MUX.

How It Works:

The circuit first computes all the possible outcomes: a+b, NOT(a), (a AND b), and (a OR b).

The desired result is then selected using a multiplexer. The control signal of the multiplexer will be the operation code in the computer instruction (stored in the IR - instruction register).

The control signal is programmed into the multiplexer using the control inputs – the control inputs and their functions are explained in more detail on the next page.

THE CONTROL INPUTS:

To select the desired operation among the 4 different possible operations, we will need to input our operation code using 2 "function" bits:

00 will mean: operand1 + operand2 ( a + b ) 01 will mean NOT(operand1) ( NOT a ) 10 will mean operand1 AND operand2 ( a AND b ) 11 will mean operand1 OR operand2 ( a OR b )

THE GATES AND SUB-CIRCUITS

The Multiplexer: The multiplexer uses the control inputs to select the desired output.

Truth Table for Multiplexer:

f1 f2 zi

0 0 D0

0 1 D1

1 0 D2

1 1 D3

zi = f1’ f0’ D0 + f1’ f0 D1 + f1 f0’ D2 + f1 f0 D3

Note: D0, D1, D2 and D3 are the outputs from the different gates, respectively.

The Full Adder: When the control inputs/function bits are set to 00, the data inputs a and b are added.

Truth table for Full Adder:

Function 1: a+bf1 f0 cin a b D0 cout

0 0 0 0 1 1 00 0 0 1 0 1 00 0 0 1 1 0 10 0 1 0 0 1 00 0 1 0 1 0 10 0 1 1 0 0 10 0 1 1 1 1 1

The NOT Gate: When the function bits are set to 01, the complement of input a is found.

Truth table for NOT Gate:

f1 f0 a b D1

0 1 0 0 10 1 0 1 10 1 1 0 00 1 1 1 0

The AND Gate: When the function bits are set to 10, the result of the operation (a AND b) is found.

Truth table for AND Gate:

Function 3: (a) AND (b)f1 f0 a b D2

1 0 0 0 01 0 0 1 01 0 1 0 01 0 1 1 1

The OR Gate: When the function bits are set to 11, the result of (a OR b) is found.

Truth table for OR Gate:

Function 4: (a) OR (b)f1 f0 a b D3

1 1 0 0 01 1 0 1 11 1 1 0 11 1 1 1 1

The above design is for a 1-bit ALU. An 8-bit ALU can be built from 8 identical 1-bit ALUs connected together in cascade. An 8-bit ALU can be used to perform many kinds of operations on 8-bit numbers.

When cascading 1-bit ALUs, the carry output of each ALU is the carry input of the following ALU.