Micro Device

8/13/2019 Micro Device

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MICRODEVICES

MOSFETs Metal Oxide Field Effect Transistors n MOSFET

The most important geometrical parameters:

-

the gate oxide thickness xox- the channel length L- the aspect ratio W/L- the channel with W

Remarks

L, L The effective channel lengthL is smaller than minimum value specified by the

design ruleL

L < L

W/L The aspect ratio is a layout geometrical parameter. The central problem in CMOS

design is finding the aspect ratios that give the desired performance of the circuit.

Symbols for MOSFETs

L

n+

p-Ln+

GDS

W

xax

DG

S

n+n+

contact

-

gate oxide

n+

diffusion

Substrate=bulk=body

G

D

nMOS

B

S

n+p-

n+ n

G

D

B

S

connected to VSS=-

AV

D

G

S

G

D

pMOS

B

S

p+n-

p+

p+

MOSFET p channel MOSFET

pn junction

G

S

B

D

S

GD

connected

to

VDD=+

AV


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nMOSFET. Regions of operations

1. Cutoff region:What is the threshold potential?

- The gate source voltage at which the channel current rises above the OFF state

leakage level

- the device acts as an open-circuit or a

SWITCH in the OFF state

- the impedance between drain and source is

extremely high (up to 1012)

The threshold voltageVth is established in the fabrication sequence. It depends on xox,

the dropping densities of G and B and the physical properties of the source bulk voltage

VBS.

Th Th0 BSV = V + ( - V - ) (1)

VTh0 the zero body bias threshold voltage (VBS= 0)VTh0= 0.5 1V; it can be 0.35V for nanodevices

the body bias factor with units of [V1/2] or the body effect parameter

n= (0.1 1.5) V ; p= (0.4 2) V

the bulk Fermi potential [V]

vDS

ID

avalancheactive

linearvDS= vDsat

increasing vGS

cutoffsubthreshold

vGS

D

G

S

B

vDSvBS0

V-

vGS


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2. The linear region nonsaturation or triode region

The MOST behaves as a voltage controlled resistor(VCR) or as a SWITCH in the OH

state.

DSD GS Th DS

vKWI = (v -V - )v

L 2 (2)

( )D GS Th DS DS GS ThI (v -V )v for v =2 v -V

D GS DSI = G (v ) v

ID ~ vDS

where KW=L

- the transconductance factor

K the process transconductance [A/V2]

E.g. Process 0.8 : Kn~ 90A / V2

Kp~ 30A / V2

K = Cox

- the carrier surface mobility

Cox= ox/ xoxthe gate oxide capacitance per unit area

ox= the permittivity of the oxide

xox= the oxide thickness

W, L = the effective channel width and length respectively

G(vGS) = (vGS- VTh) is a voltage controlled conductance (by vGS)

3. The active regionThe MOST behaves as a current source. It is a voltage controlled current source VCCS

In the active region:D DS

I f(v ) , MOSFET may be biased to the

vGS iD

VDS>VTh

vDS< vGS- VTh

vGSvDS

ron


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Strong, moderate or weak inversion:

a) weak inversion: vGS VTh< 20 mV

A small number of free carriers flow and form a - diffusion current

MOSFET operates like a bipolar transistor

GS BS

T T

v (1-k)vnV V

D Do

wI =I e e

L; n=1.6,.1.8 ; k =1/n

subthreshold region

-100mK vGS- VTh< 0

b) moderate inversion

)22080(...20 mVVmVVv ThThGS ++

Drift and diffusion currents in channel are comparable

c) strong inversion

vGS> VTh+220mV

drift current dominates the IDcomponents:2

D GS Th DS

KwI = (v - V ) (1+ v )

2L (3)

the channel length modulation factor[V-1

] ~ (0.005, 0.06)V-1

subtreshold

IDA

moderateweak

strong

100

10

0 20mV 80-220mV vGS- VTh

vGS

vBS= 0ID

vBS< 0


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The MOST behaves as a VCCS: any increase of vDSwill cause no

increase of IDor only a slight one and the value of ID is function of

vGS.

The parameter determines the slope in the output characteristic.

For short channel lengths this parameter is larger than for long

channels lengths.

Thus depends on L :

LVE

1=

VEis the Early voltage per unit channel length.4. The avalanche regionis also called breakdownmode. IDincreases very steeply with

increasing vDS.

The border between saturation and non-saturation is given by vDSsat , that is

the value of vDSat which IDin equations (2) and (3) achieves the same value

2DSD GS Th DS GS Th

DS GS Th DSsat

2

DSsat DSsat

v 1i = (v -V - ) v (v -V )

2 2

= v -V = v

KWI = v ; =

2 L

v

Small signal models of the MOSFETs

a) Non-saturation region(called also linear, triode, voltage controlled resistance region)

DSD GS Th DS GS Th DS

vKW LWi = (v -V - )v (v -V )v

L 2 L for vDS iD depends

linearly on vDS.

GS

DGS Th GS

DS V

i KWg = = (V -V )=f(V )

v L

GS Th

L 1r =

KW V -V,

vGS

d

s

sdid

vds

vgsr = 1/g

vGS

d

s

ID

real

ID

vDS

ideal


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MOSFETs behaves as a resistance that decreases with the aspect ratio W/L, and also by

increasing VGS. It can be controlled by VGS.

b) saturation regionin strong inversion

),,()1()(2

2

DSBSGSGSThGSD vvvfvVvL

Lwi =+=

The drain current is strongly influenced by vGS, but also by vBS(through VTh) and vDS.

The magnitudes that put into evidence this effect are transconductance and conductance

1) D D Dm GS Th

QuiescentGS GS Thpoint

i 2I 2KWIKWg = = (V -V ) = =

v L V -V L

(4)

2) smb m m

BS BSQ

i g = =g =(0.1,...0.3)g

v 2 -V

(5)

3) Dout D out dsDS DQ

i 1g = = I ; r = r =

v I

(6)

ActiveMOST in strong inversion Low frequencysmall signal model

ds out

out

1r = = r

g

dsds m gs mb bs

ds

ds m gs

vi = g v + g v +

r

i g v

vg

ids

rds

v s gm

g

svbs

b

vdsgm vbs


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Small signal h.f. model

Parasitic capacitances are aided to l.f. model

Cp gate oxide capacitances

depletion capacitances

CGDo, CGC, CGSo = parallel plate capacitors. The gate capacitance is the total input

capacitance.

'

G Gx oC = C = C xWL (7)'L = the drawn channel length

Cox= the capacitance per unit area of the Gate Oxide channel capacitor

CGDo, CGSo correspond to the GD and GS overlap capacitors due to unwanted

diffusion under the gate.

CGB, CSB, CCB = junction capacitors dependent on the reverse voltage

The junction capacitances:

R

o

jo

j m

C AC =

V1+

(8)

M grading parameter

A the total junction area

Cjo the zero bias junction capacitance per cm2

VR the reverse voltage

o the potential barrier

CGDo

CDB

CGS

CBC

CGSo

CSB

n

n

Drain Source

Bulk

n

channel

Gate

CGDo CDBD

G

SCGS CSB

B

B

gate oxide


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The task of laying out the IC is given to a layout designer. He has to understand

the parasitic involved in the layout. Parasitic are the stray capacitances, inductances, pn

junctions and bipolar transistors with the associated problems (break down, stored

charges, latch-up).

Latch-up in CMOS technology

The cross section of a typical CMOS device pair illustrates a pn pn sandwich structure.

pnpn parasitic structure

p+

n

G1 G2

n n+

p p

n

n well

for p MOSFET

V+

p

DpDn

vo

R1R2

1

2 3

45

G2

V

nMOS

Sp

G1

Sn

Dp

Dnvo

pMOS

R2

R1

1

2

3

45

n n

p p

V+

vdsro

s

d

gmbvbs

CSB

CCS

CGDg

vgs

gmvgs

vbs

CDB

d

B


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In normal operation all the pn junction in the structure are reverse biased. If for some

reason the two bipolar transistors enter the active region the circuit has a large positive

feedback and both transistors conduct heavily. The structure is similar to that of a Silicon

Controlled Rectifier (SCR) used in power control. In CMOS this phenomenon is called

latchup and consists in a destructive break down effect. In power electronics a SCR does

not break down, but switches on and remains in conduction (latch-up effect).

IC NPN TRANSISTOR AND OTHER DEVICES IN BIPOLAR

TECHNOLOGY

The optimized device in bipolar technology is npn transistor. The cross section of a

typical npn transistor in a junction-isolated process is shown in the following figure:

The same collector, base and emitter layers serve to realize the other devices in the IC.

They have the electrical parameters of the npn transistor and the same depth. Therefore

the resulted parameters of these devices are very poor and the realist analog ICs used no

pnp transistors. Because these pnp devices utilize the tightly doped n-type epytaxial

material as the base of the transistor, they are inferior to the npn devices in frequency

response and high current behavior:

parameter npn lateral pnp

current gain F 120 50

transition frequency fT 500MHz 5MHz

tenth of GHz

p-substrateburied layer

npn

n-

p+

pp

n+

w

Lateral pnpTvertical pnpT

(substrate T)

p+

n-

n

p p pp

+

Rp

substrate p-

P+


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Low frequency small signal model active region

( )BE TC S CE E C F Bv Vi = I e 1+ v V ; I = I (9)

C Cm

BE TQ

i Ig = = ;

v V

(10)

C C Eo o

CE E CQ

i I Vg = = ; r

v V I

=

(11)

CBE BE be

B C mQ

iv v r = = = r

i i go

(12)

m = g r (13)

gm transconductance ; ro output resistance ; r input shunt resistance

High frequency small signal model takes into account the parasites (resistive and

capacitive parasites)

vb

ro

b

e

gmvbe

r

c

vce

ro

b rb

v1r

re

C

rc

CCS

gmv1

C

c

s

es

r


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rb, rc, re the finite resistance of the silicon between the top contacts on thetransistor and the active base, collector regions or emitter.

C, C, CCSThe capacitors correspond to the b-e, b-c, and c-s junctions and aredepletion capacitances.

ris very large (much layer than X), revery small (we may neglect it) rcis large enough to be taken into account at large currents.

RESISTORS AND CAPACITORS

Resistors. Silicon devices are constructed from diffusion layers. If the pn junctions

formed by there diffusion are reverse biased, then the layer is electrically isolated from

the underlying material. The electrical parameter of the layer is the sheet resistance.

L length ; W widh ; t thickness

LR=

tW (15)

If L = W

R=R =t

(16)

R

is the sheet resistanceof the layer and has the units of ohms per square / ,

It is the resistance of any square sheet of material with thickness t.

In bipolar ICs resistor structures includes base-diffused, emitter-diffused, ion-implanted

pinch, epitaxial and pinched epitaxial resistors.

In MOS ICs resistors include diffused, polysilicon and well resistors.

Capacitors

Capacitance structures include MOS and junction capacitors. (see (7) and (8))

Capacitors play a much more important role in MOS technology than they do in bipolar

technology. Because of the MOS infinite input resistance, MOS amps sense voltages

stored continuously and nondestructively on capacitors. These one can be used to

perform many functions traditionally performed by resistors.

Capacitors have poly-poly, metal-poly, metal-silicon and silicon-silicon plates.

t

LW

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