MICRO-CONTROLLER MOTOROLA HCS12Interrupts

Mechatronics

Department

Faculty of EngineeringAin Shams University

Interrupts Handling

Sources of interruptsInterrupt service

routinesInterruption mechanism

Interrupt control registers

Real-time interrupts

Interrupts

Sources of interrupts

Maskable and non-maskable external interrupt pins.

Reset. Real-Time Interrupt (RTI). A 16-channel

10-bit A/D converter. Enhanced Capture Timer

(ECT) I/O on PortT. A watchdog timer (COP). A clock monitor. Software interrupts

Interrupts

Interrupt Service Routines

The script to be executed when an interrupt occurs.

It can be labeled by any label. Never forget to write RTI at the

end of interrupt service routine to pull back the CPU status and return address from the stack.

Interrupts

Interruption mechanism

1. Saving the program counter value.

2. Saving the CPU status in the stack.

3. Identifying the source of the interrupt.

4. Fetch the starting address of the corresponding interrupt service routine.

5. Executing the interrupt service routine.

6. Restoring the CPU status from the stack.

7. Restoring the program counter from the stack.

8. Resuming the interrupted program.

Interrupts

Interruption mechanism

Masking interrupts: The I and X bits in the CCR act globally.

(setting the I bit disables external IRQ and other maskable internal interrupt sources).

CLI is the instruction used to clear the interrupt flag.

ANDCC#%11101111 – is also used to clear the interrupt flag.

ORCC#%00010000 – is used to enable interrupts by setting the interrupt flag.

If the ISR resets the I bit - not recommended - because it may cause nested interrupts.

Interrupts

Interruption Priorities

Six sources are not maskable: (listed according to priority)1. Power-on reset (POR) or RESET pin2. Clock monitor reset3. Computer operating properly (COP) watchdog reset4. Unimplemented instruction trap5. Software interrupt instruction (SWI)6. XIRQ signal if X bit in CCR = 0The remaining sources are maskable, and any one of them can be given priority over other maskable interrupts.

Interrupts

Interrupt control registers Interrupt Control Register

(INTCR)

Highest Priority Control Register (HPRIO)

Interrupts

Interrupt control registers

Interrupt Control Register (INTCR)

Interrupts

Interrupt control registers

Highest Priority Control Register (HPRIO)

We distinct between interrupt sources with their VectorsThis byte includes the vector of the interrupt with highest

priority.

InterruptsInterrupts vectors • The interrupt vector is the

address of the memory register keeping the address of the ISR instructions.

• Each interrupt type has it’s own vector pointing to it’s own service routine.

• RESET has also a vector pointing to the entry of the main program.

InterruptsInterrupts vectors

definitionCan de defined using either:• Assembly Directives• Assembly instructions

ORG $FFF2 DC.W IRQ

MOVW #ISR,$FFF2

Eng. Mohamed Mahmoud HamdyEng. Mostafa Ahmed ArafaEng. Abd Allah Mahmoud Selim

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