Rhonald Rei R. Pahayac Microprocessors and Microcomputers

BSCpE 5 – 1

Microprocessor Architecture

1. Intel 8080

The Intel 8080 ("eighty-eighty") was the second 8-bit microprocessor designed and manufactured by Intel and was released in April 1974. It was an extended and enhanced variant of the earlier 8008 design, although without binary compatibility. The 8080 has sometimes been labeled "the first truly usable microprocessor", although earlier microprocessors were used for calculators, cash registers, computer terminals, industrial robots and other applications. The architecture of the 8080 strongly influenced Intel's 8086 CPU architecture, which spawned the x86 family of processors.

2. Motorola 6800

The 6800 ("sixty-eight hundred") was an 8-bit microprocessor designed and first manufactured by Motorola in 1974. The MC6800 microprocessor was part of the M6800 Microcomputer System that also included serial and parallel interface ICs, RAM, ROM and other support chips.

3. Zilog Z80

The Zilog Z80 is an 8-bit microprocessor designed by Zilog and sold from July 1976 onwards. It was widely used both in desktop and embedded computer designs as well as for military purposes. The Z80 and its derivatives and clones made up one of the most commonly used CPU families of all time, and, along with the MOS Technology 6502 family, dominated the 8-bit microcomputer market from the late 1970s to the mid-1980s.

Microprocessor Instruction Set

1. Intel 8080

2. Motorola 6800

|Mnem. |Op|HINZVC|IEXD#R|~|Description |Notes ||------+--+------+------+-+-----------------------+------------||ABA |1B|*-****|X |2|Add accumulators |A=A+B ||ADCA s|B9|*-****| XXXX |4|Add with Carry |A=A+s+C ||ADCB s|F9|*-****| XXXX |4|Add with Carry |B=B+s+C ||ADDA s|BB|*-****| XXXX |4|Add |A=A+s ||ADDB s|FB|*-****| XXXX |4|Add |B=B+s ||ANDA s|B4|--**0-| XXXX |4|Logical AND |A=A&s ||ANDB s|F4|--**0-| XXXX |4|Logical AND |B=B&s ||ASL d|78|--****| XX |6|Arithmetic Shift Left |d=d*2 ||ASLA |48|--****|X |2|Arithmetic Shift Left |A=A*2 ||ASLB |58|--****|X |2|Arithmetic Shift Left |B=B*2 ||ASR d|77|--****| XX |6|Arithmetic Shift Right |d=d/2 ||ASRA |47|--****|X |2|Arithmetic Shift Right |A=A/2 ||ASRB |57|--****|X |2|Arithmetic Shift Right |B=B/2 ||BCC a|24|------| X|4|Branch if Carry Clear |If C=0 ||BCS a|25|------| X|4|Branch if Carry Set |If C=1 ||BEQ a|27|------| X|4|Branch if Equal |If Z=1 ||BGE a|2C|------| X|4|Branch if Greater or Eq|If NxV=0 ||BGT a|2E|------| X|4|Branch if Greater Than |If Zv{NxV}=0||BHI a|22|------| X|4|Branch if Higher |If CvZ=0 ||BITA s|B5|--**0-| XXXX |4|Bit Test |A&s ||BITB s|F5|--**0-| XXXX |4|Bit Test |B&s ||BLE a|2F|------| X|4|Branch if Less or Equal|If Zv{NxV}=0|

|BLS a|23|------| X|4|Branch if Lower or Same|If CvZ=1 ||BLT a|2D|------| X|4|Branch if Less Than |If NxV=1 ||BMI a|2B|------| X|4|Branch if Minus |If N=1 ||BNE a|26|------| X|4|Branch if Not Equal |If Z=0 ||BPL a|2A|------| X|4|Branch if Plus |If N=0 ||BRA a|20|------| X|4|Branch Always |PC=a ||BSR a|8D|------| X|8|Branch to Subroutine |-[S]=PC,PC,a||BVC a|28|------| X|4|Branch if Overflow Clr |If V=0 ||BVS a|29|------| X|4|Branch if Overflow Set |If V=1 ||CBA |11|--****|X |2|Compare accumulators |A-B ||CLC |0C|-----0|X |2|Clear Carry |C=0 ||CLI |0E|-0----|X |2|Clear Interrupt Mask |I=0 ||CLR d|7F|--0100| XX |6|Clear |d=0 ||CLRA |4F|--0100|X |2|Clear accumulator |A=0 ||CLRB |5F|--0100|X |2|Clear accumulator |B=0 ||CLV |0A|----0-|X |2|Clear Overflow |V=0 ||CMPA s|B1|--****| XXXX |4|Compare |A-s ||CMPB s|F1|--****| XXXX |4|Compare |B-s ||COM d|63|--**01| XX |7|Complement |d=~d ||COMA |43|--**01|X |2|Complement accumulator |A=~A ||COMB |53|--**01|X |2|Complement accumulator |B=~B ||CPX s|BC|--****| XXX* |5|Compare Index Register |X-s ||DAA |19|--****|X |2|Decimal Adjust Acc. |A=BCD format||DEC d|7A|--**?-| XX |6|Decrement |d=d-1 ||DECA |4A|--**?-|X |2|Decrement accumulator |A=A-1 ||DECB |5A|--**?-|X |2|Decrement accumulator |B=B-1 ||DES |34|------|X |4|Decrement Stack Pointer|S=S-1 ||DEX |09|---*--|X |4|Decrement Index Reg. |X=X-1 ||EORA s|B8|--**0-| XXXX |4|Logical Exclusive OR |A=Axs ||EORB s|F8|--**0-| XXXX |4|Logical Exclusive OR |B=Bxs ||INC d|7C|--**?-| XX |6|Increment |d=d+1 ||INCA |4C|--**?-|X |2|Increment accumulator |A=A+1 ||INCB |5C|--**?-|X |2|Increment accumulator |B=B+1 ||INS |31|------|X |4|Increment Stack Pointer|S=S+1 ||INX |08|---*--|X |4|Increment Index Reg. |X=X+1 ||JMP d|7E|------| XX |3|Jump |PC=d ||JSR d|BD|------| XX |9|Jump to Subroutine |-[S]=PC,PC=d||LDAA s|B6|--**0-| XXXX |4|Load Accumulator |A=s ||LDAB s|F6|--**0-| XXXX |4|Load Accumulator |B=s ||LDS s|BE|--**0-| XXX* |5|Load Stack Pointer |S=s ||LDX s|FE|--**0-| XXX* |5|Load Index Register |X=s ||LSR d|74|--0***| XX |6|Logical Shift Right |d=->{0,d,C} ||LSRA |44|--0***|X |2|Logical Shift Right |A=->{0,A,C} ||LSRB |54|--0***|X |2|Logical Shift Right |B=->{0,B,C} ||NEG d|70|--****| XX |6|Negate |d=-d ||NEGA |40|--****|X |2|Negate accumulator |A=-A ||NEGB |50|--****|X |2|Negate accumulator |B=-B ||NOP |01|------|X |2|No Operation | ||ORAA s|BA|--**0-| XXXX |4|Logical inclusive OR |A=Avs ||ORAB s|FA|--**0-| XXXX |4|Logical inclusive OR |B=Bvs ||PSHA |36|------|X |4|Push |-[S]=A ||PSHB |37|------|X |4|Push |-[S]=B ||PULA |32|------|X |4|Pull |A=[S]+ ||PULB |33|------|X |4|Pull |B=[S]+ ||ROL d|79|--**?*| XX |6|Rotate Left |d={C,d}<- ||ROLA |49|--**?*|X |2|Rotate Left accumulator|A={C,A}<- ||ROLB |59|--**?*|X |2|Rotate Left accumulator|B={C,B}<- ||ROR d|76|--**?*| XX |6|Rotate Right |d=->{C,d} ||RORA |46|--**?*|X |2|Rotate Right acc. |A=->{C,A} ||RORB |56|--**?*|X |2|Rotate Right acc. |B=->{C,B} |

|RTI |3B|??????|X |A|Return from Interrupt |{regs}=[S]+ ||RTS |39|------|X |5|Return from Subroutine |PC=[S]+ ||SBA |10|--****|X |2|Subtract accumulators |A=A-B ||SBCA s|B2|--****| XXXX |4|Subtract with Carry |A=A-s-C ||SBCB s|F2|--****| XXXX |4|Subtract with Carry |B=B-s-C ||SEC |0D|-----1|X |2|Set Carry |C=1 ||SEI |0F|-1----|X |2|Set Interrupt Mask |I=1 ||SEV |0B|----1-|X |2|Set Overflow |V=1 ||STAA d|B7|--**0-| XXX |5|Store Accumulator |d=A ||STAB d|F7|--**0-| XXX |5|Store Accumulator |d=B ||STS d|BF|--**0-| XXX |6|Store Stack Pointer |d=S ||STX d|FF|--**0-| XXX |6|Store Index Register |d=X ||SUBA s|B0|--****| XXXX |4|Subtract |A=A-s ||SUBB s|F0|--****| XXXX |4|Subtract |B=B-s ||SWI |3F|-1----|X |C|Software Interrupt |-[S]={regs} ||TAB |17|--**0-|X |2|Transfer accumulators |B=A ||TAP |06|******|X |2|Transfer to CCR |P=A ||TBA |17|--**0-|X |2|Transfer accumulators |A=B ||TPA |07|------|X |2|Transfer from CCR |A=P ||TST s|7D|--**00| XX |6|Test |s ||TSTA |4D|--**00|X |2|Test accumulator |A ||TSTB |5D|--**00|X |2|Test accumulator |B ||TSX |30|------|X |4|Transfer Stack Pointer |X=S ||TXS |35|------|X |4|Transfer Index Register|S=X ||WAI |3E|-*----|X |9|Wait for Interrupt |-[S]={regs} ||---------+------+------+-+------------------------------------|| CCR |-*01? | | |Unaffect/affected/reset/set/unknown || H |H | | |Half carry (Bit 5) || I | I | | |Interrupt mask (Bit 4) || N | N | | |Negative (Bit 3) || Z | Z | | |Zero (Bit 2) || V | V | | |Overflow (Bit 1) || C | C| | |Carry (Bit 0) ||----------------+------+-+------------------------------------|| |I | |Inherent || nn,E | E | |Extended (Op=E, ~s=e) || nn,X | X | |Index (Op=E-10H, ~s=e+1, JSR ~s=e-1)|| n,D | D | |Direct (Op=E-20H, ~s=e-1) || #n | # | |Immediate (8-bit, Op=E-30H, ~s=e-2) || #nn | * | |Immediate (16-bit, Op=E-30H, ~s=e-2)|| a | R| |Relative (PC=PC+2+offset) ||-------------------------+------------------------------------||DIRECT |Direct addressing mode ||EXTEND |Extended addressing mode ||FCB n |Form Constant Byte ||FCC 'string' |Form Constant Characters ||FDB nn |Form Double Byte ||RMB nn |Reserve Memory Bytes ||-------------------------+------------------------------------|| A B |Accumulators (8-bit) || P |Condition Code Register (CCR, 8-bit)|| PC |Program Counter (16-bit) || S |Stack Pointer (16-bit) || X |Index Register (16-bit) ||-------------------------+------------------------------------|| a |Relative address (-125 to +129) || d s |Destination/source || n nn |8/16-bit expression (0 to 255/65535)|| + - * / |Add/subtract/multiply/divide || & ~ v x |AND/NOT/inclusive OR/exclusive OR |

| <- -> |Rotate left/right || [ ] |Indirect addressing || [ ]+ -[ ] |Indirect auto-increment/decrement || { } |Combination of operands || {regs} |All registers {PC,X,A,B,P} ||-------------------------+------------------------------------|| FFF8H to FFF9H |Hardware interrupt vector || FFFAH to FFFBH |SWI instruction interrupt vector || FFFCH to FFFDH |Non-maskable interrupt vector || FFFEH to FFFFH |Reset vector

3. Zilog Z80

Mnemonic |SZHPNC|Description |Notes ||----------+------+---------------------+----------------------||ADC A,s |***V0*|Add with Carry |A=A+s+CY ||ADC HL,ss |**?V0*|Add with Carry |HL=HL+ss+CY ||ADD A,s |***V0*|Add |A=A+s ||ADD HL,ss |--?-0*|Add |HL=HL+ss ||ADD IX,pp |--?-0*|Add |IX=IX+pp ||ADD IY,rr |--?-0*|Add |IY=IY+rr ||AND s |***P00|Logical AND |A=A&s ||BIT b,m |?*1?0-|Test Bit |m&{2^b} ||CALL cc,nn|------|Conditional Call |If cc CALL ||CALL nn |------|Unconditional Call |-[SP]=PC,PC=nn ||CCF |--?-0*|Complement Carry Flag|CY=~CY ||CP s |***V1*|Compare |A-s ||CPD |****1-|Compare and Decrement|A-[HL],HL=HL-1,BC=BC-1||CPDR |****1-|Compare, Dec., Repeat|CPD till A=[HL]or BC=0||CPI |****1-|Compare and Increment|A-[HL],HL=HL+1,BC=BC-1||CPIR |****1-|Compare, Inc., Repeat|CPI till A=[HL]or BC=0||CPL |--1-1-|Complement |A=~A ||DAA |***P-*|Decimal Adjust Acc. |A=BCD format ||DEC s |***V1-|Decrement |s=s-1 ||DEC xx |------|Decrement |xx=xx-1 ||DEC ss |------|Decrement |ss=ss-1 ||DI |------|Disable Interrupts | ||DJNZ e |------|Dec., Jump Non-Zero |B=B-1 till B=0 ||EI |------|Enable Interrupts | ||EX [SP],HL|------|Exchange |[SP]<->HL ||EX [SP],xx|------|Exchange |[SP]<->xx ||EX AF,AF' |------|Exchange |AF<->AF' ||EX DE,HL |------|Exchange |DE<->HL ||EXX |------|Exchange |qq<->qq' (except AF)||HALT |------|Halt | ||IM n |------|Interrupt Mode | (n=0,1,2)||IN A,[n] |------|Input |A=[n] ||IN r,[C] |***P0-|Input |r=[C] ||INC r |***V0-|Increment |r=r+1 ||INC [HL] |***V0-|Increment |[HL]=[HL]+1 ||INC xx |------|Increment |xx=xx+1 ||INC [xx+d]|***V0-|Increment |[xx+d]=[xx+d]+1 ||INC ss |------|Increment |ss=ss+1 ||IND |?*??1-|Input and Decrement |[HL]=[C],HL=HL-1,B=B-1||INDR |?1??1-|Input, Dec., Repeat |IND till B=0 ||INI |?*??1-|Input and Increment |[HL]=[C],HL=HL+1,B=B-1||INIR |?1??1-|Input, Inc., Repeat |INI till B=0 ||JP [HL] |------|Unconditional Jump |PC=[HL] ||JP [xx] |------|Unconditional Jump |PC=[xx] |

|JP nn |------|Unconditional Jump |PC=nn ||JP cc,nn |------|Conditional Jump |If cc JP ||JR e |------|Unconditional Jump |PC=PC+e ||JR cc,e |------|Conditional Jump |If cc JR(cc=C,NC,NZ,Z)||LD dst,src|------|Load |dst=src ||LD A,i |**0*0-|Load |A=i (i=I,R)||LDD |--0*0-|Load and Decrement |[DE]=[HL],HL=HL-1,# ||LDDR |--000-|Load, Dec., Repeat |LDD till BC=0 ||LDI |--0*0-|Load and Increment |[DE]=[HL],HL=HL+1,# ||LDIR |--000-|Load, Inc., Repeat |LDI till BC=0 ||NEG |***V1*|Negate |A=-A ||NOP |------|No Operation | ||OR s |***P00|Logical inclusive OR |A=Avs ||OTDR |?1??1-|Output, Dec., Repeat |OUTD till B=0 ||OTIR |?1??1-|Output, Inc., Repeat |OUTI till B=0 ||OUT [C],r |------|Output |[C]=r ||OUT [n],A |------|Output |[n]=A ||OUTD |?*??1-|Output and Decrement |[C]=[HL],HL=HL-1,B=B-1||OUTI |?*??1-|Output and Increment |[C]=[HL],HL=HL+1,B=B-1||POP xx |------|Pop |xx=[SP]+ ||POP qq |------|Pop |qq=[SP]+ ||PUSH xx |------|Push |-[SP]=xx ||PUSH qq |------|Push |-[SP]=qq ||RES b,m |------|Reset bit |m=m&{~2^b} ||RET |------|Return |PC=[SP]+ ||RET cc |------|Conditional Return |If cc RET ||RETI |------|Return from Interrupt|PC=[SP]+ ||RETN |------|Return from NMI |PC=[SP]+ ||RL m |**0P0*|Rotate Left |m={CY,m}<- ||RLA |--0-0*|Rotate Left Acc. |A={CY,A}<- ||RLC m |**0P0*|Rotate Left Circular |m=m<- ||RLCA |--0-0*|Rotate Left Circular |A=A<- ||RLD |**0P0-|Rotate Left 4 bits |{A,[HL]}={A,[HL]}<- ##||RR m |**0P0*|Rotate Right |m=->{CY,m} ||RRA |--0-0*|Rotate Right Acc. |A=->{CY,A} ||RRC m |**0P0*|Rotate Right Circular|m=->m ||RRCA |--0-0*|Rotate Right Circular|A=->A ||RRD |**0P0-|Rotate Right 4 bits |{A,[HL]}=->{A,[HL]} ##||RST p |------|Restart | (p=0H,8H,10H,...,38H)||SBC A,s |***V1*|Subtract with Carry |A=A-s-CY ||SBC HL,ss |**?V1*|Subtract with Carry |HL=HL-ss-CY ||SCF |--0-01|Set Carry Flag |CY=1 ||SET b,m |------|Set bit |m=mv{2^b} ||SLA m |**0P0*|Shift Left Arithmetic|m=m*2 ||SRA m |**0P0*|Shift Right Arith. |m=m/2 ||SRL m |**0P0*|Shift Right Logical |m=->{0,m,CY} ||SUB s |***V1*|Subtract |A=A-s ||XOR s |***P00|Logical Exclusive OR |A=Axs ||----------+------+--------------------------------------------|| F |-*01? |Flag unaffected/affected/reset/set/unknown || S |S |Sign flag (Bit 7) || Z | Z |Zero flag (Bit 6) || HC | H |Half Carry flag (Bit 4) || P/V | P |Parity/Overflow flag (Bit 2, V=overflow) || N | N |Add/Subtract flag (Bit 1) || CY | C|Carry flag (Bit 0) ||-----------------+--------------------------------------------|| n |Immediate addressing || nn |Immediate extended addressing || e |Relative addressing (PC=PC+2+offset) |

| [nn] |Extended addressing || [xx+d] |Indexed addressing || r |Register addressing || [rr] |Register indirect addressing || |Implied addressing || b |Bit addressing || p |Modified page zero addressing (see RST) ||-----------------+--------------------------------------------||DEFB n(,...) |Define Byte(s) ||DEFB 'str'(,...) |Define Byte ASCII string(s) ||DEFS nn |Define Storage Block ||DEFW nn(,...) |Define Word(s) ||-----------------+--------------------------------------------|| A B C D E |Registers (8-bit) || AF BC DE HL |Register pairs (16-bit) || F |Flag register (8-bit) || I |Interrupt page address register (8-bit) || IX IY |Index registers (16-bit) || PC |Program Counter register (16-bit) || R |Memory Refresh register || SP |Stack Pointer register (16-bit) ||-----------------+--------------------------------------------|| b |One bit (0 to 7) || cc |Condition (C,M,NC,NZ,P,PE,PO,Z) || d |One-byte expression (-128 to +127) || dst |Destination s, ss, [BC], [DE], [HL], [nn] || e |One-byte expression (-126 to +129) || m |Any register r, [HL] or [xx+d] || n |One-byte expression (0 to 255) || nn |Two-byte expression (0 to 65535) || pp |Register pair BC, DE, IX or SP || qq |Register pair AF, BC, DE or HL || qq' |Alternative register pair AF, BC, DE or HL || r |Register A, B, C, D, E, H or L || rr |Register pair BC, DE, IY or SP || s |Any register r, value n, [HL] or [xx+d] || src |Source s, ss, [BC], [DE], [HL], nn, [nn] || ss |Register pair BC, DE, HL or SP || xx |Index register IX or IY ||-----------------+--------------------------------------------|| + - * / ^ |Add/subtract/multiply/divide/exponent || & ~ v x |Logical AND/NOT/inclusive OR/exclusive OR || <- -> |Rotate left/right || [ ] |Indirect addressing || [ ]+ -[ ] |Indirect addressing auto-increment/decrement|| { } |Combination of operands || # |Also BC=BC-1,DE=DE-1 || ## |Only lower 4 bits of accumulator A used |

Microprocessor Pin Assignments

1. Intel 8080

Pin FunctionsA15-AO Type: O. ADDRESS BUS: The address bus provides the address to memory (up to 64K 8-bit words) or denotes the I/O device number for up to 256 input and 256 output devices. A0 is the least significant address bit.D7-D0 Type: I/O. DATA BUS: The data bus provides bi-directional communication between the CPU, memory, and I/O devices for instructions and data transfers. Also, during the first clock cycle of each machine cycle, the 80BOA outputs a status word on the data bus that describes the current machine cycle. Do is the least significant bit.SYNC Type: O. SYNCHRONIZING SIGNAL: The SYNC pin provides a signal to indicate the beginning of each machine cycle.DBIN Type: O. DATA BUS IN: The DBIN signal indicates to external circuits that the data bus is in the input mode. This signal should be used to enable the gating of data onto the 8080A data bus from memory or I/O.READYType: I. READY: The READY signal indicates to the 8080A that valid memory or input data is available on the 8080A data bus. This signal is used to synchronize the CPU with slower memory or I/O devices. If after sending an address out the 8080A does not receive a READY input, the 8080A will enter a WAIT state for as long as the READY line is low. READY can also be used to single step the CPU.WAIT Type: O. WAIT: The WAIT signal acknowledges that the CPU is in a WAIT state.WR Type: O WRITE: The WR signal is used for memory WRITE or I/O output control. The data on the data bus is stable while the WR signal is active low (WR = 0).HOLD Type: I HOLD: The HOLD signal requests the CPU to enter the HOLD state. The HOLD state allows an external device to gain control of the BOBOA address and data bus as soon as the 8080A has completed its use of these busses for the current machine cycle. It is recognized under the following conditions:• the CPU is in the HALT state.

• the CPU is in the T2 or TW state and the READY signal is active. As a result of entering the HOLD state the CPU ADDRESS BUS (A15-AO) and DATA BUS (D7-D0) will be in their high impedance state. The CPU acknowledges its state with the HOLD ACKNOWLEDGE (HLDA) pin.HLDA Type: O. HOLD ACKNOWLEDGE: The HLDA signal appears in response to the HOLD signal and indicates that the data and address bus will go to the high impedance state. The HLDA signal begins at:• T3 for READ memory or input.• The Clock Period following T3 for WRITE memory or OUTPUT operation.In either case, the HLOA signal appears after the rising edge of <1>2'INTE Type: O. INTERRUPT ENABLE: Indicates the content of the internal interrupt enable flip/flop. This flip/flop may be set or reset by the Enable and Disable Interrupt instructions and inhibits interrupts from being accepted by the CPU when it is reset. It is automatically reset (disabling further interrupts) at time T1 of the instruction fetch cycle (M1) when an interrupt is accepted and is also reset by the RESET signal.INTType: I. INTERRUPT REQUEST: The CPU recognizes an interrupt request on this line at the end of the current instruction or while halted. If the CPU is in the HOLD state or if the Interrupt Enable flip/flop is reset it will not honor the request.RESET1Type: I. RESET: While the RESET signal is activated, the content of the program counter is cleared. After RESET, the program will start at location 0 in memory. The INTE and HLDA flip/flops are also reset. Note that the flags, accumulator, stack pointer, and registers are not cleared.Vss GROUND: Reference.VDD POWER: +12 ±5% V.VCC POWER: +5 ±5% V.VBB POWER: - 5 ± 5% V.

2. Motorola 6800

Pin FunctionsAddress Bus (AOA15) – Sixteen pins are used for the address bus. The outputs are three-state bus drivers capable of driving one standard TTL load and 90 pF. When the output is turned off, it is essentially an open circuit.Data Bus (DO-D7) – Eight pins are used for the data bus. It is bidirectional, transferring data to and from the memory and peripheral devices.Data Bus Enable (DBE) – This level sensitive input is the three-state control signal for the M PU data bus and will enable the bus drivers when in the high state. This input is TTL compatible; however in normal operation it would be driven by the phase two clock.Bus Available(BA) – The Bus Available signal will normally be in the low state; when activated, it will go to thehigh state indicating that the microprocessor has stopped and that the address bus is available. This will occur if the HALT line is in the low state or the processor is in the WAIT state as a result of the execution of a WAIT instruction.Read/Write (R/W) – This TTL compatible output signals the peripherals and memory devices whether the MPU is in a Read (high) or Write (low) state, The normal standby state of this signal is Read (high).RESET – The RESET input is used to reset and start the MPU from a power down condition resulting from a powerfailure or initial start-up of the processor. This level sensitive input can also be used to reinitialize the machine at any time after start-up.Interrupt Request (~Q) – This level sensitive input requests that an interrupt sequence be generated within themachine. The processor will wait until it completes the current instruction that is being executed before it recognizes the request. Non-Maskable Interrupt (NMI) and Wait for Interrupt (WAI) – The MCWCO is capable of handling two types of interrupts: maskable (~) as described earlier, and nonmaskable (~) which is an edge sensitive input. IRQ ismaskable by the interrupt mask in the condition code register while ~ is not maskable.Three-State Control (TSC) – When the level sensitive Three-State Control (TSC) line is a logic “l”, the AddressBus and the Rim line are placed in a high-impedance state. VMA and BA are forced low when TSC= “1” to preventfalse reads or writes on any device enabled by VMA.Valid Memory Address (VMA) This output indicates to peripheral devices that there is a valid address on the address bus. In normal operation, this signal should be utilized for enabling peripheral interfaces such as the PIA and ACiA.HALT – When this level sensitive input is in the low state, all activity in the machine will be halted. This input is level sensitive.

3. Zilog Z80

Pin FunctionsA15–A0Address Bus (output, active High, tristate). A15-A0 form a 16-bit address bus. The Address Bus provides the address for memory data bus exchanges (up to 64 Kbytes) and for I/O device exchanges.BUSACKBus Acknowledge (output, active Low). Bus Acknowledge indicates to the requesting device that the CPU address bus, data bus, and control signals MREQ, IORQ RD, and WR have entered their high-impedance states. The external circuitry can now control these lines.BUSREQBus Request (input, active Low). Bus Request has a higher priority than NMI and is always recognized at the end of the current machine cycle. BUSREQ forces the CPU address bus, data bus, and control signals MREQ IORQ, RD, and WR to go to a high-impedance state so that other devices can control these lines. BUSREQ is normally wired-OR and requires an external pull-up for these applications. Extended BUSREQ periods due to extensive DMA operations can prevent the CPU from properly refreshing dynamic RAMS.D7–D0Data Bus (input/output, active High, tristate). D7–D0 constitute an 8-bit bidirectional data bus, used for data exchanges with memory and I/O.HALTHALT State (output, active Low). HALT indicates that the CPU has executed a HALT instruction and is waiting for either a non-maskable or a maskable interrupt (with the mask enabled) before operation can resume. During HALT, the CPU executes NOPs to maintain memory refresh.INTInterrupt Request (input, active Low). Interrupt Request is generated by I/O devices. The CPU honors a request at the end of the current instruction if the internal software-controlled interrupt enable flip-flop (IFF) is enabled. INT is normally wired-OR and requires an external pull-up for these applications.IORQInput/Output Request (output, active Low, tristate). IORQ indicates that the lower half of the address bus holds a valid I/O address for an I/O read or write operation. IORQ is also generated concurrently with M1 during an interrupt acknowledge cycle to indicate that an interrupt response vector can be placed on the data bus.M1Machine Cycle One (output, active Low). M1, together with MREQ, indicates that the current machine cycle is the opcode fetch cycle of an instruction execution. M1 together with IORQ, indicates an interrupt acknowledge cycle.MREQMemory Request (output, active Low, tristate). MREQ indicates that the address bus holds a valid address for a memory read of memory write operation.NMINon-Maskable Interrupt (input, negative edge-triggered). NMI has a higher priority than INT. NMI is always recognized at the end of the current instruction, independent of the status of the interrupt enable flip-flop, and automatically forces the CPU to restart at location 0066H.RDRead (output, active Low, tristate). RD indicates that the CPU wants to read data from memory or an I/O device. The addressed I/O device or memory should use this signal to gate data onto the CPU data bus.RESETReset (input, active Low). RESET initializes the CPU as follows: it resets the interrupt enable flip-flop, clears the PC and registers I and R, and sets the interrupt status to Mode 0. During reset time, the address and data bus go to a high-impedance state, and all control output signals go to the inactive state. Notice that RESET must be active for a minimum of three full clock cycles before the reset operation is complete.RFSHRefresh (output, active Low). RFSH, together with MREQ indicates that the lower seven bits of the system’s address bus can be used as a refresh address to the system’s dynamic memories.WAITWAIT (input, active Low). WAIT communicates to the CPU that the addressed memory or I/O devices are not ready for a data transfer. The CPU continues to enter a WAIT state as long as this signal is active. Extended WAIT periods can prevent the CPU from properly refreshing dynamic memory.

WRWrite (output, active Low, tristate). WR indicates that the CPU data bus holds valid data to be stored at the addressed memory or I/O location.CLKClock (input). Single-phase MOS-level clock.

What is Microcontroller?

A microcontroller is an integrated chip that is often part of an embedded system. It includes a CPU, RAM, ROM, I/O ports, and timers like a standard computer, but because they are designed to execute only a single specific task to control a single system, they are much smaller and simplified so that they can include all the functions required on a single chip. Unlike a microprocessor, which is a general-purpose chip used to create a multi-function computer or device and requires multiple chips to handle various tasks, this device is meant to be more self-contained and independent, and functions as a tiny, dedicated computer.

The great advantage of microcontrollers, as opposed to using larger microprocessors, is that the parts-count and design costs of the item being controlled can be kept to a minimum. They are typically designed using complementary metal oxide semiconductor (CMOS) technology, an efficient fabrication technique that uses less power and is more immune to power spikes than other techniques. There are also multiple architectures used, but the predominant architecture is Complex Instruction Set Computer (CISC), which allows the chip to contain multiple control instructions that can be executed with a single macro instruction. Some use a Reduced Instruction Set Computer (RISC) architecture, which implements fewer instructions, but delivers greater simplicity and lower power consumption.