Micro-2407 Technical Reference
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Transcript of Micro-2407 Technical Reference
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MICRO - 2407
Technical Reference
Version 1.0
Technical Clarification /Suggestion :
/
Technical Support Division,
Vi Microsystems Pvt. Ltd.,Plot No :75,Electronics Estate,
Perungudi,Chennai - 600 096,INDIA.
Ph: 91- 44-2496 1852, 91-44-2496 3142
Mail : [email protected],Web : www.vimicrosystems.com
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MICRO - 2407 TECHNICAL REFERENCE INTRODUCTION
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CHAPTER - 1
INTRODUCTION TO MICRO - 2407
1.1. INTRODUCTION
Micro-2407 is a 16-bit (data lines) fixed point DSP trainer, based on texas instruments
TMS320LF2407A DSP Processor. This trainer enables the user to learn the basics of digital
signal processing & digital control along with basic DSP functions like filtering, PWM
generation, calculation of spectral characteristics of input analog signals. The trainer helps to
perform real time implementation of very complex algorithms, such as adaptive control, Motor
control etc.,
The TMS320LF2407A contains a C2xx DSP core along with useful peripherals such as
ADC, Timer, PWM Generation are integrated onto a single piece of silicon.
The Micro-2407 trainer can be operated in two modes. In the mode:1(serial mode ) the
trainer is configured to communicate with PC through serial port. In the mode:2 (stand alone
mode), the user can interact with the trainer through the IBM PC keyboard and 16 × 2 LCD
display.
1.2. SPECIFICATIONS
1. PROCESSOR
CPU : Texas Instruments TMS320LF2407A,
Crystal Frequency : 10MHz.
Clock Frequency : 40 Mhz
Wait States : 2 for EPROM, 0 for On-Chip RAM, 2 for external
RAM and 6 for LCD DISPLAY
2. MONITOR (EPROM) : 0x0000 - 0xBFFF for 48kwords
3. MEMORY
Program RAM : 0xC000 - 0xFFFF for 16kwords.
Data RAM : 0x9000 - 0xFFFF for 32kwords (0x8000 to 0x8FFF
reserved for monitor).
4. SERIAL : One RS232C Serial Interface using on-chip
SERIAL COMMUNICATION INTERFACE (SCI)
module
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5. TIMER : On-chip timer can be used.
6. INTERRUPTS : 6 Interrupt lines of TMS320LF2407A are
available to users.
7. IBM AT KEY BOARD : CD 4015-101 KEY keyboard controller
8. DISPLAY : 16x2 LCD display (For Mode-2).
9. ON-BOARD BATTERY BACKUP : 3.6V, Ni-Cd Battery
10. POWER SUPPLY (LPOW-001A) SPECIFICATIONS
Mains : 230 Volts AC at 50 Hz
Outputs : 1. + 5 Volts, 3.5 Amps Regulated
2. + 12 Volts, 150 mA Regulated
3. - 12 Volts, 150 mA Regulated
4. +5 Volts, 500 mA Regulated
11. SYSTEM POWER CONSUMPTION
Digital
+ 5 V : 1.5 Amps+ 12 V : 100 mA
- 12 V : 100 mA
Analog
+ 5 V : 200 mA
1.3 FEATURES OF TMS320C / F2XX
1. TMS320C / F2xx core CPU
* 32-bit Central Arithmetic Logic Unit (CALU).
* 32-bit accumulator.
* 16-bit x 16-bit parallel multiplier with a 32-bit product capability.
* Eight 16-bit auxiliary registers with a dedicated arithmetic unit for indirect addressing of
data memory.
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2. MEMORY
* 64 kwords program memory space
* 64 kwords Data memory space* 64 kwords I / O space
3. POWER
* Static CMOS Technology
* Four power-down modes to reduce power consumption.
4. EMULATION
* IEEE standard 1149.1 test access port to on-chip scan-based emulation logic.
5. SPEED
* 25-ns (40MIPS) instruction cycle time, with most instructions single cycle.
6. EVENT MANAGER
* Two event managers A & B.
* Four 16-bit general-purpose timers with six modes including continuous up counting and
continuous down counting.
* Six 16-bit full compare units with dead band capability in each event managers.* Two 16 bit Timer PWMs in each event manager.
* Six capture units, four of which have quadrature encoder pulse interface capability.
7. DUAL 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC)
8. 40 INDIVIDUALLY PROGRAMMABLE, MULTIPLEXED I/O PINS.
9. PHASE-LOCKED LOOP (PLL) BASED CLOCK MODULE.
10. WATCHDOG (WD) TIMER MODULE WITH REAL-TIME INTERRUPT (RTI)
11. SERIAL COMMUNICATION INTERFACE (SCI)
12. SERIAL PERIPHERAL INTERFACE (SPI)
13. CAN CONTROLLER MODULE
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MICRO - 2407 TECHNICAL REFERENCE HARDWARE OVERVIEW
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CHAPTER - 2
HARDWARE OVERVIEW
The hardware description of Micro-2407 is provided in this chapter. It describes the technical
capabilities of TMS320LF2407A trainer board and the peripherals & memory as related to
TMS320LF2407A CPU.
The Block Diagram of Micro-2407 Trainer consists of Processor section, DAC section, ADC
section, Display section etc., The following are the buses connecting various sections to
processor in Micro-2407
ADDRESS AND DATA BUS
16 Bit data bus and 16 bit address bus given to data transceivers and octal buffers. They are
qualified R / W and STRB. The output of these buffers and latches comprise of system bus (D0
to D15) and address bus (A0 to A15).
CONTROL BUS
The control signal required for proper operation of the signal are the Read / Write signal for the
memory devices and the Read / Write signals for I/O devices. Since the processor is capable of
accessing memory as separate data and program spaces, the signals PS, DS and R/W are used togenerate the proper Read / Write enable signals for all the devices. The entire logic is
implemented using TTL MSI Devices.
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2.1 FUNCTIONAL BLOCK DIAGRAM OF MICRO - 2407 TRAINER BOARD
Figure - 1 Functional Block Diagram
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Figure - 2 Architecture of TMS320LF2407A CPU
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2.2 ARCHITECTURE OF TMS320LF2407A
The TMS320LF2407A DSP controller is a programmable digital controller. The controller
combines the power CPU with the on-chip memory and the peripherals.
The Controller offers 40 MIPS (million instructions per second) performance. This fast
performance is well suited for processing control parameter in application where large amount
of calculation are to be computed quickly.
The figure - 2 illustrates the Architecture of TMS320LF2407A CPU and the explanation for the
peripherals in CPU are given below.
1. C2xx DSP CORE
The C2xx DSP core is a 16-bit fixed point processor (i.e. it works with 16-bit binary number).
The DSP core consists of several sub components to perform arithmetic operations with 16-bit
binary numbers.The components of C2xx DSP core:
i. Central Arithmetic Logic Unit (CALU)
ii. Accumulator
iii. Data scaling shifters
iv. Multiplier
v. Product scaling shifters
vi. Auxiliary register and auxiliary register arithmetic unit (ARAU)
i. Central Arithmetic Logic Unit (CALU)
The DSP core performs 2's-complement arithmetic using the 32-bit CALU. The CALU uses 16-
bit words taken from the data memory, derived from an immediate instruction, or from the 32-bit
multiplier result. In addition to arithmetic operations, the CALU can perform Boolean operations.
ii 32-BIT Accumulator
The accumulator stores the output from the CALU and provides an input to the CALU. The
accumulator also performs shift and rotate operations. Its word length is 32-bit. The
accumulator is divided into a high-order word (bits 31 through 16) and a low-order word (bits
15 through 0). Instructions in assembly language are provided for storing and loading the higher
and lower order accumulator words to data memory.
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iii. Shifters
The core contains three 32-bit shifters that allow for scaling, bit extraction, extended arithmetic,
and overflow-prevention operations. The scaling shifters make possible commands that shift dataleft or right. The three shifters are mentioned below.
* Input data-scaling shifter (input shifter) - This shifter left-shifts 16-bit input data by 0 to
16 bits to align the data to the 32-bit input of the CALU.
* Output data-scaling shifter (output shifter) - This shifter left-shifts data from the
accumulator by 0 to 7 bits before the output is stored to data memory. The content of the
accumulator remain unchanged.
* Product - scaling shifter (product shifter) - The product register (PREG) receives the
output of the multiplier. The product shifter shifts the output of the PREG before that
output is sent to the input of the CALU. The product shifter has four product shift modes
(no shift, left shift by one bit, left shift by four bits, and right shift by six bits), which are
useful for performing multiply / accumulate operations, fractional arithmetic, or justifying
fractional products.
iv 16 x 16 Bit Parallel Multiplier
The multiplier performs a 16-bit two's complement multiplication with a 32-bit result in a single
instruction cycle. The multiplier consists of three units: the T-Register, P-Register, and multiplier
array. The 16-bit T-Register temporarily stores the multiplicand and the P-Register stores the 32-bit product. Multiplier values either comes from the data memory or derived immediately from the
MPY (multiply immediate) instruction word. The fast on-chip multiplier allows the device to
perform fundamental operations such as convolution, correlation and filtering. Two
multiply/accumulate instructions in the instruction set fully utilize the computational bandwidth of
the multiplier, allowing both operands to be processed simultaneously.
v. Auxiliary Register Arithmetic Unit (ARAU) and Auxiliary Registers
The ARAU generates data memory addresses when an instruction uses indirect addressing to
access data memory. Eight auxiliary registers (AR0 through AR7) support the ARAU, each of
which can be loaded with a 16-bit value from data memory or directly from an instruction. Eachauxiliary registers are mainly used as ? pointers” to data memory locations to more easily facilitate
looping or repeating algorithms. The auxiliary register pointer (ARP) embedded in status register
ST0 references the auxiliary register.
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2. EVENT MANAGER (EV)
There are two identical Event Managers (EVA and EVB) on TMS320LF2407A. The event
manager is a most important peripheral in digital motor control. It supports the functions neededfor controlling the electromechanical device.
Each EV Module in the TMS320LF2407A contains following sub components:
i. Interrupt logic
ii. Two general purpose timers
iii. Three compare units
iv. Three capture units
v. Quadrature encoder pulse circuit
i. Interrupt Logic
EV interrupt sub-system is slightly different from the main interrupt and are arranged into three
groups (A, B, C ) and each group has its own mask and flag register and is assigned to particular
CPU Interrupt priority level at the PIE. EV interrupt are happen to be only at INT2, INT3 and
INT4 CPU priority levels.
ii. GP Timer
A General purpose timer is configured to count up, down or continuously up and down. Each
EV has two GP timers. Timer1 & 2 for EVA and Timer3 & 4 for EVB. Timers are configured
to generate interrupt or trigger another peripheral on certain cases such as timer overflow,
underflow or compare.
iii. Compare Unit
A PWM signal can also be generated using compare unit .Their functions are identical to GP
Timer compare units. The PWM outputs associated with the compare unit allows for generation
of six PWM ouputs per EV whereas GP timer associated for two PWM outputs.
iv. Capture Unit
The capture unit on TMS320LF2407A allows an event on the capture pin to be time stamped by
selected GP Timer. Capture units 1, 2 and 3 are associated with EVA while capture units 4, 5,
6 are associated with EVB.
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v. Quadrature Encoder Pulse
QEP's are two sequence of pulses which have a variable frequency and are 90 out of phase witho
each other. QEP's are usually generated by position speed sensing device such as a rotary opticalencoder. Each EV module has a QEP circuit associated with capture unit.
Figure - 3 Quadrature Encoder Pulses
3. CONTROLLER AREA NETWORK
CAN module is a useful peripheral for specific application of TMS320LF2407A. The CAN
module is used for multi-master serial communication between external hardware. The CAN
bus has a high level of data integrity and is ideal for operation in noisy environment such as inan automobile, or industrial environments that requires reliable communication and data
integrity.
4. SERIAL PERIPHERAL INTERFACE
The SPI is a high speed synchronous serial input / output port that allow a serial bit stream of
program length to be shifted in and out of device at a programmed bit transfer rate.
SPI is mainly used for communication between DSP and external peripherals or another DSP
device. Typical uses of SPI includes communication with external shift register, display drivers
or ADC's.
5. SERIAL COMMUNICATION INTERFACE
The programmable SCI module that supports asynchronous serial digital communication between
CPU and other asynchronous peripherals that uses standard NRZ format (Non-retun to-zero).
It is used for communication between external device and CPU.
The SCI transmits and receives serial data one bit at a time at programmable bit rate. The SCI's
receivers and transmitter are double buffered and each has its own separate enable and interrupt
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bits, Both may be operated independently or simultaneously in full-duplex mode. To ensure data
integrity, the SCI checks data that has been received for break detection, parity, overrun and
framing errors. The speed of bit rate is programmable to over 64K different speeds through a 16-
bit baud select register.
6. WATCH DOG TIMER (WD)
The watchdog timer (WD) peripheral assets a system reset when its internal counter overflows.
The WD timer will count for specific amount of time. It is necessary for the user's software to
reset the WD timer periodically so that unwanted reset does not occurs. When the software
enters into endless loop or CPU is disrupted, the WD timer will overflow and DSP reset will
occur which cause the DSP program to branch to its starting point. In this way WD ensures
reliability of CPU, thus ensuring system integrity.
7. PHASE LOCKED LOOP CLOCK MODULE (PLL)
The PLL module is basically an input clock multiplier that allows the user to control the input
clock frequency to DSP processor. External to the processor a clock reference is generated by
a oscillator crystal. This signal is then used to clock the DSP core and is multiplied or divided
by PLL. Usual multiplication factor ranges from 0.5x to 4x that of external clock signal. The
default value of PLL is 0.5x.
8. ANALOG TO DIGITAL CONVERTER
The ADC on TMS320LF2407A allows the DSP to sample the analog voltage signals. The O/Pof ADC is an integer number which represent voltage level sampled, ADC will generate a 10-bit
numbers for every conversion it performs. ADC stores the conversion result in register that are
16-bit wide. The 10 MSB's are ADC result & LSB's are filled with zero, hence value in resultant
register is simply right shifted by six places.
9. JOIN TEST ACTION GROUP PORT (JTAG)
JTAG provides a standard method for emulation and development by interfacing the personal
computer and TMS320LF2407A DSP Controller. The XDS510PP+ or equivalent emulator pod
provides the connection between the JTAG module on TMS320LF2407A and the personal
computer. The JTAG allows PC to take full control over DSP processor and it can be used with
code composer.
Figure - 4 Interfacing of PC to Micro-2407
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2.3 MEMORY
1. MEMORY MAPPING
The TMS320LF2407A DSP controller has 16-bit address bus that can access the following
individual selectable memory.
i. Program Memory
ii. Data Memory
iii. I/O space
Program Memory
The program memory stores the user code, the immediate operands. A maximum of 64k, 16-bit
words can be addressed in program memory.
Figure - 5 Program memory mapping
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Data Memory
Data Memory address up to 64k of 16-bit words. 32k words are internal memory. Internal data
memory includes memory mapped registers, DARAM and peripheral memory mapped registers.Data memory can be addressed either with direct addressing mode or indirect addressing mode.
Figure - 6 Data Memory Mapping
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I/O Spaces
I/O Space memory addresses up to 64k, 16-bit words.
Figure - 7 I/O Spaces
2. MEMORY CONFIGURATION
Figure-8 shows the complete Program Memory Allocation of Micro-2407 based on
TMS320LF2407A CPU. As seen from the figure, the Monitor EPROM occupies the address
0x0000-0xBFFFH of the total addressable program memory area, and is constituted by two
numbers of 27512 EPROMs. This is indicated as "MONITOR PROGRAM AREA". The
remaining of the program memory space is for RAM area available as program memory to the
user for program development and execution.
Figure-9 shows the complete Data Memory Allocation of Micro-2407 based on
TMS320LF2407A CPU. The data RAM in the address range 0x9000 - 0xFFFF is available
default to the user.
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Figure - 8 Program Memory Allocation Table for TMS320LF2407A CPU
* The data RAM in the address range 0x8000 to 0x8FFF are used as the monitor buffer and
the user are restricted to use those addresses.
Figure - 9 Data Memory Allocation Table for TMS320LF2407A CPU
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ALLOCATION OF PROGRAM ROM ON MICRO-2407 TRAINER
The Micro-2407 has the main Monitor EPROMs which control the complete system operation.
The main software for responding to the user requests is programmed in these EPROMs. The27512 EPROMs have the Assembler, Disassembler and Serial monitor for the TMS320F2407A
CPU. Out of the aggregate 48kW [i.e. 0x0000 to 0xBFFF] U1 comprises of Lower byte and U5
comprises the Higher byte of each word that can be addressed at each address.
Out of the aggregate 28kwords DATA RAM [i.e, 0x9000 to 0xFFFF] U6 comprises the higher
byte and U2 the lower byte of each word that can be addressed at each address.
ALLOCATION OF PROGRAM RAM
The below Table -1 gives a clear idea about the mapping of program memory (RAM), on the
base board of Micro-2407 Trainer.
Sl.No. Start
Address
End
Address
Socket No. IC Used Total
Capacity
1. 0xC000 0xFFFF U2, U6 71024 × 2 16kwords
Table - 1 Location of Program RAM in Micro-2407 Trainer.
ALLOCATION OF DATA RAM
Table - 2 gives a clear idea about the mapping of RAM on Micro-2407 Trainer from the
minimum to the maximum configuration. The basic configuration is 32 kwords.
Sl.No. Start
Address
End
Address
Socket No. IC Used Total
Capacity
1 0x9000 0xFFFF U3, U7 71024 × 2 32kwords
Table - 2 Location of Data RAM in Micro-2407 Trainer
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I/O CONFIGURATION
This section explains the I/O facilities available on the Micro-2407 Trainer. All the peripherals
are I/O mapped. The I / O address used in the Micro-2407 trainer are given in the table - 3.
I/O ADDRESS
IN HEX
READ/WRITE PERIPHERAL USED
00
01
02
04
05
06
WRITE
READ
READ
WRITE
WRITE
WRITE
LCD Display
LCD Display
IBM PC Keyboard
DAC AD8582 CH1 select
address
DAC AD8582 CH2 select
address
Digital O/P line LEDs
Table - 3 I/O Configuration for Micro - 2407
2.4 INTERRUPT VECTOR ADDRESSES
In Micro-2407 the interrupt vector addresses are remapped to 0xC000 to 0xC03F page in
program memory. Remapping is done by giving a branch in monitor EPROM at locations
0x0000 - 0x003F. The relative vector address are described in the following table. To use
the interrupts in the program just add 0xC000H to the required interrupt vector address. For eg.if INT1 is used, its address is 0x0002H. So branch to ISR should be given at location 0xC000
+ 0x0002 = 0xC002H.
(0x0000 - 0x003F IS REMAPPED TO 0xC000 TO 0xC03F)
Note:
All the addresses are in hexadecimal.
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MICRO-2407 TECHNICAL REFERENCE FRONT PANEL DESCRIPTION
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CHAPTER - 3
FRONT PANEL DESCRIPTION
This chapter gives a brief description about Front Panel of Micro-2407 Trainer board.
Figure - 10 Pictorial View of Micro-2407
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The following tabular column shows the component and the locations with reference to Micro-
2407 Trainer Board.
NO COMPONENT REF.DES LOCATION IN FIG
1 Regulator IC LM317 VR1 1I
2 ADC Buffer Ic's
3403
U27
U28
U28
U30
1K
2K
2K
3K
3 DAC IC
AD8582
U32 4J / 4K
4 IC TLO84 U31 4K
5 EPROM IC'S
W 27C512
U1
U5
2A
2C
6 RAM IC'S
71204
U2
U3
U6
U7
2A
3A
2B / 2C
3B / 3C
7 74LS 214 IC'S U33U34
U35
4J4J
4K
8 BACKUP BATTERY X1 4B
9 BUFFER IC'S
74LS245
U17
U18
U19
U20
2E
3E
3E / 4E
4E
10 DC TO DC CONVERTER IC
DC010505
U4 1C
11 MAX232 U21 1G
12 IC 7406 U9
U10
1D
2D
13 6N137 U15
U16
1E
1E
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14 SWITCHES SW1
SW2
SW3
RES
6H
6I
6J
6J / 6K
15 74LS273 IC'S U25
U26
5H
5I
16 CD 4015 IC'S U36
U37
5J
5K
17 PAL 16L8 U12
U13
4C / 4D
5C / 5D
18 IC 273 U8
U14
5B
5C
19 IC 74LS14 U11 3C
20 IC 70151 U38 5J
21 SIP RESISTOR SIP 2F / 2G
22 7400 IC'S U23
U24
5E
5F
23 POWER SUPPLY P1
P3
1B
1H
24 SERIAL PORT CONNECTOR P2 1G
25 40 PIN FRC CONNECTOR P4 4A
26 14 PIN MALE CONNECTOR P5 5A
27 26 PIN FRC CONNECTOR P6 2L
28 3 PIN J801 CONNECTOR P7 4L
29 34 PIN FRC CONNECTOR P8 4L / 5L
30 IBM PC/AT KB CONNECTOR P9 6L
31 TRIMPOT (100k) TP1 3J
32 TRIMPOT (10k) TP2 3J
33 TRIMPOT (100k) TP3 3K
34 TRIMPOT (10k) TP4 3K
35 TRIMPOT (100k) TP5 6D
Table - 4 Location of Components in Micro-2407 Board
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MICRO-2407 TECHNICAL REFERENCE FRONT PANEL DESCRIPTION
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3.1 FRONTPANEL DESCRIPTION
Front Panel of Micro-2407 consists of the following
i. ADC section
ii. DAC section
iii. PWM section
iv. Opto Coupler Section
v. Inverter section
vi. SIP Resistor Section
vii. LCD & keyboard interface
viii. PAL section
ix. Signal Conditioning
x. Switches
1. ADC SECTION
The 16 ADC channel's are terminated to the 26 pin header and the remaining 10 pins are
grounded. The input analog signals are buffered using ICs 3403 (U27, U28, U29, U30). Each
buffer IC (3403) consists of four buffers. The ADC inputs are given through the protection
section to the processor. The protection section is built out of zener regulators to prevent the
processor from high voltage flow of above 3.3V.
Figure - 12 Block Diagram of ADC Section
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2. DAC SECTION
Figure - 13 Block Diagram of DAC Section
The digital output from the processor is converted into Analog using IC AD8582 (U32). It is
a 2 channel DAC IC . The output from the DAC is of low voltage, hence IC TL084 is placed at
the output of the DAC to amplify the DAC output. The trimpots are provided at the output of
DAC to adjust the offset and gain of channel - 5.
Trimpot Functions
TP1 To adjust the offset of channel 2
TP2 To adjust the gain of channel 2
TP3 To adjust the offset of channel 1
TP4 To adjust the gain of channel 1
Table -5 Trimpot functions
The output of DAC is terminated at the 3 pin J801 connector named as P7.
3. PWM SECTION
In the PWM Section three numbers of 74LS14 (U34, U33, U35) ICs are provided. The default
PWM output of the processor is high signals. The 74LS14 IC is provided to invert the PWM
outputs to avoid shoot through faults. The 34 pin FRC header (P8) is provided to connect the
PWM outputs from the processor. In this 34 pin header 4 pins are provided for TIMER PWM
output and 6 pins are provided for capture inputs to the processor. Capture input is a square
pulse input for eg. speed feedback from an encoder.
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4. OPTO COUPLER SECTION
To operate the kit through PC a MAX232 level detector along with the buffer inverter ICs
7436(U9 and U10) and 6N137 (U15 & U16) are used for serial communication. The 6N137opto-coupler IC is placed in between the two 7406 IC's to isolate the high voltage serial port side
from the low voltage processor side.
Figure - 14 Optocoupler Block Diagram
5. INVERTER SECTION
The IC 74LS14 (U11) is used to generate RST
6. SIP RESISTOR
The Sip Resistor SIP1, of 10 k is used to pull up the interrupts in the processor which are to be
kept high.
7. LCD AND KEYBOARD INTERFACE
The IC'S 74LS273 (U25 and U26) are used for the LCD display and Trimpot TP5 is used to
adjust the brightness of the LCD. The IC'S CD4015 (U36 and U37) are used as keyboard
interface IC'S for interfacing the keyboard to Micro-2407 Trainer to work in mode2 (Stand alone
mode)
8. PAL SECTION
Two numbers of PAL16V8B are used for the purpose of chip selection. The IC74LS273 (U14
& U8) are used as Latch IC for LED's. Each IC 273 is used for 8 LED'S to glow. If a chip is
selected through PAL, Digital output is given to IC74LS273 and the data output to the
corresponding Address is high & the particular LED glows.
9. SIGNAL CONDITIONING
dd. ddThe Power supply P3 provided to supply the analog V (AV ) of the processor. The Regulator
(LM317) VR1 is placed in between the power supply and the processor for converting the supply
voltage 5V to desired 3.3V. The IC DC010505 (U4) is a DC voltage conversion IC to convert
the input voltage of 5V to 3.3V for the isolated serial communications. The IC 70151(U38) is
ddused to divide the input voltage of 5 V to 3.3V and 1.8V and given to (Digital V ) processor.
A 3.6V Ni-Cd Battery Backup is provided to supply RAM during power off.
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10. SWITCHES
Two number of 7400 (U23, U24) ICs are placed at Micro-2407 Kit. These ICs are provided to
connect the processor I/O pins to the switches SW1, SW2 and SW3.
Switches Function
SW1 To select mode - 1 or mode - 2
SW2 Input Switch
SW3 Input Switch
RES Processor reset switch
Table - 6 Switch Functions
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CHAPTER - 4
JUMPER DETAILS
4.1 INTRODUCTION
This chapter gives a brief introduction about jumpers placed in Micro-2407 Trainer board and
their configuration.
JUMPER POSITION FUNCTION LOC. DEST
J1 STRAP (Default) To supply the protection circuit
and ADC buffer ICs fromregulator.
2I
J2 STRAP A
STRAP B
To select B10 I/O lines to high.
To select B10 I/O lines to low
2D
J3 STRAP A(Default)
STRAP B
To select microprocessor mode.
To select micro controller mode.
3D
J4 STRAP A
STRAP B (Default)
To select Vcc to high.
To select Vcc to low.
4G
J5 STRAP B (Default) To connect PWM10 to ground. 4G
J6 STRAP B (Default) To connect PWM11 to ground. 4H
J7 STRAP B (Default) To connect PWM12 to ground. 4H
J8 STRAP B (Default) To connect T4 PWM to ground. 4H
J9 STRAP B (Default) To connect CAP5 to ground. 4H
J10 STRAP B (Default) To connect CAP6 to ground. 4H
J11 STRAP B (Default) To connect INT B (PDPINTB-) to
ground
4H
J12 STRAP A
STRAP B
TRST high with emulator.
TRST low with emulator.
5H
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J13 STRAPA (Default)
STRAP B
To operate in mode 1.
To operate in mode 1.
5E
J14 STRAP A (Default) SW2 to decrease the speed. 5F
J15 STRAP B(Default) SW3 to increase the speed. 5G
J16 STRAP(Default) To have 3.3V for processor from
voltage divider.
5K
Table - 7 Jumper Configuration
Note
Default strapping is the necessary position of jumpers to work in Micro-2407 Trainer.
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CHAPTER - 5
CONNECTOR DETAILS
5.1 INTRODUCTION
Following are the shortlist of connectors available on Micro-2407 trainer board.
P1 - 5 Pin Unicon Connector
P2 - 9 Pin Serial port Connector
P3 - 2 Pin J801 Connector
P4 - 40 Pin FRC Connector
P5 - 14 Pin JTAG Connector
P6 - 26 Pin FRC Connector
P7 - J801 3 Pin Connector
P8 - 34 Pin FRC Connector
P9 - 6 Pin Keyboard Connector
5.2 POWER CONNECTOR: (P1)
CONNECTOR USED
Single row 5 Pin UNICON Male Connector
- Spacing between pins 2,3,4,5 = 5mm
- Spacing between pins 1&2 = 7.5mm
PIN DETAILS
1
2
3
4
5
GND
-12V
+12V
NC
VCC
Table - 8 Signal Description of P1 Connector
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Where,
NC - No Connection
VCC - +5V Power SupplyGND - 0V Reference Ground
MATING CONNECTOR
Single row 5-pin UNICON Female Connector
- With the same spacing as said above
5.3. SERIAL PORT CONNECTOR: (P2)
CONNECTOR USED
9 Pin D type Male Connector
- Pins arranged in two rows of 5 and 4 pins
- Grid pitch is 2.76 mm * 2.84 mm
- The connector is AMPHENOL standard
PIN DETAILS
12
3
4
5
6
7
8
9
NCRxD
TxD
NC
GND
NC
RTS
CTS
NC
Table - 9 Signal Description of P2 Connector
SIGNAL DEFINITION
TxD - Transmit Data
RxD - Receive Data
RTS - Ready to send
CTS - Clear to send
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MATING CONNECTOR
9 Pin D type Female Connector with the same specifications.
5.4 J801 2 PIN CONNECTOR (P3)
PIN CONFIGURATION
1 - GND
2 - +5v
5.5 GENERAL PURPOSE INPUT / OUTPUT CONNECTOR (P4)
CONNECTOR USED : 40 Pin Dual row male header
MATING CONNECTOR : 40 Pin Dual row female Socket
5.6 14 PIN JTAG CONNECTOR (P5)
CONNECTOR USED : 14 Pin Double row male connector
MATING CONNECTOR : 14 Pin Double row female Socket
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5.7. ADC INPUT FRC CONNECTOR (P6)
CONNECTOR USED
26 Pin Double Row Header (13*2)
PIN DETAILS
1
2
3
4
5
6
7
9
11
13
15
17
19
21
23
25
8,10,12,1416,18,20,22
24,26
ADC8
ADC15
ADC0
ADC7
ADC9
ADC6
ADC1
ADC10
ADC11
ADC2
ADC12
ADC3
ADC13
ADC4
ADC5
ADC14
GNDGND
GND
Table - 10 Signal Description of P6 Connector
MATING CONNECTOR
26 Pin Double row socket
5.8 J801 3 PIN CONNECTOR (P7)
PIN CONFIGURATION
1 - GND
2 - DAC1 OUTPUT
3 - DAC2 OUTPUT
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5.9 PWM OUTPUT 34 Pin FRC connector (P8)
Connector Used : 34 Pin Double Row Header
SIGNAL DESCRIPTION
PIN DETAILS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1728
29
30
31
32
33
34
18
19
20 - 27
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
PWM8
PWM9
T1PWM
T2PWM
T3PWM
CAP1
CAP2
CAP3
CAP4
PDPINTA-PWM10
PWM11
PWM12
T4PWM / T4CMP
CAP5 / QEP4
CAP6 / I/O
PDP/INTB1-
CCV
CCV
GND
Table - 11 Signal Description of P8 Connector
MATING CONNECTOR
34 Pin Double Row Socket
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5.10 IBM PC KEYBOARD CONNECTOR: (P9)
CONNECTOR USED
6 Pin PS2 Female Connector
PIN DETAILS
1
2
3
4
5
6
NC
KBDATA
VCC
GND
NC
KBCLK
Table - 12 Signal Descirption of P9 Connector
SIGNAL DEFINITION
CLK - Keyboard Clock
DATA - Serial Data from keyboard
MATING CONNECTOR
6 Pin PS2 Male Connector (Available in the IBM PC Keyboard itself)