Metrology RoadmapMetrology Roadmap2001 Update2001 Update

EuropeEurope Alain Deleporte (ST)Alain Deleporte (ST)Ulrich Mantz (Infineon)Ulrich Mantz (Infineon)

Vincent Vachellerie (ST)Vincent Vachellerie (ST)

JapanJapan

KoreaKorea

Taiwan Taiwan Henry Ma (EPISIL)Henry Ma (EPISIL)

USUS James Whetstone (NIST)James Whetstone (NIST)Alain Diebold (Int. SEMATECH)Alain Diebold (Int. SEMATECH)

AGENDAAGENDA

• 1999 – 2000 - 2001

• 2001 Difficult Challenges

• 2001 Technology Requirements

• 2001 Potential Solutions

1999 Metrology Roadmap Highlights1999 Metrology Roadmap HighlightsYear of First Product

ShipmentTechnology Generation

1999180 nm

2000 20012002

130 nm2003 2004

2003100 nm

Driver

DRAM 1/2 Pitch 180 165 150 130 120 110 100 D½Logic Isolated Lines 140 120 100 85 80 70 65 M Gate

Microscopy and LithographyMicroscopy resolution(nm) for P/T=0.1 1.4 1.2 1.0 0.85 0.8 0.7 0.65 MPU

Wafer Gate CDControl*

13 12 10 8.5 8 7 6.3 MPU

Wafer CD ToolPrecision* P/T=.2Isolated Lines**

2.6 2.4 2.0 1.8 1.6 1.4 1.3 MPU

Mask Area MetrologyTool Precision P/T=.2

4.8 4.2 3.4 2.8 2.6 2.4 2.2 MPU

Front End ProcessesLogic Dielectric ThickPrecision 1 (nm) B 0.0025 0.0024 0.0021 0.0017 0.0016 0.0013 0.0012

MPUGate

2D Dopant ProfileSpatial Resolution (nm) 3 3 3 2 2 2 1.5

MPUGate

InterconnectBarrier layerThick (nm)process range (± 3)Precision 1 (nm)

2320%0.08

1920%0.06

1620%0.05

1320%0.04

1120%0.035

720%0.02

320%0.01

MPU

Metrology Challenges by 2000 ITRS NodeMetrology Challenges by 2000 ITRS NodeTiming BringsTiming Brings RED RED CloserCloser

Technology Node 180 nm 130 nm 90nm 60 nm 40 nm 30 nm DriverLithography MetrologyWafer Gate CD nm post-etch contol

12 8 6 4 3 2 MPU

Wafer CD Tool 3 Precision P/T=0.2 Isolated Lines

2.4 1.6 1.2 0.8 0.6 0.4 MPU

Overlay Control (nm) (mean +3 )

65 45 31 25 20 15 MPU

Overlay Metrology Precision (nm) P/T=0.1

6.5 4.5 3.1 2.5 2 1.5 MPU

Front End Processes MetrologyLogic Dielectric Thick Precision 3 (nm) 0.0075 0.006 0.004 0.0032 0.0024 0.002

MPU

Metrology for Ultra-Shallow Junctions at Channel Xj (nm)

50.4 32.4 23.6 16.4 11.6 8 MPU

Interconnect MetrologyBarrier layer thick (nm) process range (±3 ) Precision 1 (nm)

1720%0.08

1320%0.04

1020%0.03

720%0.02

520%0.016

420%0.013

MPU

New to – New to – Five Difficult Challenges Five Difficult Challenges 65nm / Before 2007 65nm / Before 2007

• Key requirement for Cu/Damascene metrology is void detection in Cu lines and pore size distribution (find killer voids)

• Scribe line shrinkage reduce test structure area making high precision measurements difficult in scribe lines.

• Determination of manufacturing Metrology when device and interconnect technology remain undefined.

New to – New to – Five Difficult Challenges Five Difficult Challenges 65nm / After 2007 65nm / After 2007

Difficult ChallengesDifficult Challenges

Five Difficult Challenges 65 nm / Through 2007 Summary of Issues

Factory level and company wide metrology integration for in situ and inline metrology tools; continued development of robust sensors and process controllers; and data management that allows integration of add-on sensors

Standards for process controllers and data management must be agreed upon. Conversion of massive quantities of raw data to information useful for enhancing the yield of a semiconductor manufacturing process. Better sensors must be developed for trench et

Impurity detection (especially particles) at levels of interest for starting materials and reduced edge exclusion for metrology tools. Control of gettering.

Existing capabilities will not meet Roadmap specifications. Very small particles must be detected and properly sized.

Control of high-aspect ratio technologies such as Damascene challenges all metrology methods. Key requirements are void detection in copper lines and pore size distribution in patterned low k.

New process control needs are not yet established. For example, 3-dimensional (CD and depth) measurements will be required for trench structures in new, low k dielectrics.

Measurement of complex material stacks and interfacial properties including physical and electrical properties.

Reference materials and standard measurement methodology for new, high k

gate and capacitor dielectrics with interface layers, thin films such as interconnect barrier and low k dielectric layers, and other process needs. Optical measurement of gate and c

Measurement test structures and reference materials. Scribe lines are shrinking and correlation to variation of chip properties is difficult. Overlay and other test structures are sensitive to process variation, and test structure design must be improved to insure correlation between scribe line measuremen

Difficult ChallengesDifficult Challenges

Five Difficult Challenges < 65 nm / Beyond 2007

Standard electrical test methods for reliability of new materials, such as ultra-thin gate and capacitor dielectric materials, are not available.

The wearout mechanism for new, high k gate and capacitor dielectric materials is unknown.

Statistical limits of sub-70 nm process control Controlling processes where the natural stochastic variation limits metrology will be difficult. Examples are low-dose implant, thin gate dielectrics, and edge roughness of very small structures.

3D dopant profiling The dimensions of the active area approach the spacing between dopant atoms, complicating both process simulation and metrology. Elemental measurement of the dopant concentration at the requested spatial resolution is not possible.

Determination of manufacturing Metrology when device and interconnect technology remain undefined.

The replacement devices for the transistor and structure and materials replacement for copper interconnect are being researched.

Nondestructive, production worthy wafer and mask level microscopy for critical dimension measurement for 3-D structures, overlay, defect detection, and analysis

Accelerated feature size reduction makes precision requirements for transistor and interconnect CD difficult or impossible to attain by known methods. Surface charging and contamination interfere with electron beam imaging. CD measurements must account f

Metrology Challenges by 2001 ITRS NodeMetrology Challenges by 2001 ITRS NodeTiming BringsTiming Brings RED RED CloserCloser

Technology Node 130 nm 90nm 65 nm 45 nm 32 nm 22 nm DriverLithography MetrologyEtched Gate CD (nm) 65 37 25 18 13 9 MPU

Wafer Gate CD nm post-etch contol

6.5 3.7 2.5 1.8 1.3 0.9 MPU

Wafer CD Tool 3 Precision P/T=0.2 Isolated Lines

0.65 0.37 0.25 0.18 0.13 0.09 MPU

Overlay Control (nm) (mean +3 )

45 31 25 20 15 ? MPU

Overlay Metrology Precision (nm) P/T=0.1

4.5 3.1 2.5 2 1.5 ? MPU

Front End Processes MetrologyLogic Dielectric Thick Precision 3 (nm)

0.006 0.004 0.0032 0.0024 0.002 0.0016 MPU

Metrology for Ultra-Shallow Junctions at Channel Xj (nm)

26 14.8 10 7.2 5.2 3.6MPU

0.4*CD

Interconnect MetrologyBarrier layer thick (nm) process range (±3 ) Precision 1 (nm)

1320%0.04

1020%0.03

720%0.02

520%0.016

420%0.013

? MPU

FEP TWG Requests to MetrologyFEP TWG Requests to Metrology• Make sure Clive is at May 17 FEP meeting• Important feature is channel length at silicon interface which is etched gate

length• FEP introducing new roadmaps for FERAM and Flash

– Need metrology to know if FERAM is fatigued– Metrology for inter-poly dielectric

• Need to close on the metrology info in the starting materials section of FEP• Discuss EOT models which seem to have issues below 1 nm - Curt to write• Discuss need to make software more user friendly and not use lookup tables• Multiple high k layers are being developed as potential high k and optical

models need to be developed. Nano-laminate of Al and Hf oxide• How do you achieve statistical significance using non-goal post methods,

I.e., range of defects. Metrology measurements need to comprehend • In-line monitoring for epi-growth

Factory Integration TWG and MetrologyFactory Integration TWG and Metrology

• Define Integrated Metrology • Stand alone unit more capable than integrated metrology• Includes Cluster tool and sensor based measurements.• Process level, Wafer level, tool level metrology• Near term Metrology community would benefit from

factory integration modeling factory modeling to determine factory impact.

• Metrology community looks to working with the factory integration community to develop Standards for open architecture to allow IC manufacturer to select metrology

Metrology TWG Metrology TWG RequestsRequests

• Interconnect TWG– 2001 Requirements Tables– Barrier Thickness – Insulator Killer Pore Size and conc.– Cu line Void conc. or %

Interconnect TWG Requests to MetrologyInterconnect TWG Requests to Metrology• Voids in Cu and low k pore size metrology• Add discussion on Cu ECD bath metrology• See new planarization requirements such as metric for thinning of dielectric• For SOC

– K value of high k at high frequency– R and L measurements needs (thick metal thickness, composition)

• Etch– Sidewall angle– Trench bottom profile , possibly after planarization– Diagnostic for run to run stability– End point for low k etch– In-situ monitoring and process control feedback– High aspect ratio contact etch

• Bottom CD• Profile and angle• End point detection

Litho TWG Requests to Metrology TWGLitho TWG Requests to Metrology TWG

• Add Line Edge roughness requirements– Kyle Patterson correlated line edge roughness on electrical

properties at SPIE 2001

• Registration of Mask after pellicle placement• Measurement of Arc n, k, thickness need specs• Measure minimum dimension (height and width) of scattering

and anti scattering bars• Overlay kerf structures do not represent on chip variation• Litho will separate optical and non optical NGL mask

requirements. Some will deal with metrology. Are there unique metrology requirements that need to be addressed.

Packaging TWG Requests to Metrology TWGPackaging TWG Requests to Metrology TWG

• 4 new sections: Opto-electronics, MEMS, multi-chip, materials

• Metrology areas : – Need good input parameters for Thermal Mechanical Simulation

• Interfacial adhesion • Bulk vs microstructural properties

– Nano-indentation not broadly available– Need to understand fracture toughness thus need to measure

modulus variation during use and test.– Scanning acoustic microscopy, x-ray, and adhesion are now in-

line for packaging– Laser Moire are becoming in-line for stress measurement– High frequency materials properties

Why are CD Measurement Requirements RED?

• There is no universal metrology solution for all CD measurements.– e.g., Scatterometry meets Focus-Exposure precision

needs to (70 nm node?) for resist lines but not for contacts (yet).

• 3D info needed for undercut gate, contact, and other structures.

• Precision includes tool matching and near + long term measurement variation.

CD-SEM a Potential Solution CD-SEM a Potential Solution for for

Wafer and Mask / R&D + ProductionWafer and Mask / R&D + Production

From Sato and Mizuno, EIPBN 2000, Palm Springs, CA

Barriers and Solutions

• 193 & 157 nm Resist Damage» lower dose images

• Precision Improvements» new nano-tip source

• Depth of Focus» new SEM concept needed

• Ultimate Limit of CD-SEM» ~ 5 nm for etched poly Si Gate

60 nm node130 / 90 nm node 40 nm node

Schottky Emitter

Anode

Final Aperature

Detector

Magnetic Lens

Electrostatic Lens

Specimen

Z

Ucol

UE

CD

-SE

M

Depth of Focusvs

Resolution

Damage to 193 Resist

from e beam &

DoF

Structure

Coherent Electron Beam

illumination footprint

detector

detector

e holography

“Boot Tip”

Line Scan

CD

-AF

M

Tip technology low throughput Tip Technology

scat

tero

met

ry

Metal Gates

0th order

Incident LaserBeam

contacts

CD Potential Solutions for Mask and WaferCD Potential Solutions for Mask and Wafer

Reason for Red is Precision and Tool Matching

IR or UV for In-Line ?

Existingin-line

metrology

zro2 Optical Constants

Photon Energy (eV)1.0 2.0 3.0 4.0 5.0 6.0 7.0

Rea

l(D

iele

ctric

Con

stan

t),

1

Imag(D

ielectric Constant),

2

4.0

5.0

6.0

7.0

8.0

9.0

10.0

0.0

1.0

2.0

3.0

4.0

12

ZrO2 Dielectric Function

60 nm node130 / 90 nm node 40 nm node

Gate Dielectric Metrology Potential SolutionsGate Dielectric Metrology Potential SolutionsEnable High k Development with Existing ToolEnable High k Development with Existing Tool

Interconnect Metrology SolutionsInterconnect Metrology SolutionsBarrier/Seed Cu FilmsBarrier/Seed Cu Films

ZY

X

Wafer Positioning Stage

Sample

Detector

Aperture

Lens

Probe Laser

Excitation Laser

Neutral Density (ND) Filters

Phase Masks (PM)

Lens

Lens

20x 90 mm Spot Size

~1-2 seconds/point (measurement + data analysis + stage motion)

Excitation LaserDiode-Pumped, Pulsed, Frequency-Doubled Nd:YAG microchip laser. 600 ps Pulse

AlGaAs Diode Laser

5 Potential Solutions 5 Potential Solutions all expected to meet precision requirementsall expected to meet precision requirements

some are extendable to patterned waferssome are extendable to patterned wafers

Objective lens

GenerationlaserProbe laser

Beam splitter

Visionsystem

Detector

Detail inwafer

Junction

Beam

Excess carriers

X-Ray Tube

Thin-Film Sample

Monochromator

Spatially ResolvingX-Ray Sensor

0.15 mm 1psec

Pulsed Laser(200 fsec; 90 MHz) 800nm

Servo delay

Lens

FrequencyDoubler

photocell

Wafer

WavelengthSelector

Acoustic ISTSPicosecond acoustics

X-ray reflectivityX-ray fluorescence

Non-contact resistivity

Materials Characterization Enables Materials Characterization Enables Process and Metrology DevelopmentProcess and Metrology Development

High Angle - Annular Dark Field STEMHigh Angle - Annular Dark Field STEM

GaAs

EELS Spectrometer

Annular Detector

1.4Å

As Ga

1.3Å Scanning

Probe

Objective Lens

I Z 2

Z=31 Z=33

Electron Beam

Thin Foil Sample

Image Plane

diffracted beammisses annular detector

Enlarged view of Lattice Planes“on axis” to electron beam

scatter from atoms or atomic columns

HA-ADF & EELS

0

500

1000

1500

2000

520 530 540 550 560 570

Interface

7Å from interface

Inte

nsi

ty (a.

u.)

Energy (eV)

Oxynitride and High k Interfaces

Dave Muller - Lucent

1.1MeV deuteron

14N(d,) 12C reaction:

12C

HeCapture & decay

14N

NRATotal N in oxynitride

Metrology & New StructuresMetrology & New Structures

Gate Gate

Drain

Source

Vertical Vertical TransistorTransistor

2000 and 2001 Changes2000 and 2001 Changes

• Accelerated Timeline Brings RED closer………..

• Developments in some CD measurements push Red out further for some applications?