METAMOC: Modular Execution Time Analysis UsingModel Checking

Mads Chr. Olesen joint work with

Andreas Engelbredt Dalsgaard, Martin Toft,René Rydhof Hansen, Kim Guldstrand Larsen

Aalborg University

July 6th 2010

Introduction Modelling Approach UPPAAL, explained Experiments Future Work

Overview of METAMOC

1/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work

Overview of METAMOC

(UPPAAL model)Main memory Cache

specifications

Control Flow Graph(UPPAAL model)

Complete model(UPPAAL model)

Caches(UPPAAL models)

combine

model check(UPPAAL)

WCET

generate(cache−gen)

executableAnnotated

value analysis(WALi)

Assembly

disassemble(objdump, Dissy)

(UPPAAL model)Pipeline

(Assembly−to−UPPAAL)

generate

2/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work

Overview of METAMOC

Control Flow Graph(UPPAAL model)

Complete model(UPPAAL model)

Caches(UPPAAL models)

combine

model check(UPPAAL)

WCET

generate(cache−gen)

value analysis(WALi)

Assembly

disassemble(objdump, Dissy) (Assembly−to−UPPAAL)

generate

executableAnnotated

(UPPAAL model)Pipeline

(UPPAAL model)Main memory Cache

specifications

2/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work

Overview of METAMOC

Control Flow Graph(UPPAAL model)

Complete model(UPPAAL model)

Caches(UPPAAL models)

combine

model check(UPPAAL)

WCET

generate(cache−gen)

value analysis(WALi)

Assembly

(Assembly−to−UPPAAL)

generate

executableAnnotated

(UPPAAL model)Pipeline

(UPPAAL model)Main memory Cache

specifications

disassemble(objdump, Dissy)

2/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work

Overview of METAMOC

Control Flow Graph(UPPAAL model)

Complete model(UPPAAL model)

Caches(UPPAAL models)

combine

model check(UPPAAL)

WCET

generate(cache−gen)

value analysis(WALi)

(Assembly−to−UPPAAL)

generate

executableAnnotated

(UPPAAL model)Pipeline

(UPPAAL model)Main memory Cache

specifications

disassemble(objdump, Dissy)

Assembly

2/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work

Overview of METAMOC

Control Flow Graph(UPPAAL model)

Complete model(UPPAAL model)

Caches(UPPAAL models)

combine

model check(UPPAAL)

WCET

generate(cache−gen)

executableAnnotated

(UPPAAL model)Pipeline

(UPPAAL model)Main memory Cache

specifications

disassemble(objdump, Dissy)

Assembly

(Assembly−to−UPPAAL)

generate

value analysis(WALi)

2/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work

Overview of METAMOC

Complete model(UPPAAL model)

Caches(UPPAAL models)

combine

model check(UPPAAL)

WCET

generate(cache−gen)

executableAnnotated

(UPPAAL model)Pipeline

(UPPAAL model)Main memory Cache

specifications

disassemble(objdump, Dissy)

Assembly

(Assembly−to−UPPAAL)

generate

value analysis(WALi)

Control Flow Graph(UPPAAL model)

2/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work

Overview of METAMOC

Complete model(UPPAAL model)

Caches(UPPAAL models)

combine

model check(UPPAAL)

WCET

executableAnnotated

(UPPAAL model)Pipeline

(UPPAAL model)Main memory Cache

specifications

disassemble(objdump, Dissy)

Assembly

(Assembly−to−UPPAAL)

generate

value analysis(WALi)

Control Flow Graph(UPPAAL model)

generate(cache−gen)

2/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work

Overview of METAMOC

Complete model(UPPAAL model)

combine

model check(UPPAAL)

WCET

executableAnnotated

(UPPAAL model)Pipeline

(UPPAAL model)Main memory Cache

specifications

disassemble(objdump, Dissy)

Assembly

(Assembly−to−UPPAAL)

generate

value analysis(WALi)

Control Flow Graph(UPPAAL model)

generate(cache−gen)

Caches(UPPAAL models)

2/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work

Overview of METAMOC

Complete model(UPPAAL model)

model check(UPPAAL)

WCET

executableAnnotated

(UPPAAL model)Pipeline

(UPPAAL model)Main memory Cache

specifications

disassemble(objdump, Dissy)

Assembly

(Assembly−to−UPPAAL)

generate

value analysis(WALi)

Control Flow Graph(UPPAAL model)

generate(cache−gen)

Caches(UPPAAL models)

combine

2/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work

Overview of METAMOC

model check(UPPAAL)

WCET

executableAnnotated

(UPPAAL model)Pipeline

(UPPAAL model)Main memory Cache

specifications

disassemble(objdump, Dissy)

Assembly

(Assembly−to−UPPAAL)

generate

value analysis(WALi)

Control Flow Graph(UPPAAL model)

generate(cache−gen)

Caches(UPPAAL models)

combine

Complete model(UPPAAL model)

2/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work

Overview of METAMOC

WCET

executableAnnotated

(UPPAAL model)Pipeline

(UPPAAL model)Main memory Cache

specifications

disassemble(objdump, Dissy)

Assembly

(Assembly−to−UPPAAL)

generate

value analysis(WALi)

Control Flow Graph(UPPAAL model)

generate(cache−gen)

Caches(UPPAAL models)

combine

Complete model(UPPAAL model)

model check(UPPAAL)

2/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work

Overview of METAMOC

executableAnnotated

(UPPAAL model)Pipeline

(UPPAAL model)Main memory Cache

specifications

disassemble(objdump, Dissy)

Assembly

(Assembly−to−UPPAAL)

generate

value analysis(WALi)

Control Flow Graph(UPPAAL model)

generate(cache−gen)

Caches(UPPAAL models)

combine

Complete model(UPPAAL model)

model check(UPPAAL)

WCET

2/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work

Current Work

Support for pipelines

ARM9TDMIARM7TDMIATMEL AVR 8-BIT

Support for instruction/data caches

Automatically generatedLRU/FIFO replacement policy

Value analysis for predicting memory accesses

Implemented using Weighted Push-Down SystemsInter-proceduralCurrently syntactic constant-propagation

Timing anomalies cannot be (consistently) handled

Experiments with caches are with LRU caches, not FIFO as on the realARM9

3/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work

Modelling in METAMOC

Fetch stage TA

Decode stage TA

Execute stage TA

Memory stage TA

Writeback stage TA

Process function TAs

Data cache TAInstruction cache TA

Main memory TA

Pipeline

Caches

Dependency through code

Synchronisation

Overview of the ARM9 automata

4/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work

Modelling in METAMOC

fooCall!

fooReturn?done!

fetch!

main

fooCall?

fetch!fooReturn!

foo

Sketch of the function automata for a process

5/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work

Modelling in METAMOC

Instruction cache

Data cache

Main memory

ARM9TDMI pipeline

Memory stage

Writeback stageExecute stage

Decode stage

Fetch stage

ARM920T

Caches

writeback?

Writeback

m_done?

memory?

Memory

writeback!

m_done!

e_done?

execute?

Execute

memory!

e_done!

d_done?

decode?

Decode

execute!

d_done!

f_done?

fetch?

decode!

f_done!

done?

Fetch

ARM9 overview and sketch of pipeline automata

6/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work

UPPAAL

7/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work

UPPAAL

8/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work

UPPAAL

9/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work

UPPAAL Zones

10/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work

UPPAAL Zones

Delay is cheap - large zones

Resilient to different memory wait delays

Many small steps expensive - smaller zones

Zones can be collapsed, overapproximation

11/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work

Eliminating non-determinism

Since no timing anomalies, cut down on the number of distinct pathsas much as possible

Pigeonhole optimisations

Iterate loops the maximum number of timesDon’t forward jump if path is subset of not jumping

“Executing more code increases the execution time”

Can be disabled if timing anomalies present

12/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work

Experiments

Evaluation using WCET benchmark programs from MälardalenReal-Time Research Centre

ApplicabilityPerformance

Discarded a number of programs

Floating point operations handled by software routinesDynamic jumpsSome programs do not compile for our architectures

21 programs for ARM and 19 programs for AVR

Manually annotated loop bounds

13/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work

Experiments

Relative improvement in WCET for

ARM9.

Analysis times in minutes for AVR

and ARM9.

14/17

Introduction Modelling Approach UPPAAL, explained Experiments Future Work

Future Work

Improvements in model checker technology

Our models atypical: more deterministic, longer paths, largerSummarizing long deterministic paths - “short-cuts”Parallel/Distributed model checkingGuiding the search - A*

Data sensitivity/flow facts

Track values of registers in model

Timing anomalies

Introduces more non-determinismImproving model checker technology

Schedulability instead of WCET analysis

SARTS project has done this for Java bytecode on the JOP processor

15/17

Thank you for your attention!

Questions?

http://metamoc.dk

http://metamoc.dk

1 IntroductionOverview of METAMOCCurrent Work

2 Modelling ApproachModelling in METAMOCModel Checking using UPPAAL

3 UPPAAL, explainedUPPAAL ZonesEliminating non-determinism

4 ExperimentsExperiments

5 Future WorkFuture Work

IntroductionOverview of METAMOCCurrent Work

Modelling ApproachModelling in METAMOCModel Checking using UPPAAL

UPPAAL, explainedUPPAAL ZonesEliminating non-determinism

ExperimentsExperiments

Future WorkFuture Work

Appendix