Memory Memory Address Decoding.
72
FETCH CIRCUITRY INCREM ENTOR EXECUTE CIRCUITRY ARITHM ETIC & LOGIC UNIT (ALU) A D D R E S S D E C O D E R CLOCK ACCUM ULATOR OPCODE OPERAND ADDRESS JUM P ADDRESS INSTRUCTION REGISTERS PROGRAM COUNTER LOAD PROGRAM INSTRUCTION COUNTER REGISTERS EXECUTE CONTROL OPCODE IN ACCUM ULATOR INSTRUCTION REGISTER CONTROL CONTROL ALU CONTROL M EM OPCODE IN
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Transcript of Memory Memory Address Decoding.
FETCH CIRCUITRY
INCREMENTOR
EXECUTE CIRCUITRY
ARITHMETIC &LOGIC UNIT
(ALU)
ADDRESS
DECODER
CLOCK
ACCUMULATOR
OPCODE OPERANDADDRESS
JUMPADDRESS
INSTRUCTION REGISTERS
PROGRAM COUNTER
LOAD PROGRAM INSTRUCTION COUNTER REGISTERS EXECUTE CONTROL
OPCODE IN
ACCUMULATORINSTRUCTION REGISTER CONTROL CONTROL ALU CONTROL MEM
OPCODE IN
Memory
FETCH CIRCUITRY
INCREMENTOR
EXECUTE CIRCUITRY
ARITHMETIC &LOGIC UNIT
(ALU)
ADDRESS
DECODER
CLOCK
ACCUMULATOR
OPCODE OPERANDADDRESS
JUMPADDRESS
INSTRUCTION REGISTERS
PROGRAM COUNTER
LOAD PROGRAM INSTRUCTION COUNTER REGISTERS EXECUTE CONTROL
OPCODE IN
ACCUMULATORINSTRUCTION REGISTER CONTROL CONTROL ALU CONTROL MEM
OPCODE IN
NAND
NAND
NOT
Memory or Register Bitbased on a “D Flip-Flop” --- other designs are more efficient
Data InData Out
Write
NAND
NAND
AND NOT
AND NOT
AND NOT
AND NOT
NOT
Memory or Register Bitbased on a “D Flip-Flop” --- other designs are more efficient
Data InData Out
Write
AND NOT
AND NOT
AND NOT
AND NOT
NOT
Memory or Register Bitbased on a “D Flip-Flop” --- other designs are more efficient
Data InData Out
Write
Power is just switched on – everything is at 0 momentarily.
0
0
00
0
0
0 0
0 0
0 0
0
0
0
0
0 0
0
0
AND NOT
AND NOT
AND NOT
AND NOT
NOT
Memory or Register Bitbased on a “D Flip-Flop”
Data InData Out
Write
Logic gates activate – no input yet, and no change in output
1
0
10
0
0
0 0
0 1
0 0
1
1
1
0
1 0
1
0Data out stays at 0No change
AND NOT
AND NOT
AND NOT
AND NOT
NOT
Memory or Register Bitbased on a “D Flip-Flop”
Data InData Out
Write
Data In changes, but Write stays at 0 -- no change in output
1
0
10
1
0
1 0
1 0
0 0
1
1
1
0
1 0
1
0Data out stays at 0Data changes to 1
AND NOT
AND NOT
AND NOT
AND NOT
NOT
Memory or Register Bitbased on a “D Flip-Flop”
Data InData Out
Write
Data changes back, but Write stays at 0 -- no change in output
1
0
10
0
0
0 0
0 1
0 0
1
1
1
0
1 0
1
0Data out stays at 0Data changes to 0
AND NOT
AND NOT
AND NOT
AND NOT
NOT
Memory or Register Bitbased on a “D Flip-Flop”
Data InData Out
Write
Data changes again, but Write stays at 0 -- still no change out
1
0
10
1
0
1 0
1 0
0 0
1
1
1
0
1 0
1
0Data out stays at 0Data changes to 1
AND NOT
AND NOT
AND NOT
AND NOT
NOT
Memory or Register Bitbased on a “D Flip-Flop”
Data InData Out
Write
Now Write changes to 1 --- the output changes to 1
1
1
01
1
1
1 1
1 0
1 0
0
1
0
1
0 1
0
1Data out changes to 1Write changes to 1
AND NOT
AND NOT
AND NOT
AND NOT
NOT
Memory or Register Bitbased on a “D Flip-Flop”
Data InData Out
Write
Write changes back to 0 --- the output stays at 1
1
1
00
1
0
1 0
1 0
0 0
1
1
1
1
0 1
0
1Data out stays at 1Write changes to 0
AND NOT
AND NOT
AND NOT
AND NOT
NOT
Memory or Register Bitbased on a “D Flip-Flop”
Data InData Out
Write
Data In also changes back to 0, but the output stays at 1 because Write is still 0.
1
1
00
0
0
0 0
0 1
0 0
1
1
1
1
0 1
0
1Data out stays at 1Data changes to 0
AND NOT
AND NOT
AND NOT
AND NOT
NOT
Memory or Register Bitbased on a “D Flip-Flop”
Data InData Out
Write
When Write changes to 1 --- the output changes to the input 0
0
0
11
0
1
0 0
0 1
1 1
1
0
1
0
1 0
1
0Data changes to 0Write changes to 1
AND NOT
AND NOT
AND NOT
AND NOT
NOT
Memory or Register Bitbased on a “D Flip-Flop”
Data InData Out
Write
Write changes back to 0 --- the output will continue to hold it’s value, whatever it is.
1
0
10
0
0
0 0
0 1
0 0
1
1
1
0
1 0
1
0Data out stays at 0Write changes to 0
AND NOT
AND NOT
AND NOT
AND NOT
NOT
Memory or Register Bitbased on a “D Flip-Flop”
Data InData Out
Write
Even though Data In changes to 1 the output continues to hold it’s previous value.
1
0
10
1
0
1 0
1 0
0 0
1
1
1
0
1 0
1
0Data out stays at 0Data changes to 1
AND NOT
AND NOT
AND NOT
AND NOT
NOT
Memory or Register Bitbased on a “D Flip-Flop”
Data InData Out
Write
If Write stays at zero, these two pairs of AND and NOT gates will always output 1, no matter how the Data In changes. This means the Flip-Flop will hold its previous
value.
1
0
10
1
0
1 0
1 0
0 0
1
1
1
0
1 0
1
0Data Out remains the same.
Write stays at 0
AND NOT
AND NOT
AND NOT
AND NOT
NOT
Memory or Register Bitbased on a “D Flip-Flop”
Data InData Out
Write
This is the Flip-Flop part.As long as the two inputs from the NOT
gates to the left are both 1's, the Flip-Flop will not change it’s output.
1
0
10
1
0
1 0
1 0
0 0
1
1
1
0
1 0
1
0Data Out remains the same.
Write stays at 0
Memory Address Decoding
FETCH CIRCUITRY
INCREMENTOR
EXECUTE CIRCUITRY
ARITHMETIC &LOGIC UNIT
(ALU)
ADDRESS
DECODER
CLOCK
ACCUMULATOR
OPCODE OPERANDADDRESS
JUMPADDRESS
INSTRUCTION REGISTERS
PROGRAM COUNTER
LOAD PROGRAM INSTRUCTION COUNTER REGISTERS EXECUTE CONTROL
OPCODE IN
ACCUMULATORINSTRUCTION REGISTER CONTROL CONTROL ALU CONTROL MEM
OPCODE IN
Address DecoderI n p u t f r o m A d d r e s s B u s
000102
03040506
07
08090A
0B0C0D
0E0F1011
12
131415161718
191A1B1C
1D
1E1F
A d d r e s s B u s
Address DecoderI n p u t f r o m A d d r e s s B u s
000102
03040506
07
08090A
0B0C0D
0E0F1011
12
131415161718
191A1B1C
1D
1E1F
A d d r e s s B u s
1 0 1 1 0
1
1
1
0
0 1
1
1 0
1
1111
1
01 0
11
0
0 1
Bus Control
FETCH CIRCUITRY
INCREMENTOR
EXECUTE CIRCUITRY
ARITHMETIC &LOGIC UNIT
(ALU)
ADDRESS
DECODER
CLOCK
ACCUMULATOR
OPCODE OPERANDADDRESS
JUMPADDRESS
INSTRUCTION REGISTERS
PROGRAM COUNTER
LOAD PROGRAM INSTRUCTION COUNTER REGISTERS EXECUTE CONTROL
OPCODE IN
ACCUMULATORINSTRUCTION REGISTER CONTROL CONTROL ALU CONTROL MEM
OPCODE IN
Bus ControlI n p u t s F r o m B u s
AND AND AND AND AND
Control Line Input
O u t p u t
All output is 0 if Control Line is 0 Identical to Inputs From Bus if Control Line is 1
Bus ControlI n p u t s F r o m B u s
AND AND AND AND AND
Control Line Input
O u t p u t
All output is 0 if Control Line is 0Identical to Inputs From Bus if Control Line is 1
0 1 0 1 1
0
00000
0 00 000 01 11
Bus ControlI n p u t s F r o m B u s
AND AND AND AND AND
Control Line Input
O u t p u t
All output is 0 if Control Line is 0Identical to Inputs From Bus if Control Line is 1
0 1 0 1 1
1
11010
1 10 101 11 11
Incrementor
FETCH CIRCUITRY
INCREMENTOR
EXECUTE CIRCUITRY
ARITHMETIC &LOGIC UNIT
(ALU)
ADDRESS
DECODER
CLOCK
ACCUMULATOR
OPCODE OPERANDADDRESS
JUMPADDRESS
INSTRUCTION REGISTERS
PROGRAM COUNTER
LOAD PROGRAM INSTRUCTION COUNTER REGISTERS EXECUTE CONTROL
OPCODE IN
ACCUMULATORINSTRUCTION REGISTER CONTROL CONTROL ALU CONTROL MEM
OPCODE IN
Incrementor
O u t p u t Input number + 1
Carry out
Left bus into ALU
1
Incrementor
O u t p u t Input number + 1
Carry out
0 0 1 0 10 0 0 0 1
0 0 1 0 1
5
Decimal equivalent
+ 1
0 0 1 1 0 6
+
0 0 1 1 0
0 1 100
0 100
Left bus into ALU
INC opcode
00101 + 00001 5 + 1
1
0
Arithmetic and Logic Unit (ALU)
FETCH CIRCUITRY
INCREMENTOR
EXECUTE CIRCUITRY
ARITHMETIC &LOGIC UNIT
(ALU)
ADDRESS
DECODER
CLOCK
ACCUMULATOR
OPCODE OPERANDADDRESS
JUMPADDRESS
INSTRUCTION REGISTERS
PROGRAM COUNTER
LOAD PROGRAM INSTRUCTION COUNTER REGISTERS EXECUTE CONTROL
OPCODE IN
ACCUMULATORINSTRUCTION REGISTER CONTROL CONTROL ALU CONTROL MEM
OPCODE IN
A L U(Arithmetic and Logic Unit)
Less Than
Greater ThanLess Than or Equal
Not EqualEqual
Control Lines In
Greater Than or Equal
Inverter
Equality
Inequality (Greater Than)
Five Bit Adder
Incrementer
Left bus into ALU Right bus into ALU
ALU Data Bus OutJump Decision Out
SUBADD
Control Lines InINC
Left bus into ALU Right bus into ALU Jump Logic Arithmetic
Activate Five Bit Adder
Turn off left bus to Incrementer crossover
Turn on left bus to Incrementer crossover
ALU - Invertor
Invertor
O u t p u t
twos complement of the input bus
Bus input
1 1 1 1 1
Invertor
O u t p u t
twos complement of the input bus
Bus input
1 1 1 1 1
0 1 0 10
0 0 1 0 1
1 0 1 01
ALU - Five Bit Adder
Five Bit AdderInputs from Left and Right Busses into the ALU
O u t p u t
Accurate addition of two 5-bit binary numbers.
Carry out
Left bus into ALU
Right bus into ALU
Five Bit AdderInputs from Left and Right Busses into the ALU
O u t p u t
Accurate addition of two 5-bit binary numbers.
Carry out
1 0 0 1 00 0 1 1 1
1 0 0 1 0
0 0 1 1 1
1 8
Decimal equivalent
+ 7
1 1 0 0 1 2 5
+
1 1 0 0 1
1 0 0
1
1
11
1
0
0
0
0
11
1 1 000
0
Left bus into ALU
Right bus into ALU
ALU – Equality
EqualityInputs from Left and Right Busses into the ALU
O u t p u t
1 if Left equals Right, 0 otherwise
Left bus into ALU
Right bus into ALU
EqualityInputs from Left and Right Busses into the ALU
O u t p u t
1 if Left equals Right, 0 otherwise
Left bus into ALU
Right bus into ALU
00
0
01 0011
0
00
0
10
1
11
1
01
1
0
01
1
00110
10
1 0 0 1
1
01100 = 00101 12 = 5
0 1 1 0 0
0 0 1 0 1
ALU – Greater Than
Inequality – Left > RightInputs from Left and Right Busses into the ALU
O u t p u t
1 if Left > Right, 0 otherwise
Left bus into ALU
Right bus into ALU
Inequality – Left > RightInputs from Left and Right Busses into the ALU
O u t p u t
1 if Left > Right, 0 otherwise
Left bus into ALU
Right bus into ALU
0 00 0
01
0
0
0 1
1 00 1
111
1 0
0 00 0
010
0 1
1 11 1
001
0 1
0 1
00
0
11
1
01
0
0
0
01
0
00
0
01
0
00
0
00
0
01
000
0
01
0
10
1
01
1
01
1
0
01
1
00110
01100 > 00101 12 > 5
0 1 1 0 0
0 0 1 0 1
1
1
End of ALU
Control CircuitryRing Counter
FETCH CIRCUITRY
INCREMENTOR
EXECUTE CIRCUITRY
ARITHMETIC &LOGIC UNIT
(ALU)
ADDRESS
DECODER
CLOCK
ACCUMULATOR
OPCODE OPERANDADDRESS
JUMPADDRESS
INSTRUCTION REGISTERS
PROGRAM COUNTER
LOAD PROGRAM INSTRUCTION COUNTER REGISTERS EXECUTE CONTROL
OPCODE IN
ACCUMULATORINSTRUCTION REGISTER CONTROL CONTROL ALU CONTROL MEM
OPCODE IN
Ring Counterbased on a “D Flip-Flop” --- other designs are more efficient
Ring Counterbased on a D Flip-Flops
Q
QSET
CLR
D
Clock
Reset
Clock 1
Q
QSET
CLR
D
Clock 2
Q
QSET
CLR
D
Clock 3
Q
QSET
CLR
D
Clock 4
Q
QSET
CLR
D
Clock 5
Q
QSET
CLR
D
Clock 6
Ring Counterbased on a D Flip-Flops
Q
QSET
CLR
D
Clock
Reset
Clock 1
Q
QSET
CLR
D
Clock 2
Q
QSET
CLR
D
Clock 3
Q
QSET
CLR
D
Clock 4
Q
QSET
CLR
D
Clock 5
Q
QSET
CLR
D
Clock 6
1
1 0 0 0 0 0Reset
Ring Counterbased on a D Flip-Flops
Q
QSET
CLR
D
Clock
Reset
Clock 1
Q
QSET
CLR
D
Clock 2
Q
QSET
CLR
D
Clock 3
Q
QSET
CLR
D
Clock 4
Q
QSET
CLR
D
Clock 5
Q
QSET
CLR
D
Clock 6
0
0 1 0 0 0 0
Ring Counterbased on a D Flip-Flops
Q
QSET
CLR
D
Clock
Reset
Clock 1
Q
QSET
CLR
D
Clock 2
Q
QSET
CLR
D
Clock 3
Q
QSET
CLR
D
Clock 4
Q
QSET
CLR
D
Clock 5
Q
QSET
CLR
D
Clock 6
0
0 0 1 0 0 0
Ring Counterbased on a D Flip-Flops
Q
QSET
CLR
D
Clock
Reset
Clock 1
Q
QSET
CLR
D
Clock 2
Q
QSET
CLR
D
Clock 3
Q
QSET
CLR
D
Clock 4
Q
QSET
CLR
D
Clock 5
Q
QSET
CLR
D
Clock 6
0
0 0 0 1 0 0
Ring Counterbased on a D Flip-Flops
Q
QSET
CLR
D
Clock
Reset
Clock 1
Q
QSET
CLR
D
Clock 2
Q
QSET
CLR
D
Clock 3
Q
QSET
CLR
D
Clock 4
Q
QSET
CLR
D
Clock 5
Q
QSET
CLR
D
Clock 6
0
0 0 0 0 1 0
Ring Counterbased on a D Flip-Flops
Q
QSET
CLR
D
Clock
Reset
Clock 1
Q
QSET
CLR
D
Clock 2
Q
QSET
CLR
D
Clock 3
Q
QSET
CLR
D
Clock 4
Q
QSET
CLR
D
Clock 5
Q
QSET
CLR
D
Clock 6
0
0 0 0 0 0 1
Ring Counterbased on a D Flip-Flops
Q
QSET
CLR
D
Clock
Reset
Clock 1
Q
QSET
CLR
D
Clock 2
Q
QSET
CLR
D
Clock 3
Q
QSET
CLR
D
Clock 4
Q
QSET
CLR
D
Clock 5
Q
QSET
CLR
D
Clock 6
0
1 0 0 0 0 0
Control CircuitryFetch
FETCH CIRCUITRY
INCREMENTOR
EXECUTE CIRCUITRY
ARITHMETIC &LOGIC UNIT
(ALU)
ADDRESS
DECODER
CLOCK
ACCUMULATOR
OPCODE OPERANDADDRESS
JUMPADDRESS
INSTRUCTION REGISTERS
PROGRAM COUNTER
LOAD PROGRAM INSTRUCTION COUNTER REGISTERS EXECUTE CONTROL
OPCODE IN
ACCUMULATORINSTRUCTION REGISTER CONTROL CONTROL ALU CONTROL MEM
OPCODE IN
Fetch Circuitry
Opcode Register in bus enable
Operand Register in bus enable
Opcode Register Write
Program Counter Write
Increment Program Counter
Operand Register Write
Jump Register in bus enableJump Register Write
Control Lines OutData Bus to Fetch Circuitry Opcode In bus enable
Program Counter to Incrementor bus enable
Q
QSET
CLR
D
Clock in
Reset
Clock 1
Q
QSET
CLR
D
Clock 2
Q
QSET
CLR
D
Clock 3
Q
QSET
CLR
D
Clock 4
Q
QSET
CLR
D
Clock 5
Q
QSET
CLR
D
Clock 6
Program Counter to Address Bus enable
Detect HALT, INC, and NOT
Detect JMP
Detect all jumps (JMP, JEQ, JNE, JLT, JGE, JGT, JLE)
Fetch Opcode
Fetch Opcode
Increment Program Counter
Fetch Operand Address
Fetch Operand Address
Increment Program Counter
Increment Program Counter
Fetch Jump Address
Fetch Jump Address
Opcode In
If HALT, INC, and NOT, then reset the Ring Counter.
If not JEQ, JNE, JLT, JGE, JGT, or JLE then reset the Ring Counter.
If JMP then fetch the Jump Address otherwise fetch the Operand Addreass. Only JEQ, JNE, JLT,
JGE, JGT, or JLE will make it to here because of the resets at Clock 2 and Clock 4.
Execute out
J
Q
Q
K
SET
CLR
Clock pause during
execute
1
1
Fetch in (from
execute circuitry) Ring Counter
Decode to determine how many additional fetches are needed.
Fetch Circuitry
Opcode Register in bus enable
Operand Register in bus enable
Opcode Register Write
Program Counter Write
Increment Program Counter
Operand Register Write
Jump Register in bus enableJump Register Write
Control Lines OutData Bus to Fetch Circuitry Opcode In bus enable
Program Counter to Incrementor bus enable
Q
QSET
CLR
D
Clock in
Reset
Clock 1
Q
QSET
CLR
D
Clock 2
Q
QSET
CLR
D
Clock 3
Q
QSET
CLR
D
Clock 4
Q
QSET
CLR
D
Clock 5
Q
QSET
CLR
D
Clock 6
Program Counter to Address Bus enable
Detect HALT, INC, and NOT
Detect JMP
Detect all jumps (JMP, JEQ, JNE, JLT, JGE, JGT, JLE)
Fetch Opcode
Fetch Opcode
Increment Program Counter
Fetch Operand Address
Fetch Operand Address
Increment Program Counter
Increment Program Counter
Fetch Jump Address
Fetch Jump Address
Opcode In
If HALT, INC, and NOT, then reset the Ring Counter.
If not JEQ, JNE, JLT, JGE, JGT, or JLE then reset the Ring Counter.
If JMP then fetch the Jump Address otherwise fetch the Operand Addreass. Only JEQ, JNE, JLT,
JGE, JGT, or JLE will make it to here because of the resets at Clock 2 and Clock 4.
Execute out
J
Q
Q
K
SET
CLR
Clock pause during
execute
1
1
Fetch in (from
execute circuitry) Ring Counter
Decode to determine how many additional fetches are needed.
Fetch Circuitry
Opcode Register in bus enable
Operand Register in bus enable
Opcode Register Write
Program Counter Write
Increment Program Counter
Operand Register Write
Jump Register in bus enableJump Register Write
Control Lines OutData Bus to Fetch Circuitry Opcode In bus enable
Program Counter to Incrementor bus enable
Q
QSET
CLR
D
Clock in
Reset
Clock 1
Q
QSET
CLR
D
Clock 2
Q
QSET
CLR
D
Clock 3
Q
QSET
CLR
D
Clock 4
Q
QSET
CLR
D
Clock 5
Q
QSET
CLR
D
Clock 6
Program Counter to Address Bus enable
Detect HALT, INC, and NOT
Detect JMP
Detect all jumps (JMP, JEQ, JNE, JLT, JGE, JGT, JLE)
Fetch Opcode
Fetch Opcode
Increment Program Counter
Fetch Operand Address
Fetch Operand Address
Increment Program Counter
Increment Program Counter
Fetch Jump Address
Fetch Jump Address
Opcode In
If HALT, INC, and NOT, then reset the Ring Counter.
If not JEQ, JNE, JLT, JGE, JGT, or JLE then reset the Ring Counter.
If JMP then fetch the Jump Address otherwise fetch the Operand Addreass. Only JEQ, JNE, JLT,
JGE, JGT, or JLE will make it to here because of the resets at Clock 2 and Clock 4.
Execute out
J
Q
Q
K
SET
CLR
Clock pause during
execute
1
1
Fetch in (from
execute circuitry) Ring Counter
Decode to determine how many additional fetches are needed.
0
10
Fetch Circuitry
Opcode Register in bus enable
Operand Register in bus enable
Opcode Register Write
Program Counter Write
Increment Program Counter
Operand Register Write
Jump Register in bus enableJump Register Write
Control Lines OutData Bus to Fetch Circuitry Opcode In bus enable
Program Counter to Incrementor bus enable
Q
QSET
CLR
D
Clock in
Reset
Clock 1
Q
QSET
CLR
D
Clock 2
Q
QSET
CLR
D
Clock 3
Q
QSET
CLR
D
Clock 4
Q
QSET
CLR
D
Clock 5
Q
QSET
CLR
D
Clock 6
Program Counter to Address Bus enable
Detect HALT, INC, and NOT
Detect JMP
Detect all jumps (JMP, JEQ, JNE, JLT, JGE, JGT, JLE)
Fetch Opcode
Fetch Opcode
Increment Program Counter
Fetch Operand Address
Fetch Operand Address
Increment Program Counter
Increment Program Counter
Fetch Jump Address
Fetch Jump Address
Opcode In
If HALT, INC, and NOT, then reset the Ring Counter.
If not JEQ, JNE, JLT, JGE, JGT, or JLE then reset the Ring Counter.
If JMP then fetch the Jump Address otherwise fetch the Operand Addreass. Only JEQ, JNE, JLT,
JGE, JGT, or JLE will make it to here because of the resets at Clock 2 and Clock 4.
Execute out
J
Q
Q
K
SET
CLR
Clock pause during
execute
1
1
Fetch in (from
execute circuitry) Ring Counter
Decode to determine how many additional fetches are needed.
Fetch Circuitry
Opcode Register in bus enable
Operand Register in bus enable
Opcode Register Write
Program Counter Write
Increment Program Counter
Operand Register Write
Jump Register in bus enableJump Register Write
Control Lines OutData Bus to Fetch Circuitry Opcode In bus enable
Program Counter to Incrementor bus enable
Q
QSET
CLR
D
Clock in
Reset
Clock 1
Q
QSET
CLR
D
Clock 2
Q
QSET
CLR
D
Clock 3
Q
QSET
CLR
D
Clock 4
Q
QSET
CLR
D
Clock 5
Q
QSET
CLR
D
Clock 6
Program Counter to Address Bus enable
Detect HALT, INC, and NOT
Detect JMP
Detect all jumps (JMP, JEQ, JNE, JLT, JGE, JGT, JLE)
Fetch Opcode
Fetch Opcode
Increment Program Counter
Fetch Operand Address
Fetch Operand Address
Increment Program Counter
Increment Program Counter
Fetch Jump Address
Fetch Jump Address
Opcode In
If HALT, INC, and NOT, then reset the Ring Counter.
If not JEQ, JNE, JLT, JGE, JGT, or JLE then reset the Ring Counter.
If JMP then fetch the Jump Address otherwise fetch the Operand Addreass. Only JEQ, JNE, JLT,
JGE, JGT, or JLE will make it to here because of the resets at Clock 2 and Clock 4.
Execute out
J
Q
Q
K
SET
CLR
Clock pause during
execute
1
1
Fetch in (from
execute circuitry) Ring Counter
Decode to determine how many additional fetches are needed.
0 1 0
SUB opcode
0 1 0 1 1
1 1
11
10
001
0
1
10
1
1
1 00
0
0
0
0
0
0
0
00
1
1
0
1
1
Reset
Control CircuitryExecute
FETCH CIRCUITRY
INCREMENTOR
EXECUTE CIRCUITRY
ARITHMETIC &LOGIC UNIT
(ALU)
ADDRESS
DECODER
CLOCK
ACCUMULATOR
OPCODE OPERANDADDRESS
JUMPADDRESS
INSTRUCTION REGISTERS
PROGRAM COUNTER
LOAD PROGRAM INSTRUCTION COUNTER REGISTERS EXECUTE CONTROL
OPCODE IN
ACCUMULATORINSTRUCTION REGISTER CONTROL CONTROL ALU CONTROL MEM
OPCODE IN
Execute Circuitry
HALT - disables clock input (not implemented)
INC
NOTANDOR
XOR
ADD
SUB
JEQ
JMP
JNEJLTJGEJGT
JLE
LOAD
STOROpcode Register out bus enableOperand Register out bus enableJump Address Register out bus enable
Memory Write
ALU ADD enableALU SUB enableALU INC enable
Accumulator out to ALU Left in enableAccumulator out to Data Bus enableAccumulator Write
Control Lines Out
Data Bus to ALU Right in enableData Bus to Accumulator in enable
Opc
ode
Regi
ster
out
bus
ena
ble
Ope
rand
Reg
iste
r out
bus
ena
ble
Mem
ory
Writ
e
ALU
AD
D e
nabl
eAL
U S
UB
enab
leAL
U IN
C en
able
Accu
mul
ator
out
to A
LU L
eft in
ena
ble
Accu
mul
ator
out
to D
ata
Bus
enab
leAc
cum
ulat
or W
rite
Dat
a Bu
s to
ALU
Rig
ht in
ena
ble
Dat
a Bu
s to
Acc
umul
ator
in e
nabl
e
ALU Jump Comparison
Logi
c op
code
s no
t im
plem
ente
d
Opcode bus in
Q
QSET
CLR
D
Clock in
Clock 1
Q
QSET
CLR
D
J
Q
Q
K
SET
CLR
1
1
Execute in (from fetch
circuitry)
Fetch out (to fetch circuitry)
Clock 2
Activate opcode
Decode and
execute opcode
Q
QSET
CLR
D
Clock 3
Third Clock for
AND, SUB, and INC
Reset after two clocks
Program Counter Write
Prog
ram
Cou
nter
Writ
e
Choose output for third clock
Execute Circuitry
HALT - disables clock input (not implemented)
INC
NOTANDOR
XOR
ADD
SUB
JEQ
JMP
JNEJLTJGEJGT
JLE
LOAD
STOROpcode Register out bus enableOperand Register out bus enableJump Address Register out bus enable
Memory Write
ALU ADD enableALU SUB enableALU INC enable
Accumulator out to ALU Left in enableAccumulator out to Data Bus enableAccumulator Write
Control Lines Out
Data Bus to ALU Right in enableData Bus to Accumulator in enable
Opc
ode
Regi
ster
out
bus
ena
ble
Ope
rand
Reg
iste
r out
bus
ena
ble
Mem
ory
Writ
e
ALU
AD
D e
nabl
eAL
U S
UB
enab
leAL
U IN
C en
able
Accu
mul
ator
out
to A
LU L
eft in
ena
ble
Accu
mul
ator
out
to D
ata
Bus
enab
leAc
cum
ulat
or W
rite
Dat
a Bu
s to
ALU
Rig
ht in
ena
ble
Dat
a Bu
s to
Acc
umul
ator
in e
nabl
e
ALU Jump Comparison
Logi
c op
code
s no
t im
plem
ente
d
Opcode bus in
Q
QSET
CLR
D
Clock in
Clock 1
Q
QSET
CLR
D
J
Q
Q
K
SET
CLR
1
1
Execute in (from fetch
circuitry)
Fetch out (to fetch circuitry)
Clock 2
Activate opcode
Decode and
execute opcode
Q
QSET
CLR
D
Clock 3
Third Clock for
AND, SUB, and INC
Reset after two clocks
Program Counter Write
Prog
ram
Cou
nter
Writ
e
Choose output for third clock
0
0
0
0
0
00
0
0
0
1
0
0
Execute Circuitry
HALT - disables clock input (not implemented)
INC
NOTANDOR
XOR
ADD
SUB
JEQ
JMP
JNEJLTJGEJGT
JLE
LOAD
STOROpcode Register out bus enableOperand Register out bus enableJump Address Register out bus enable
Memory Write
ALU ADD enableALU SUB enableALU INC enable
Accumulator out to ALU Left in enableAccumulator out to Data Bus enableAccumulator Write
Control Lines Out
Data Bus to ALU Right in enableData Bus to Accumulator in enable
Opc
ode
Regi
ster
out
bus
ena
ble
Ope
rand
Reg
iste
r out
bus
ena
ble
Mem
ory
Writ
e
ALU
AD
D e
nabl
eAL
U S
UB
enab
leAL
U IN
C en
able
Accu
mul
ator
out
to A
LU L
eft in
ena
ble
Accu
mul
ator
out
to D
ata
Bus
enab
leAc
cum
ulat
or W
rite
Dat
a Bu
s to
ALU
Rig
ht in
ena
ble
Dat
a Bu
s to
Acc
umul
ator
in e
nabl
e
ALU Jump Comparison
Logi
c op
code
s no
t im
plem
ente
d
Q
QSET
CLR
D
Clock in
Clock 1
Q
QSET
CLR
D
J
Q
Q
K
SET
CLR
1
1
Execute in (from fetch
circuitry)
Fetch out (to fetch circuitry)
Clock 2
Activate opcode
Decode and
execute opcode
Q
QSET
CLR
D
Clock 3
Third Clock for
AND, SUB, and INC
Reset after two clocks
Program Counter Write
Prog
ram
Cou
nter
Writ
e
Choose output for third clock
0
0
0
0
1
01
1
0
0
0
0
0
JLT opcode
1 0 1 0 0
Opcode bus in1 0 1 0 0
0
1 0
1
1
01
110 0
00
111
1
1
1
11
01
0
10
10
1
1
0
1
Execute Circuitry
HALT - disables clock input (not implemented)
INC
NOTANDOR
XOR
ADD
SUB
JEQ
JMP
JNEJLTJGEJGT
JLE
LOAD
STOROpcode Register out bus enableOperand Register out bus enableJump Address Register out bus enable
Memory Write
ALU ADD enableALU SUB enableALU INC enable
Accumulator out to ALU Left in enableAccumulator out to Data Bus enableAccumulator Write
Control Lines Out
Data Bus to ALU Right in enableData Bus to Accumulator in enable
Opc
ode
Regi
ster
out
bus
ena
ble
Ope
rand
Reg
iste
r out
bus
ena
ble
Mem
ory
Writ
e
ALU
AD
D e
nabl
eAL
U S
UB
enab
leAL
U IN
C en
able
Accu
mul
ator
out
to A
LU L
eft in
ena
ble
Accu
mul
ator
out
to D
ata
Bus
enab
leAc
cum
ulat
or W
rite
Dat
a Bu
s to
ALU
Rig
ht in
ena
ble
Dat
a Bu
s to
Acc
umul
ator
in e
nabl
e
ALU Jump Comparison
Logi
c op
code
s no
t im
plem
ente
d
Opcode bus in
Q
QSET
CLR
D
Clock in
Clock 1
Q
QSET
CLR
D
J
Q
Q
K
SET
CLR
1
1
Execute in (from fetch
circuitry)
Fetch out (to fetch circuitry)
Clock 2
Activate opcode
Decode and
execute opcode
Q
QSET
CLR
D
Clock 3
Third Clock for
AND, SUB, and INC
Reset after two clocks
Program Counter Write
Prog
ram
Cou
nter
Writ
e
Choose output for third clock
1
0
0
0
0
00
0
0
0
0
0
1
JLT opcode
1 0 1 0 0
1
0 1
1
0
1
11
1
1
1
1
0 1
011
Next Presentation: Execution Sequence, individual clock cycles
End of Presentation
