Memory Interfacing 8255 PPI-37
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BITS Pilani, Pilani Campus
8086
ADO-AD15A16-A19
BHE
WR
RD
M/IO
ALE
8086 Address/Data buses
74LS373
STB
8286Transcei
ver
OE
T
ADDR
DATA
DT/R
MEM I/O
Control
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BITS Pilani, Pilani Campus
Buffered Systems
Address, Data and control bus buffered toprovide sufficiently strong signals to drivemultiple devices.
Unidirectional/bidirectional
A B
C
C
74LS244 74LS245
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BITS Pilani, Pilani Campus
DECODER
Memory location
ADDBus
DATA Bus
Memory Chip
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BITS Pilani, Pilani Campus
8086
ADO-AD15
A16-A19
BHE
WR
RD
M/IO
ALE
8086 Address/Data buses
A0-AN
D0-D7
RD
WR
___K x 8
A0-AN
D0-D7
RD
WR
___Kx 8
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BITS Pilani, Pilani Campus
Interface using 2K Memory chips 8 K bytes of Memory to the 8086 CPU
- Address Space
- No of Memory chips
- Decoding logic
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BITS Pilani, Pilani Campus
A19 A18A17A16A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1 A0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000H
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 00001H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 00002H0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 00003H
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 00FFEH
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 00FFFH
4K (2K+2K)
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BITS Pilani, Pilani Campus
ADDRESS DATA
TYPE BHE A0
BUS
CYCLES
DATA
LINES
USED
00000
00000
00001
00001
BYTE
WORD
BYTE
WORD
1
0
0
0
1
0
0
1
1
0
ONE
ONE
ONE
FIRST
SECOND
D0-D7
D0-D15
D8-D15
D8-D15
D0-D7
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BITS Pilani, Pilani Campus
A19 A18A17A16A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1 A0
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 01000H
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 01001H 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 01002H0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 01003H
0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 01FFEH
0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 01FFFH
4K (2K+2K) Total 8K
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BITS Pilani, Pilani Campus
A0-A10A1-A11of CPU
CSRemainingAdd linesOf CPU
ADDDecodingLogic
Data BusOf CPU
WR
RD
MEMW
MEMR
A0-A10
CS
WR
RD
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BITS Pilani, Pilani Campus
RD
WR
M/IO
MEMR
MEMW
IOR
IOW
LOGICCIRCUIT
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BITS Pilani, Pilani Campus
Ex: Interface 1M of SRAM to 8086. Chips available are of size 256K each.
A19 A18………………………………………………………A1 A0
0 0 ……………………………………………………… 0 0
0 1 ……………………………………………………….1 1
1 0 ……………………………………………………….0 0
1 1 ……………………………………………………….1 1
512KB
512KB
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BITS Pilani, Pilani Campus
A1
A18
A0
A17
256K
A1
A18
A0
A17
256K
A
B
C74138
A19
GND
GNDBHE
VCC
CS
01 A
B
C74138
GND
GNDA0
VCC
01A19
CS
D15-D8D7-D0
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BITS Pilani, Pilani Campus
Ex: Interface 4K of ROM to 8086 starting at 80000H. Chips available are 2716.
A19 A18………………………A11 A10……………………A1 A0
1 0 ………………………..0….0……………………… 0 0
1 0 ………………………..1….1……………………….1 1
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BITS Pilani, Pilani Campus
Ex: Interface 16K of ROM to 8086 starting at 80000H. Chips available are 1KB each.
A19 A18………………………A11 A10……………………A1 A0
1 0 ………………………..0….0……………………… 0 0
1 0 ………………………..0….1……………………… 1 1
1 0 ………………………..1….0……………………… 0 0
1 0 ………………………..1….1……………………….1 1
2KB
2KB
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BITS Pilani, Pilani Campus
Ex: Interface 8K of RAM to 8086 starting at 00000H. Chips available are 1KB(4 Chips) and 2KB (2 Chips).
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BITS Pilani, Pilani Campus
Ex: Interface
4K 2716 (ROM) starting at 00000H
8K 6116 (SRAM) starting at 08000H
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BITS Pilani, Pilani Campus
Input Device:
Ex: Switch
R
VCC
S1 A
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BITS Pilani, Pilani Campus
R
VCC
S1
BUFFER
E
I O
From Add Decoding Logic
To data linesOf CPU
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BITS Pilani, Pilani Campus
IN AL, 00H
ROR AL, 1
JC SWITCH OPEN
I/O MAPPED I/O
MOV AL, [0000H]
ROR AL, 1
JC SWITCH OPEN
MEMORY MAPPED I/O
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BITS Pilani, Pilani Campus
Output Device
Ex: LED
RA
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BITS Pilani, Pilani Campus
RLATCH
E
I
FromCPUDataline
From AddDecoding logic
O
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BITS Pilani, Pilani Campus
MOV AL, 01H
OUT 00H, AL
To turn the LED on
To turn the LED OFF
MOV AL, 00H
OUT 00H, AL
Add DecodingLogic
I/O Mapped I/O
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BITS Pilani, Pilani Campus
Interfacing input devices like switchesrequire buffers
Interfacing output devices like LEDsrequire latches.
Programmable Peripheral Interface ( PPI)provide these features.
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BITS Pilani, Pilani Campus
8255
- Three 8 bit ports Port A, Port B, Port C
- Can act as output port / input port
- 8 bit data bus
- 8 bit control register used to program 8255
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BITS Pilani, Pilani Campus
PORT APA0-PA7
PORT BPB0-PB7
PORT CPC0-PC7
CONTROLREG
D0
D7
CS
A0
A1
RD
WR
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BITS Pilani, Pilani Campus
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BITS Pilani, Pilani Campus
8255 Can Operate in Different Modes
- I/O Modes
MODE 0 - Simple I/O Mode
MODE 1 - Hand shaked I/O Mode
MODE 2 - Bi-directional I/O
- BSR ( Bit Set Reset) Mode
Port A can operate in Modes 0,1,2Port B can operate in Modes 0,1Port C can operate in Mode0, BSR mode
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BITS Pilani, Pilani Campus
Port C divided into Port C0-PC3 lower port & PC4- PC7 upper port
Port A and Port C Upper grouped – Group A
Port B and Port C lower grouped - Group B
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BITS Pilani, Pilani Campus
Programming is done by writing a control word in control register.
D7 D6 D5 D4 D3 D2 D1 D0
Control Word
A1A0 - 11 Control RegisterA1A0 - 00 Port A
A1A0 - 01 Port B
A1A0 - 10 Port C
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Control Register
• There are two groups of control blocks in the 8255A control register
D7 D6 D5 D4 D3 D2 D1 D0
Mode Set Flag0 - bit set/reset1 – I/O mode
Group A Mode00 - mode 001 - mode 11x - mode 2
PORT A0 - output1 - input
PORT C (upper)0 - output1 - input
Group B Mode0 - mode 01 - mode 1
PORT B0 - output1 - input
PORT C (lower)0 - output1 - input
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BITS Pilani, Pilani Campus
Write the Initialization routine to initialize 8255 as per the following specifications:
Port A- Input Port – Mode 0
Port B- Output Port - Mode 0
Port Cupper – Input Port - Mode 0
Port C lower – Output Port – Mode 0
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BITS Pilani, Pilani Campus
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BITS Pilani, Pilani Campus
vcc
OUT VCC
OUTPORT
IN PORT
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BITS Pilani, Pilani Campus
7447
SS S S
VCC VCC VCC VCC
CC C C
PORT
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BITS Pilani, Pilani Campus
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BITS Pilani, Pilani Campus
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BITS Pilani, Pilani Campus
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BITS Pilani, Pilani Campus
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BITS Pilani, Pilani Campus
Interfacing Analog to Digital Converter
D0
D7
Vin
Start
EOC
8-bit ADC
AD 570
To start conversionsend 2S active highpulse at start
Conversion time
20 S EOC = 1indicates
end of conversion
Vref
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BITS Pilani, Pilani Campus
Interfacing Analog to Digital Converter
D0
D7
I0
I7
Start
EOC
8-bit ADC
ADC 0809
ALE
ABC
OE’