AN-1363APPLICATION NOTE

One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com

Meeting Biasing Requirements of Externally Biased RF/Microwave Amplifiers with

Active Bias Controllers by Kagan Kaya

Rev. 0 | Page 1 of 16

INTRODUCTION Radio frequency (RF) and microwave amplifiers provide their best performance under specific bias conditions. The quiescent current established by the bias point affects critical performance metrics such as linearity and efficiency. While some amplifiers are self biased, many devices require external biasing using multiple supplies that must be sequenced properly for safe operation.

This application note provides an overview of bias sequencing requirements and the effects of using various bias conditions. It presents an elegant solution for biasing amplifiers using active bias controller such as the HMC980, HMC980LP4E, HMC981, HMC981LP3E, HMC920LP5E, and all externally biased RF/microwave amplifiers.

AN-1363 Application Note

Rev. 0 | Page 2 of 16

TABLE OF CONTENTS Introduction ...................................................................................... 1

Revision History ............................................................................... 2

Biased Amplifiers .............................................................................. 3

Power Supply Sequencing ........................................................... 3

Self Biased Amplifiers .................................................................. 3

Externally Biased Amplifiers ...................................................... 3

Cascode Amplifiers ...................................................................... 5

Using Active Bias Controllers to Bias Externally Biased Amplifiers ...................................................................................... 6

Operating Principles .....................................................................8

Adjusting the Default VNEG and VGATE Threshold Values .9

Reducing VGATE Rise Time .................................................... 10

Daisy-Chain Configuration ...................................................... 11

Testing the Functionality of the Active Bias Controller ........ 12

Biasing Multiple DUTs by a Single Active Bias Controller ... 12

Sample Active Bias Controler Application Circuits ............... 12

Conclusion....................................................................................... 16

REVISION HISTORY 7/2016—Revision 0: Initial Version

Application Note AN-1363

Rev. 0 | Page 3 of 16

BIASED AMPLIFIERS POWER SUPPLY SEQUENCING Power supply sequencing is critical while operating externally biased amplifiers for the following reasons:

Failing to follow the proper power supply sequencing compromises the reliability of the device. Exceeding breakdown voltage levels can result in instant failure. Long term reliability degrades when out of bond conditions are repeated multiple times, and the system is stressed. In addition, continually violating the sequencing pattern damages the on-chip protection circuitry and results in long term damage, which can result in a failure in the field operation.

Optimizing the bias level not only during power up and power down but also during regular operation can improve the performance of the RF amplifier, depending on the configuration and the application requirements. For some applications, changes can be made to the RF performance of the amplifier to comply with different field scenarios. For example, the output power can be increased for wider coverage during rainy weather, or the output power can be reduced during clear weather. The external gate control of the amplifier can implement these arrangements.

Analog Devices, Inc., has a wide selection of RF amplifier types. Many RF amplifiers are based on a depletion mode, pseudo-morphic, high electron mobility transfer (pHEMT) technology. The transistors used in this process typically require supplies for the drain pins and gate pins. This quiescent drain current is a function of the gate voltage. See Figure 1 for the typical IV characteristics of a typical field effect transistor (FET) process.

700

0

100

200

300

400

500

600

0 2 4 6 8 10 12

I DS

(A

)

VDS (V)

VGS = 0V

VGS = –2V

131

64-

00

1

Figure 1. Typical IV Characteristics of a Typical FET Process

As the gate to source voltage (VGS) increases, more electrons enter the channel, resulting in a higher drain to source current (IDS).

Additionally, as the drain to source voltage (VDS) increases, the drain to source current also increases (in the linear region) due to the higher field force pulling the electrons.

In real-world amplifiers, due to effects like channel length modulation, these amplifiers can be broadly categorized into two categories: self biased and externally biased amplifiers.

SELF BIASED AMPLIFIERS Self biased amplifiers have an internal circuit that sets the optimal bias point suitable for operation. These amplifiers tend to be best suited for broadband, low powered applications. See Figure 2 for a typical pinout of a self biased amplifier.

12

11

10

1

3

4 9

2

65 7 8

16 15 14 13

PACKAGEBASE

GND

GND

RFIN

GND

GND

VD

D3

NIC

VD

D2

VD

D1

GND

RFOUT

GND

GNDNIC

NIC

NIC

NIC

131

64-0

02

Figure 2. Typical Pinout for a Multistage Self Biased Amplifier with Multiple

Bias Pins

While self biased amplifiers are simple to use, they may not provide the best performance because the internal resistive bias circuit cannot fully compensate for lot, device, and temperature variations.

EXTERNALLY BIASED AMPLIFIERS Externally biased amplifiers tend to provide higher performance than self biased amplifiers under specific bias conditions. The quiescent drain current of the amplifier affects parameters such as power compression point, gain, noise figure, intermodulation products, and efficiency. For these high performance externally biased amplifiers, correctly sequencing the supplies is crucial for safe and optimal performance.

This procedure also applies to other radio frequency integrated circuits (RFICs), such as frequency multipliers, upconverters, and downconverters. These products can require similar biasing techniques. Table 1 lists externally biased RF products from various product families.

Table 1. Externally Biased RF Devices Device Number Product Family HMC1082LP4E Driver amplifier/medium power amplifier HMC1049 Bare Die Low noise amplifier HMC7357LP5GE Power amplifier HMC463 Wideband distributed amplifier HMC996LP4E Variable gain amplifier HMC598 Frequency multiplier chip HMC1065LP4E Downconverter HMC6787ALC5A Upconverter HMC871LC5 Optical modulator driver

AN-1363 Application Note

Rev. 0 | Page 4 of 16

Figure 3 shows the typical connections for the pins of an externally biased amplifier and the corresponding transistor pins. The pin mapping in Figure 3 is a simplified representation of the amplifier.

GATE

DRAIN

SOURCE

PACKAGEBASE

GND

9

8

7

1

2

3

GND

RFOUT

GND

GND

RFIN

GND

4N

IC

5V

GG

6N

IC

12N

C

11V

DD

10N

IC

131

64-

005

Figure 3. Typical Connections of an Externally Biased Amplifier

Furthermore, many externally biased amplifiers have multiple stages to meet design requirements such as gain, bandwidth, and power. Figure 4 shows a typical block diagram of the HMC1131, which is a multistage externally biased amplifier.

PACKAGEBASE

GND

13

1

3

4

2

7

NIC

GND

RFIN

GND

5

6

NIC

NIC NIC

14 NIC

15 GND

16

1.5kΩ

1.5kΩ

RFOUT

17 GND

18 NIC

NIC

8V

GG

1

9N

IC

10N

IC

11V

GG

2

1219

NIC

NIC

20V

DD

4

21V

DD

3

22V

DD

2

23V

DD

1

24N

IC

13

164

-00

8

Figure 4. HMC1131 Multistage Externally Biased Amplifier

HMC1131 Biasing and Sequencing Requirements

The HMC1131 is a gallium arsenide (GaAs), pHEMT, monolithic microwave integrated circuit (MMIC), medium power amplifier. It operates from 24 GHz to 35 GHz. The 4-stage design typically provides a 22 dB gain, 23 dBm output power for 1 dB compression (P1dB), and 27 dBm saturated output power (PSAT) under the bias conditions of VDD = 5 V and IDQ = 225 mA, where VDD is the drain bias voltage and IDQ is the quiescent drain current. The electrical specifications table of the HMC1131 data sheet, for the 24 GHz to 27 GHz frequency range, gives this information. Figure 4 shows the pin connections of the HMC1131.

To achieve a target quiescent drain current (IDQ) of 225 mA, set the voltage of the gate bias pins (VGG1 and VGG2) between 0 V and −2 V. To set that negative voltage without damaging the amplifier, follow the recommended biasing sequence during power up and power down.

The recommended bias sequence during power up for the HMC1131 is the following:

1. Connect to ground. 2. Set VGG1 and VGG2 to −2 V. 3. Set VDD1 through VDD4, the drain voltage bias pins, to 5 V. 4. Increase VGG1 and VGG2 to achieve an IDQ of 225 mA. 5. Apply the RF signal

The recommended bias sequence during power down for the HMC1131 is the following:

1. Turn the RF signal off. 2. Decrease VGG1 and VGG2 to −2 V to achieve an IDQ of

approximately 0 mA. 3. Decrease VDD1 through VDD4 to 0 V. 4. Increase VGG1 and VGG2 to 0 V.

When the gate voltage (VGGx) is −2 V, the transistors are pinched off. Therefore, IDQ is typically close to zero.

In general, the recommended biasing sequence is similar for most externally biased amplifiers. IDQ, VDDx, and VGGx values are different for different devices. For GaAs devices, VGG is generally set to −2 V or −3 V to turn off the amplifier, while that voltage can be −5 V to −8 V for gallium nitride (GaN) amplifiers. Similarly, VDDx can reach 28 V, even 50 V, for GaN devices, while it is usually less than 13 V for GaAs amplifiers.

In general, for multistage amplifiers, the VGG pins are connected and biased together. By following the same procedure, a user can get the typical performance results provided on the data sheet. Operating the amplifier under different bias conditions may provide different performance. For instance, using a different VGGx level for the HMC1131 gate bias pins to obtain various IDQ values changes the RF and dc performance of the amplifier.

Application Note AN-1363

Rev. 0 | Page 5 of 16

Figure 5 shows the P1dB vs. the frequency at various supply currents, and Figure 6 shows the output third order intercept (IP3) performance vs. the frequency at various supply currents for the HMC1131.

30

12

14

16

18

20

22

24

26

28

24 25 27 29 31 33 3526 28 30 32 34 36

P1d

B (

dB

m)

FREQUENCY (GHz)

250mA225mA200mA175mA

131

64-0

09

Figure 5. P1dB vs. Frequency at Various Supply Currents

40

20

22

24

26

28

30

32

34

36

38

24 25 27 29 31 33 3526 28 30 32 34 36

OU

TP

UT

IP

3 (d

Bm

)

FREQUENCY (GHz)

250mA225mA200mA175mA

131

64-0

10

Figure 6. Output IP3 vs. Frequency at Various Supply Currents,

POUT/Tone = 10 dBm

Another option for biasing amplifiers with multiple VGGx pins is to control the gate bias pins independently. This operation mode helps users customize device performance by optimizing specific parameters such as P1dB, IP3, NF, gain, and power consumption.

This flexibility is useful for some applications. If the performance data of an amplifier provided on the data sheet meets some requirements of the application easily, yet misses others by a small margin, testing the performance under different bias conditions can be advantageous without exceeding the absolute maximum ratings given in the data sheet.

Another option for biasing externally biased amplifiers, is setting VGGx for the desired IDQ of 225 mA and using a constant gate voltage during normal operation. In this case, the IDD of the amplifier increases under the RF drive. This behavior is shown in the power compression at 30.5 GHz in the HMC1131 data sheet (see the orange line). The performance of the amplifier with constant gate voltage and with constant IDD can be different.

CASCODE AMPLIFIERS Analog Devices wideband distributed amplifiers often use a cascode architecture to extend the frequency range. The cascode distributed amplifier uses a fundamental cell of two FETs in series, source to drain. This fundamental cell is then duplicated a number of times. This duplication increases the operation bandwidth. Figure 7 shows a simplified schematic for a fundamental cell.

VDD

VGG2

VGG1

RFIN

RFOUT

131

64-

011

Figure 7. Simplified Fundamental Cascode Cell Schematic

With some exceptions, the cascode wideband amplifiers are externally biased.

The HMC637A is a wideband amplifier that uses cascode topology. The HMC637A is a GaAs, MMIC, metal semiconductor field effect transistor (MESFET) distributed power amplifier that operates between dc and 6 GHz. Figure 8 shows the pin connections for the HMC637A.

17

1

34

2

9

NICVGG2

NIC

NIC56

RFINNIC

7NIC8NIC NIC

18 NIC19 NIC20 NIC21 RFOUT/VDD

22 NIC23 NIC24 NIC

NIC

12N

IC11

NIC

10N

IC

13V

GG

114

NIC

15A

CG

416

AC

G3

25N

IC26

NIC

27N

IC28

NIC

29A

CG

230

AC

G1

31N

IC32

NIC

PACKAGEBASE

GND

131

64-0

12

Figure 8. HMC637A Pin Connections

The amplifier provides 14 dB of gain, 43 dBm of output IP3, and 30.5 dBm of output power at a 1 dB gain compression under the bias conditions of VDD = 12 V, VGG2 = 6 V, and IDQ = 400 mA. The electrical specifications table of the HMC637A data sheet provides this information.

AN-1363 Application Note

Rev. 0 | Page 6 of 16

To achieve the recommended quiescent drain current of 400 mA, VGG1 must be somewhere between 0 to −2 V. To set the desired negative voltage, follow the recommended bias sequence during power up and power down.

The recommended bias sequence for the HMC637A during power up follows:

1. Connect to ground. 2. Set VGG1 to −2 V. 3. Set VDD to 12 V. 4. Set VGG2 to 6 V (VGG2 can be obtained by a resistive divider

from VDD). 5. Increase VGG1 to achieve a typical quiescent current (IDQ) of

400 mA. 6. Apply the RF signal.

The recommended bias sequence for the HMC637A during power down follows:

1. Turn off the RF signal. 2. Decrease VGG1 to −2 V to achieve IDQ = 0 mA. 3. Decrease VGG2 to 0 V. 4. Decrease VDD to 0 V. 5. Increase VGG1 to 0 V.

USING ACTIVE BIAS CONTROLLERS TO BIAS EXTERNALLY BIASED AMPLIFIERS There are two major approaches for biasing externally biased amplifiers:

Constant gate voltage approach. In this approach, the gate voltage value is varied to achieve the desired IDQ value. This gate voltage value is then kept constant during operation, which typically results in a variable drain current (IDD) under the RF drive.

Constant IDD approach. In this approach, the gate voltage value is varied to achieve the desired IDQ value, then the IDD value of the amplifier is monitored, and the gate voltage value is adjusted constantly to have the same IDD value for different RF drive levels. Active bias controllers keep the IDD of the device under test (DUT) constant.

Another approach, a subset of the constant IDD approach, consists of following the constant IDD approach and switching in between multiple constant IDD levels when necessary due to various field scenarios. For instance, a user can bias a power amplifier stage of a transmitter for high current levels during rainy weather to compensate for the additional rain attenuation. Similarly, a user can bias the same power amplifier for low current levels during clear weather to reduce the power consumption.

In general, Analog Devices RF amplifiers are characterized with a constant gat voltage approach, using bench top power supply units. Therefore, biasing those amplifiers with the constant IDD approach can result in different RF performance than what is given on the amplifier data sheet.

Designing bias circuits for amplifiers to keep the drain current constant and provide necessary sequencing can be cumbersome. Such control circuits are complicated and require not only multiple external components such as low drop out regulators (LDOs), charge pumps, voltage sequencing, and protection circuits, but also calibration cycles. Such implementations occupy a large printed circuit board (PCB) area that is usually much larger than the amplifier itself.

The HMC920LP5E houses all the necessary operation blocks in a compact 5 mm × 5 mm plastic surface-mount technology (SMT) package. By eliminating multiple IC and external component requirements, this compact size results in reduced PCB area compared to the discrete biasing implementations.

Similar to the HMC920LP5E, active bias controllers require less PCB space than discrete transistor solutions. When using the HMC980LP4E, bias sequencing, constant gate voltage adjustment, short-circuit protection, and negative voltage generation features are implemented within 10 mm × 15 mm of PCB space.

The HMC981LP3E, HMC980LP4E, and HMC920LP5E are 3 mm × 3 mm, 4 mm × 4 mm, and 5 mm × 5 mm plastic packaged active bias controllers, respectively. Figure 9 shows the PCB area required for a typical application, including external passive components.

HMC981LP3E HMC980LP4E HMC920LP5E

ACTUAL AREA REQUIREDIN TYPICAL APPLICATION

13

164-

01

4

Figure 9. PCB Area Required in Typical Application

The Analog Devices active bias controller family offers some key advantages:

Internal negative voltage generators generate the negative voltage at the VGATE pin required for externally biased amplifiers. These generators eliminate the need for voltage inverters and reduce the device count, the PCB space, and, as a result, the system cost.

Continuous internal gate voltage adjustment ensures a constant DUT drain current.

Bias accuracy improves due to the reduction of device to device variation effects. The optimum gate voltage level required to obtain a desired IDD for different amplifiers with the same device number is different due to device to device variation. Therefore, setting the gate voltage to the same value for separate DUTs results in a different RF performance. Active bias controllers adjust the gate voltage level separately for each individual DUT and reduce the performance difference introduced by device to device variation.

Application Note AN-1363

Rev. 0 | Page 7 of 16

Figure 10 and Figure 11 show this reduction on device to device variation effects.

125

95

100

105

110

115

120

1 2SN1 SN6SN5SN4SN3SN2 3 4 5 6 7

BIA

S C

UR

RE

NT

(m

A)

SAMPLES

+85°C+25°C–40°C

131

64-0

15

Figure 10. Bias Current Variation of a Typical Amplifier Under Fixed External

VGATE Bias

125

95

100

105

110

115

120

1 2SN1 SN6SN5SN4SN3SN2 3 4 5 6 7

BIA

S C

UR

RE

NT

(m

A)

SAMPLES

+85°C+25°C–40°C

131

64-0

16

Figure 11. Improved Bias Current Variation of Same Amplifier when Biased

with the HMC920LP5E

Internal bias sequencing circuitry ensures that positive voltages on the VDRAIN pin and the VG2 pin are not supplied to the DUT when the negative VGATE voltage is not present. This feature eliminates the external components used for sequencing during DUT power up and power down.

Short-circuit protection circuitry disables the VDRAIN pin after the VGATE pin and therefore makes sure that the DUT is safe, even under short circuit conditions.

AN-1363 Application Note

Rev. 0 | Page 8 of 16

CONTROLBLOCK

NEGATIVEVOLTAGE GENERATOR

GATECONTROL

BAND GAP

1

3

4

2

5

6

18C9

10nF

C3100pF

C44.7µF

C710µF

VDD

R35.1kΩ

R43.3kΩ

C61µF

C510nF

NIC

R101kΩ

R134.7kΩ

C210nF

R12301Ω

R1410kΩ

R11301Ω

C82.2µF

16

15

17

14

13

7 9 108 11 12

24 22 2123 20 19

C14.7µF

GNDTP12

VDD

VDRAINTP10

TRIG OUTTP11

VGATETP9

VG2TP8

VDDTP1GNDTP2S0

TP3S1

TP4ENTP5ALMTP6

VDIGTP7

131

64-0

17

HMC980LP4E

Figure 12. Typical Application Circuit for the HMC980LP4E

Table 2. Selected Features of Active Bias Controllers

Device Number

Supply Range (V) VDRAIN (V) IDRAIN (mA) IGATE (mA)

Over/Under Current Alarm

Short-Circuit Protection VDRAIN LDO

Negative Voltage Generator

HMC920LP5E 5 to 16.5 3 to 15 0 to 500 −4 to +4 Yes Yes Yes Yes HMC980LP4E 5 to 16.5 5 to 16.5 50 to 1600 −4 to +4 Yes Yes No Yes HMC981LP3E 4 to 12 4 to 12 20 to 200 −0.8 to +0.8 No Yes No Yes With an internal feedback, the automatic gate voltage control achieves a constant quiescent bias current through the amplifier under bias, independent of the temperature and amplifier threshold variations. The quiescent bias current is adjusted with a resistor connected externally. Figure 12 shows the RSENSE resistor (R10) connected to Pin 20 of the HMC980LP4E.

Further details on how to calculate the RSENSE and VDD values can be found on the active bias controller data sheets.

Analog Devices offers three active bias controllers: the HMC920LP5E, HMC980LP4E, and HMC981LP3E. Table 2 details selected features of these active bias controllers.

The HMC980LP4E provides the ability to source high drain currents, while the HMC981LP3E is best suited for devices that require lower drain currents. In addition to the negative voltage generator, the HMC920LP5E integrates a positive voltage regulator, providing the ability to source drain pins.

OPERATING PRINCIPLES For externally biased amplifiers, Analog Devices data sheets highlight the biasing requirements for VGG and IDD at the bottom of electrical specifications table. For instance, the HMC637A requires its VGG1 to be adjusted from −2 V to 0 V to obtain a typical IDQ of 400 mA. However, follow the recommended sequencing during power-up and power-down to avoid damaging the HMC637A.

The HMC980LP4E employs an integrated control circuitry to manage safe power-up and power-down sequencing of the targeted amplifier.

During power up, the VDD and VDIG supplies of the bias controller turn on, and then VNEG generates by the internal negative voltage generator (NVG). VNEG starts to decrease and stops when it reaches its default value (typically −2.46 V). The VGATE output voltage also starts to decrease. Typically, once VNEG = −2.5 V and VGATE = −2.1 V are reached, the VDRAIN output is enabled, and VGATE begins to increase toward 0 V to obtain the desired IDD value for the DUT.

Application Note AN-1363

Rev. 0 | Page 9 of 16

Similar power-down protection circuitry also provides a safe power down for the DUT. During power down, VGATE always shuts down after VDD, even if there is a short circuit on the VDD pins or on the VGG pins of the DUT. This feature introduces advanced protection of the DUT, under excessive DUT IDD current scenarios.

8

–4

–2

0

2

4

6

0 10 3020 40 50

VO

LT

AG

E (

V)

TIME (ms)

VDDVDRAINVDIGVG2VNEGVGATE

131

64-0

18

Figure 13. HMC981LP3E Enabling Sequence for Supply Rails

ADJUSTING THE DEFAULT VNEG AND VGATE THRESHOLD VALUES The typical VNEG value is −2.46 V, as seen in Figure 14. Due to the internal logic that exists inside HMC980LP4E, this default value limits the VGATE output voltage swing capabilities of the HMC980LP4E.

8

–4

–2

0

2

4

6

0 10 3020 40 50

VO

LT

AG

E (

V)

TIME (ms)

VDDVDRAINVDIGVG2VNEGVGATE

131

64-0

19

Figure 14. Default VNEG Value

With the default configuration, the typical VGATE output swing is in between −2 V and 0 V. However,

For some DUTs, gate voltages of less than −2 V are necessary. Some DUTs have a gate voltage absolute maximum rating

(AMR) that is greater than −2.1 V, such as −1.5 V. In such a case, the DUT is expected to have a typical gate voltage higher than the AMR value of VGATE, such as −1 V. During the power up, however, the VGATE output of the HMC980LP4E always reduces to a typical value of −2 V.

Adjusting the default values of VNEG and VGATE by external resistors solves both of these problems. The R5, R6, R7, and R8 resistors shown in Figure 15 are used for this purpose.

C610µF

C51µF

C14.7µF

C210nF

C34.7µF

C410nF

C310nF

1

3

4

2

5

6

18 IDRAINVDRAIN

VDRAIN

VDRAIN

R10

TRIGOUTR10 = 150Ω/IDRAINVDD = VDRAIN + IDRAIN × RDS_ON

R134.7kΩ

R12301Ω

R1410kΩ

R11301Ω

VGATER7 R8

R5 R6

VGATE

VNEG

16

15

17

14

13

7CP

VD

D

CP

OU

T

VD

IG

VR

EF

VN

EG

FB

VG

AT

EF

B

9 108 11 12

24 22 2123 20 19

ISE

NS

E

TR

IGO

UT

VDD5.28V

EN

VDD

VDD

S0

S1

EN

D1 DUAL SCHOTTKY

VDIG3.3V TO 5V

VDIG

GND

GND

HMC980LP4E

131

64-0

20

Figure 15. External Resistors for Adjusting Default VNEG and VGATE Values

AN-1363 Application Note

Rev. 0 | Page 10 of 16

If the desired VNEG < −2.46 V, then R5 (kΩ) = open, and R6 (kΩ) = 50/(50 × (Desired VNEG − 0.815)/(262 × (0.815 − 1.44)) − 1).

If the desired VNEG > −2.46 V, then R5 (kΩ) = 262/(262 × (1.44 − 0.815)/(50 × (0.815 − Desired VNEG)) − 1), and R6 (kΩ) = open.

If the desired VGATE < −2.46 V, then R7 (kΩ) = open, and R8 (kΩ) = 50/(50 × (Desired VGATE − 0.815)/(262 × (0.815 − 1.44)) − 1).

If the desired VGATE > −2.46 V, then R7 (kΩ) = 262/(262 × (1.44 − 0.815)/(50 × (0.815 – Desired VGATE)) − 1), and R8 (kΩ) = open.

During power up, VNEG is enabled if VNEG reaches a default value of −2.46 V; therefore, the VNEG value must be less than the VGATE value.

It is recommended to configure the HMC980LP4E for VNEG values greater than −3.5 V.

For example, if the desired VNEG = −1.5 V and VGATE = −1.3 V, R5 = 631 kΩ, R7 = 477 kΩ, and R6 = R8 = open. In addition, if the desired VNEG = −3.2 V and VGATE = −3 V, R6 = 221 kΩ, R8 = 303 kΩ, and R5 = R7 = open.

REDUCING VGATE RISE TIME A delay exists between the moment that the enable signal reaches the enable pin of the active bias controller and the moment that the VGATE voltage level at the DUT VGATE input pin settles to the desired value. This delay is due to the combination of the internal propagation delay of the bias controller and the settling time of the VGATE signal. The VGATE settling time is affected by the shunt capacitors used on the connection between the active bias controller VGATE output and the DUT VGATE input pin. The HMC980LP4E typical enable waveform (see Figure 16) shows a VGATE settling time greater than 1 ms.

16

–12

–8

–4

0

4

8

12

0 1 32 4 5 6

VO

LT

AG

E (

V)

TIME (ms)

EN (V)VDRAIN (V)VG2 (V)VNEG (V)VGATE (V)

131

64-0

21

Figure 16. HMC980LP4E Typical Enable Waveform

The external circuit affects the gate rise time but not the propagation delay. Figure 17 shows a typical VGATE connection between the HMC980LP4E and a DUT amplifier. Generally, the shunt capacitor, C1, is used on the VGG pins of the amplifiers, where R1 is usually 0 Ω, that is, not used.

1

3

4

2

5

6

18

VDD

VGG

VDD

VDD

ALM

EN

S1

S0

VDRAIN

VDRAIN

VG2_CONT

VG2

VNEG

VGATE

RFIN RFOUT16

15

17

14

13

7C

PV

DD

CP

OU

T

VD

IG

VR

EF

VN

EG

FB

VG

AT

EF

B

FIX

BIA

S

AL

MH

ISE

T

AL

ML

ISE

NS

E

TR

IGO

UT

9 108 11 12

24 22 2123 20 19

HMC980LP4EDUT

R1

C1

131

64-

022

Figure 17. VGATE Connection Circuitry Between the HMC980LP4E and the DUT

When C1 = 10 μF, the typical rise time is greater than 1.5 ms (see Figure 18). Reducing C1 to 1 μF reduces the rise time to 131 μs (see Figure 19).

CH1 500mV

CH3

CH2 M2.030ms A CH4 1.46VT 1.000ms

1

4

T

FALL (2): NO SIGNALRISE (2): NO SIGNALRISE (1): 1.62ms

13

164

-02

3

Figure 18. Typical VGATE Rise Time with C1 = 10 μF

CH1 500mV

CH3

CH2

CH4 1.00V

M324.0ms A CH4 1.46VT 100.0ms

1

4

FALL (2): NO SIGNALRISE (2): NO SIGNALRISE (1): 131µs

PROPAGATIONDELAY

T

13

164

-02

4

Figure 19. Typical VGATE Rise Time with C1 = 1 μF

Application Note AN-1363

Rev. 0 | Page 11 of 16

When C1 = 100 nF, the VGATE rise time is reduced to 15.5 μs, but overshooting introduces ringing (see Figure 20). Adding a series resistor, R1, with a value of 68 Ω to C1 = 100 nF improves the response and keeps the rise time within a similar level (see Figure 21).

CH1 500mV

CH3

CH2

CH4 1.00V

M176.0ms A CH4 1.46VT 50.0ms

1

4

MEASURE

RISE (1):

CURRENT

15.5µs

MEAN

27.900µs

MIN

15.5µs

COUNT

5

MAX

76.0µs

STD DEV

26.890µs

T

13

164

-02

5

Figure 20. Typical VGATE Rise Time with C1 = 100 nF

CH1 500mV

CH3

CH2

CH4 1.00V

M149.5ms A CH4 1.46VT 50.0ms

1

4

MEASURE

RISE (1):

CURRENT

11.5µs

MEAN

11.500µs

MIN

11.5µs

COUNT

1

MAX

11.5µs

STD DEV

0.0s

T

13

164

-02

6

Figure 21. Typical VGATE Rise Time with C1 = 100 nF and R1 = 68 Ω

DAISY-CHAIN CONFIGURATION When multiple active bias controllers bias multiple DUTs, they can be used in a daisy-chain configuration. The TRIGOUT output of the active bias controller generates when the VDRAIN, VG2, and VGATE outputs settle. Using the TRIGOUT signal to enable another bias controller with the enable pin (EN) improves the system safety level. A daisy-chain configuration has many applications, Figure 22 and Figure 23 show two applications. The number of DUT stages and bias controllers can be increased.

VDD

VGG

RFIN RFOUT

TRIGOUTENACTIVE BIASCONTROLLER

ACTIVE BIASCONTROLLER

DUT

VDD

VGG

RFIN RFOUTDUT

131

64-0

27

Figure 22. Daisy-Chain Configuration with Two Amplifiers in Cascade

Configuration

VDD

VGGVDD VGG

RF

– LO

IF

TRIGOUT ENENACTIVE BIASCONTROLLER

ACTIVE BIASCONTROLLER

DUT

DUT

131

64-

028

Figure 23. Daisy-Chain Configuration Where DUT Amplifiers Are on Different

Signal Paths

Figure 24 shows the VDRAINx and VGATEx responses of two active bias controllers in a daisy-chain configuration, powering two DUTs individually. The second bias controller enables by the trigger signal sourced from the first bias controller. This architecture ensures that the second DUT enables after the first DUT.

CH1 5.00V

CH3 2.00V

CH2 5.00V

CH4 2.00V

M2.245ms A CH1 1.31VT 500.0ms

2

3

EN1 EN2/TRGOUT1

VDRAIN1

VDRAIN2

T

13

164

-02

9

Figure 24. VDRAINx Responses of Two Active Bias Controllers in a Daisy-

Chain Configuration, Powering Two DUTs Individually

CH1 5.00V

CH3 1.00V

CH2 5.00V

CH4 1.00V

M2.245ms A CH1 1.31VT 500.0ms

2

3

EN1 EN2/TRGOUT1

VGATE1

VGATE2

T

13

164

-03

0

Figure 25. VGATEx Responses of Two Active Bias Controllers in a Daisy-Chain

Configuration, Powering Two DUTs Individually

AN-1363 Application Note

Rev. 0 | Page 12 of 16

TESTING THE FUNCTIONALITY OF THE ACTIVE BIAS CONTROLLER The VDRAIN and VGATE outputs of active bias controllers can bias a DUT, such as an FET or an amplifier with external biasing requirements. Once the DUT is connected to the bias controller, the feedback loop is closed and the bias controller becomes operational.

Because the loop does not close, it is not feasible to test the functionality of an active bias controller with a fixed load, like a resistor.

Although testing active bas controllers without a DUT does not provide useful information, perform the following diagnostic checks.

IDD = 0 mA results in a negligible voltage drop across the VDD input and VDRAIN output; therefore, VDRAIN is almost equal to VDD.

VNEG is typically −2.46 V. VGATE hits a maximum value of VNEG + 4.5 V, which is

typically 2.04 V.

For other bias controllers, these values can be extracted from their data sheets.

BIASING MULTIPLE DUTS BY A SINGLE ACTIVE BIAS CONTROLLER It is possible to bias two or more DUTs by a single active bias controller. To do so, calculate the RSENSE value considering the total drain current of the DUTs.

Note, however, that using this approach limits the benefits that an active bias controller offers for the following reasons:

An active bias controller is not able to compensate device-to-device gate voltage variation that is common with GaAs devices. As a result, two devices can be biased using one gate voltage, resulting in nonoptimal performance.

If one of the DUTs draws excessive current due to a short circuit or other terms of failure, the bias controller shuts down all DUTs under bias. Although this does not damage the devices, it compromises system functionality.

SAMPLE ACTIVE BIAS CONTROLER APPLICATION CIRCUITS Biasing the HMC460LC5 with the HMC981LP3E

To bias the HMC460LC5 with the HMC981LP3E, do the following:

Set R10 to 426 Ω to set IDD = 75 mA for the HMC981LP3E. A common resistor value of 430 Ω can be used.

Calculate a VDD value of 8.75 V. Use R4 and R6 to ensure that the VGATE voltage is within

the Absolute Maximum Ratings section of the HMC981LP3E data sheet. Refer to the Adjusting the Default VNEG and VGATE Threshold Values section for details.

The shunt VGG capacitor values can be reduced to increase the rise time (see HMC460LC5 in Figure 26). Refer to the Reducing VGATE Rise Time section for further details.

C14.7µF

GND

C210nF

4.7µF 1nF

100nF

2.2µF 1nF

10nF 100pF

C34.7µF

C410nF

R41.6MΩ

R61.6MΩ

C610µF

1

3

4

2

5 RFIN

GND

RFOUT

GND

6

7

8

24

22

21

23

20

19

18

17

9 11 1210 13 14 15 16

32V

DD

30A

CG

1

VG

G

AC

G2

2931 28 27 26 25

HMC460LC51

3

4

2

VDD

VG2CONT

SW

EN

12

10

9

11

VDRAIN

VGATE

VG2

VNEG VNEG = –2V

VR

EF

ISE

NS

E

DIS

BL

SC

TR

IGO

UT

16 14 1315

VD

IG

CP

OU

T

VG

AT

EF

B

VN

EG

FB

5 7 86

HMC981LP3E

R10426Ω

R10 = 32 / IDRAIN (0.075A) = 426ΩVDD = VDRAIN (8V) + IDRAIN (0.075A) × RDS_ON (10Ω) = 8.75V

VDIG3.3V TO 5V

D1 DUAL SCHOTTKY

131

64-0

31

Figure 26. Application Circuit for Biasing the HMC460LC5 with the HMC981LP3E

Application Note AN-1363

Rev. 0 | Page 13 of 16

Biasing the HMC1082LP4E with the HMC980LP4E

To bias the HMC1082LP4E with the HMC980LP4E, do the following:

Set R10 to 680 Ω to set IDD = 220 mA for the HMC980LP4E Calculate a VDD value of 5.62 V.

Use R5 and R7 to ensure that the VGATE voltage is within the Absolute Maximum Ratings section of the HMC980LP4E data sheet. Refer to the Adjusting the Default VNEG and VGATE Threshold Values section for details.

The shunt VGG capacitor values can be reduced to increase the rise time (see HMC1082LP4E in Figure 27). Refer to the Reducing VGATE Rise Time section for further details.

R10680Ω

TRIGOUT

2.2µF 1nF 100pF

2.2µF

2.5kΩ

RFIN RFOUT

2.5kΩ

C14.7µF

VDD5.62V

GND

GND

C210nF

C3100pF

C410nF

C34.7µF

C610µF

C51µF

R51.6MΩ

VN

EG

= 2

.0V

1

R1410kΩ

3

4

5

6

2

18

16

15

14

13

17

VDD

VDD

S0

S1

ENEN

ALM

VDRAIN

VDRAIN

VGATE

VNEG

VG2

VG2_CONT

FIX

BIA

S

AL

ML

ISE

NS

E

AL

ML

ISE

T

TR

IGO

UT

CP

VD

D

CP

OU

T

VD

IG

VR

EF

VN

EG

FB

VG

AT

EF

B

24 22 21 20 1923

7 9 10 11 128

HMC980LP4E

R10 = 150Ω/IDRAIN (0.22A) = 680ΩVDD = VDRAIN (5V) + IDRAIN (0.220A) × RDS_ON (2.8Ω) = 5.62V

VDIG3.3V TO 5V

D1 DUAL SCHOTTKY

1

3

4

5

6

2

18

16

15

14

13

17

24V

DD

1

VD

D2

VG

G

VD

D3

22 21 20 1923

7 9 10 11 128

HMC1082LP4E

GND

R71.6MΩ

VGATE

100pF

IDRAIN =220mA

VDRAIN = 5V

5kΩ

1nF

100pF

1nF

100pF

1nF

13

164

-03

2

Figure 27. Application Circuit for Biasing the HMC1082LP4E with the HMC980LP4E

AN-1363 Application Note

Rev. 0 | Page 14 of 16

Biasing the HMC659LC5 with the HMC980LP4E

To bias the HMC659LC5 with the HMC980LP4E, do the following:

Set R10 to 500 Ω to set IDD = 300 mA for the HMC980LP4E. Use a common resistor value of 510 Ω. Calculate a VDD value of 8.84 V. Use R3 and R4 to set VGG2 for the HMC980LP4E.

Use R5 and R7 to ensure that the VGATE voltage is within the Absolute Maximum Ratings section of the HMC980LP4E data sheet. Refer to the Adjusting the Default VNEG and VGATE Threshold Values section for further details.

The shunt VGGx capacitors value can be reduced to increase the rise time (see HMC659LC5 in Figure 28). Refer to the Reducing VGATE Rise Time section for further details.

2.2µF

100n

F

100nF

10nF 0.47µF

R10500Ω

TRIGOUT

C14.7µF

VDD8.84V

GND

GND

C210nF

C3100pF

C410nF

C34.7µF

C610µF

R35kΩ

R44.74kΩ

C51µF

R51.6MΩ

1

R1410kΩ

3

4

5

6

2

18

16

15

14

13

17

VDD

VDD

S0

S1

EN

ENALM

VDRAIN

VDRAIN

VGATE

VNEG

VG2

VG2_CONT

FIX

BIA

S

AL

ML

ISE

NS

E

AL

ML

ISE

T

TR

IGO

UT

CP

VD

D

CP

OU

T

VD

IG

VR

EF

VN

EG

FB

VG

AT

EF

B

24 22 21 20 1923

7 9 10 11 128

HMC980LP4E

R10 = 150ΩIDRAIN (0.3A) = 500ΩVDD = VDRAIN (8V) + IDRAIN (0.3A) × RDS_ON (2.8Ω) = 8.84V

VDIG3.3V TO 5V

D1 DUAL SCHOTTKY

VDD

R71.6MΩ

VGATE

IDRAIN =300mA

VDRAIN = 8V

R134.7kΩ

R12301Ω

R11301Ω

1

3

4

2

5 RFIN

VGG2

VG

G1

RFOUT/VDD

6

7

8

24

22

21

23

20

19

18

179 11 1210 13 14 15 16

32 30 2931 28 27 26 25

HMC659LC5

0.47µF 10nF

13

164

-03

3

Figure 28. Application Circuit for Biasing the HMC659LC5 with the HMC980LP4E

Application Note AN-1363

Rev. 0 | Page 15 of 16

Biasing the HMC659LC5 with the HMC920LP5E

To bias the HMC659LC5 with the HMC920LP5E, do the following:

Set RSENSE to 549 Ω to set IDD = 300 mA for the HMC920LP5E. Set R8 to 30.9 kΩ to set VDRAIN = 8 V.

Use R20 and R22 to ensure that the VGATE voltage is within the Absolute Maximum Ratings section of the HMC920LP5E data sheet. Refer to the Adjusting the Default VNEG and VGATE Threshold Values section for details.

The shunt VGGx capacitor values can be reduced to increase the rise time (see HMC659LC5 in Figure 29). Refer to the Reducing VGATE Rise Time section for further details.

C2110µF

C22100nF

10nF 0.47µF

C14.7µF

VDD9V TO 16.5V

VDD

C210nF

C510µF

RESR > 0.2Ω

C11µF

C910µF

R510kΩ

R155kΩ

C24100pF

R830.9kΩ

R2710kΩ

C20

100n

F

C610µF

R221.6MΩ

VN

EG

= 2

.0V

C130.33µF

D1 DUAL SCHOTTKY

IDRAIN =300mA

VDRAIN = 8V

1

3

4

2

5 RFIN

VGG2

VG

G1

RFOUT/VDD

6

7

8

24

22

21

23

20

19

18

17

9 11 1210 13 14 15 16

32 30 2931 28 27 26 25

HMC659LC51

3

4

2

5

VDD1

VDD1

VDIG

PORCAP

TRGOUT

VDRAIN

VDRAIN

VGATE

VGATEFB

VNEGIN

VNEGFB

AGND

BGCAP

BGC

EN

CURALM

AL

MT

RIG

AL

MS

ET

AG

ND

FIX

BIA

S

VR

EF

VD

D2

CP

OU

T

DG

ND

VD

DC

HK

VD

DA

LM

LD

OF

B

LD

OC

C

AL

MH

AL

MM

AL

ML

ISE

NS

E

6

7

8

24

22

21

23

20

19

18

17

11 12109 13 14 15 16

32 30 2931 28 27 26 25

HMC920LP5E

0.47µF 10nF

RSENSE549Ω

C144.7µF

R201.6MΩ

16kΩ

10kΩ100nF

131

64-

034

Figure 29. Application Circuit for Biasing the HMC659LC5 with the HMC920LP5E

AN-1363 Application Note

Rev. 0 | Page 16 of 16

CONCLUSION Follow the recommended biasing sequence for externally biased devices during power-up and power-down to ensure the safety of the device. Operating amplifiers with an active bias controller ensures that the device is sequenced properly and at the desired level, improving overall system performance.

The active bias controller family from Analog Devices can address the biasing requirements of externally biased RF/ microwave components, such as FETs, amplifiers, multipliers, optical modulator drivers, and frequency converters. The gate voltages of the DUTs are adjusted with a closed feedback loop for the desired drain current. The sequencing feature of the VGATE, VDRAIN, and VGG2 outputs of the bias controller during power up and power down ensures that the DUT is protected.

©2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. AN13164-0-7/16(0)