ME3 Block Diagram Intel CPU Project code : 91.4X601.001...

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title

Size Document Number Rev

Date: Sheet of

Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.

ME3-Discrete SA

Block DiagramA3

1 51Monday, July 30, 2007

Prepare by Steven CF Chou

Title


Date: Sheet of


ME3-Discrete SA

Block DiagramA3



Title


Date: Sheet of


ME3-Discrete SA

Block DiagramA3



RealtekPCI-E x 1

24

25

ME3 Block Diagram

DDRII

Slot 0

DDRII

Slot 1

RTL8101E

10/100 ControllerRJ45 CONN

TV OUT

CRT

LCD 16

15

15

HDMI 17

26Camera

26RF

28USB X 4

RealtekRTL5158 27

26

27

Finger print

USB 2.0 MS/MS Pro/xD/MMC/SD 4 in 1

W25X80-VSSFlash Rom

32

SLB9635TTTPM

32.768KHz

32.768KHz

3233

CAPACITYBUTTON

31

33 33

32

KBCWPC8763Winbond

INT.KB

TouchPad

LPC BUSDEBUGCONN.

LPC

SPI

DDRII 667 Channel A

DDRII 667 Channel B

22G792

27MHz

32.768KHz

HDD CDROME-SATA

SATA

303029

PATASATA

28

34

AZALIA

35

35

AMP

Codec

Line In

MDC Card

G1432AMP

AZALIA

MODEM

G1412

INT.SPKR

Line Out(SPDIF)

RJ11

INT. MIC ArrayDigital

13,14

13,14

Power Switch23

23

23 PCI-E x 1

PCI-E x 2802.11a/b/g/nMini Card_1

New card G577

ALC662

EEPROM 46

26Blue toothor

23RobsonMini Card_2

Host BUS533/667MHz

Intel CPU

4,5,6

Meron 2M/4M SVFSB:667 or 800 MHz

DMI I/F100MHz

7,8,9,10,11,12

18,19,20,21

Crestline-GM/GMLAGTL+ CPU I/FINTEGRATED GRAHPICS

DDR I/F

LVDS, CRT I/F

ICH8-M10 USB 2.0/1.1 ports

(10/100/1000Mb)ETHERNET

ATA 66/100High Definition Audio

ACPI 1.1LPC I/F

INTEL

PCI/PCI BRIDGE

44,45,46

nVIDIANB8M-GS

PCIE x 16

REALTEK RTM875

CLK GEN

3

Project code : 91.4X601.001PCB P/N :Revision :

MAX8736ETL

OUTPUTS

1D8V_S3

3V_S5

1D05V_S0

OUTPUTS

5V_S3

MAX8743

PCB LAYER

SYSTEM DC/DC

GNDVCC

Signal 3Signal 2

Signal 1

INPUTS

GNDL3:

DCBATOUT

DCBATOUT

L2:

L5:

TPS51120

L4:

L6:

INPUTS

L1:

SYSTEM DC/DC

5V 100mA

OUTPUTS

OUTPUTS

BT+

0.844~1.3V 44A

18V 3.0A

VCC_CORE

INPUTS

DCBATOUT

MAXIM CHARGER

INPUTS

CPU DC/DC

MAX8725

DCBATOUT

OUTPUTSVGA_CORE_S0

FAN5234SYSTEM DC/DC

INPUTS

DCBATOUT

GNDSignal 5

Signal 5Signal 4L7:

L9:L8:

L10:

11A

GDDR3Graphics RAM256-Mbit

47,48

E-SATACONN

28SIL3531

CodecALC268HDMI

(SPDIF)

Mic In

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

Title


Date: Sheet of


ME3-DiscreteTable of Content

A3

2 51Friday, September 14, 2007

Title


Date: Sheet of



A3


Title


Date: Sheet of



A3


★CFG 8

★CFG 9

Only PCIE or SDVO is operation

PCIE and SDVO areoperation simultaneous

CFG 19★

CFG 12

CFG 20

CFG 13

★

★

Lane Reversal Normal Mode(Lanesnumber in order)

★

XOR/ALL-ZLL(00)LH(01)HL(10)HH(11)

ReservedXOR Mode EnabledAll Z Mode EnabledNormal Operation

CFG 16

DMI X 2 DMI X 4

CFG Strap HIGH 1LOW 0

FSB Dynamic ODT Disabled Enabled

DMI Lane Reserved Normal Operation Reserved Lane

CFG 5

Low Power PCI Express Normal Low Power mode

Concurrent SDVO/PCIE

PCI Express GraphicsLane Reversal

INTEL CRESTLINE STRAP PIN

SDVO_CTRL_DATASDVO Present

NO SDVO CardPresent

SDVO Card Present★

This signal should not be pull low unless using XOR Chain testing.

XOR Chain Entrance.Rising Edge of PWROK.

No Reboot.Rising Edge of PWROK.

This signal has weak internal pull-up. set bit27 of MPC.LR(Device28:Function0:Offset D8)

PCIE LAN REVERSAL.RisingEdge of PWROK.

If sampled high, the system is strapped to the "No Reboot" mode(ICH8M will disable the TCO Timersystem reboot feature). The status is readable via the NO REBOOT bit.(Offset:3410h:bit5)

This should only be used in manufacturingenvironments

Internal Pull-Up.If sampled low,the Flash DescriptorSecurity will be overidden.if high,the Securitymeasures defined in the Flash Descriptor will be ineffect.

Reserved

Sets bit2 of RPC.PC(Config Registers:Offset 224h)

LAN100_SLPEnables integrated VccLAN1_05,VccCL1_05 VRMwhen sampled high

Integrated VccLAN1_05 VccCL1_05 VRM enable /Disable. Always sampled.

High=No Reboot LOW = DefauleSPKR

No Reboot Strap

XOR Chain Entrance Strap

010

AZ_DOUT_ICHICH_RSVD Description

111 00

Set PCIE port cofig bit1Normal Operation(default)

Enter XOR ChainRSVD

11 01

SPI_CS#1BOOT BIOS Strap

A16 swap override strap

low = A16 swap override enable high = default

PCI_GNT#3

PCI_GNT#0 BOOT BIOS Location

SPI10PCILPC(Default)

INTEL ICH8-M STRAP PIN

DEFAULE HIGH

tp3

8.2K PULL HIGH

High=Enable Low=Disable

LAN100_SLP

SM_INTVRMEN

integrated VccLan1_05VccCL1_05

integrated VccSus1_05,VccSus1_5,VccCL1_5

High=Enable Low=Disable

Flash Descriptor SecurityOverride StrapRising Edge of PWROK.

GPIO33/ HDA_DOCK_EN#

Weak Internal PULL-DOWN.NOTE:This signal shouldnot be pull HIGH.

PCIE Port Config 2 bit0,Rising Edge of PWROK.

SATALED#

INTVRMEN

TP3

SPKR

GNT0# SPI_CS1#

Top-Block Swap Override.Rising Edge of PWROK.

Sets bit0 of RPC.PC(Config Registers:Offset 224h)

GNT2#

Controllable via Boot BIOS Destination bit(Config Registers:Offset 3410h:bit 11:10).GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC.

Boot BIOS Destination Selection.Rising Edge of PWROK.

GNT3#

HDA_SYNC

HDA_SDOUT XOR Chain Entrance/PCIE Port Config 1 bit1,Rising Edge of PWROK

Sampled low:Top-Block Swap mode(inverts A16 for allcycles targeting FWH BIOS space).Note: Software will not be able to clear the Top-Swap bit until the system is rebooted without GNT3# being pulled down.

Signal Usage/When Sampled

GPIO20

PCIE Port Config 1 bit0,Rising Edge of PWROK.

Allows entrance to XOR Chain testing when TP3pulled low at rising edge of PWROK.When TP3 notpulled low at rising edge of PWROK,sets bit1 ofRPC.PC(Config Registers:offset 224h)

Comment

Enables integrated VccSus1_05,VccSus1_5 andVccCL1_5 VRM when sampled high

Integrated VccSus1_05 VccSus1_5 and VccCL1_5 VRM Enable/Disable.Alwayssampled.

INTEL ICH8-M INTEGRATEDPULL-UPS and PULL-DOWNS

SIGNAL Resistor Type/ValueHDA_BIT_CLK

HDA_RST#

HDA_SDIN[3:0]

HDA_SDOUT

HDA_SYNC

GNT[3:0]

GPIO[20]

LDA[3:0]#/FHW[3:0]#

LDRQ[0]

PME#

PWRBTN#

SATALED#

LAN_RXD[2:0]

LDRQ[1]/GPIO23

TP[3]

SPKR

SPI_CLK

SPI_CS1#

USB[9:0][P,N]

CL_RST#

SPI_MOSI

SPI_MISO

TACH_[3:0]

NONE

PULL-DOWN 20K

PULL-DOWN 15K

TBD

PULL-UP 20K

PULL-UP 20K

PULL-UP 20K

PULL-UP 20K

PULL-UP 20K

PULL-UP 20K

PULL-UP 20K

PULL-UP 20K

PULL-UP 20K

PULL-UP 20K

PULL-UP 20K

PULL-UP 20K

PULL-UP 20K

PULL-UP 20K

PULL-DOWN 20K

PULL-DOWN 20K

PULL-DOWN 20K

PULL-DOWN 20K

PULL-DOWN 20K

U45 : 71.0NB8M.00U (VGA)U35: 71.00662.00G (Audio)U28: 71.08763.B0G (KBC)U74: 71.08101.B0G (LAN)U26: 71.ICH8M.C0U (SB)U18: 71.PM965.A0U (NB)TV1: 22.10021.H21Hole,SpringHDMI1: 22.10296.011

MB: 07230LED: 07537FP: 07546Audio: 07545USB: 07547

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CPU_BCLK#

CPU_XDP

FSB

CPU_XDP#

FSA

PCI2_TME

PCIE_NEWPCIE_NEW#

PCIE_ICHPCIE_ICH#

MCH_3GPLLMCH_3GPLL#

PCIE_MINI2PCIE_MINI2#

FSC

CLK_XTAL_OUTCLK_XTAL_IN

27_SEL

CLK_XTAL_IN

CPU_BCLK

27_SEL

MCH_BCLKMCH_BCLK#

ITP_EN

FSB

FSA

CLK_XTAL_OUT

FSCITP_EN

PCIE_MINI1PCIE_MINI1#

PCIE_LAN#PCIE_LAN

PCIE_SATA#PCIE_SATA

PCI2_TME

REFCLKPREFCLKN

27MHZSS27MHZ

3D3V_S0

3D3V_S0 3D3V_S0_CK505

1D25V_S0_CK505_IO

3D3V_S0_CK505

3D3V_S0_CK505

3D3V_S0_CK505

3D3V_S0_CK505

1D25V_S0

1D25V_S0_CK505_IO

3D3V_S0

CLK_CPU_BCLK 4CLK_CPU_BCLK# 4

CLK_MCH_BCLK# 7CLK_MCH_BCLK 7

NEWCARD_CLKREQ# 23

CLK_48M_ICH20

H_STP_PCI#20H_STP_CPU#20

ICH_SMBCLK13,14,20ICH_SMBDATA13,14,20

CK_PWRGD20

CLKSATAREQ#20CLKREQ#_B7

CLK_PCI_TCG32PCLK_KBC31CLK_PCI_ICH18

CLK_14M_ICH20

CPU_BSEL25

CPU_BSEL15

CPU_BSEL05

MCH_CLKSEL0 7

MCH_CLKSEL1 7

MCH_CLKSEL2 7

CLK_PCIE_NEW# 23CLK_PCIE_NEW 23

CLK_PCIE_ICH# 20CLK_PCIE_ICH 20

CLK_MCH_3GPLL# 7CLK_MCH_3GPLL 7

CLK_PCIE_MINI2# 23CLK_PCIE_MINI2 23

CLK_PCIE_MINI1# 23CLK_PCIE_MINI1 23

PCLK_FWH32

PEG_REFCLKP 45PEG_REFCLKN 45

VGA_27MHZ 47VGA_27MHZSS 47

CLK_PCIE_SATA# 19CLK_PCIE_SATA 19

CLK_PCIE_LAN 24CLK_PCIE_LAN# 24

CLK_PCIE_ESATA# 29CLK_PCIE_ESATA 29

Title


Date: Sheet of


ME3-DiscreteClock generator CY28548

A3

3 51Tuesday, August 21, 2007

Title


Date: Sheet of



A3


Title


Date: Sheet of



A3


FS_C FS_B FS_A CPU

1 0 1 100M 0 0 1 133M 0 1 0 200M 0 1 1 166M

27_SEL PIN 20 PIN 21 PIN 24 PIN 25

0 DOT96T DOT96C SRCT1/LCDT_100 SRCT1/LCDT_100 1 SRCT0 SRCC0 27M_NSS 27M_SS

ITP_EN Output

0 SRC81 CPU_ITP

Design Note:

1. All of Input pin didn't have internal pull up resistor.2. Clock Request (CR) function are enable by registers.3. CY28548 integrated serial resistor of differential clock, so put 0 ohm serial resistor in the schematic.

SB

12

R14610KR2J-3-GPDYR14610KR2J-3-GPDY

1 2R354

0R3-0-U-GP

DY

R354

0R3-0-U-GP

DY

12

C30

3SC

4D7P

50V2

CN

-1G

PC

303

SC4D

7P50

V2C

N-1

GP

12 3

4

RN32

SRN0J-6-GP

RN32

SRN0J-6-GP

1 2

C607 SC4D7P50V2CN-1GPC607 SC4D7P50V2CN-1GP

1 2L15

MLB-160808-18-GP

L15

MLB-160808-18-GP

12 3

4

RN39

SRN0J-6-GP

RN39

SRN0J-6-GP

12 3

4RN40

SRN0J-6-GP

RN40

SRN0J-6-GP1

2

C60

6SC

4D7P

50V2

CN

-1G

PC

606

SC4D

7P50

V2C

N-1

GP

12

C597

SCD

1U16V2ZY-2G

P

C597

SCD

1U16V2ZY-2G

P

1 2R342 0R0402-PADR342 0R0402-PAD

12

C605

SCD

1U16V2ZY-2G

P

DYC605

SCD

1U16V2ZY-2G

P

DY

12

C618

SCD

1U16V2ZY-2G

P

C618

SCD

1U16V2ZY-2G

P

12 3

4

RN41

SRN0J-6-GP

RN41

SRN0J-6-GP

12

C598

SCD

1U16V2ZY-2G

P

DYC598

SCD

1U16V2ZY-2G

P

DY

12 3

4

RN43

SRN0J-6-GP

RN43

SRN0J-6-GP

1 2R138 1KR2J-1-GPR138 1KR2J-1-GP

12

C619

SCD

1U16V2ZY-2G

P

C619

SCD

1U16V2ZY-2G

P

12

C300

SC1U

10V3KX-3GP

C300

SC1U

10V3KX-3GP

12 3

4

RN31SRN0J-6-GP

RN31SRN0J-6-GP

12

C601

SCD

1U16V2ZY-2G

P

C601

SCD

1U16V2ZY-2G

P

12 3

4RN45 SRN0J-6-GPRN45 SRN0J-6-GP

12

R34110KR2J-3-GPDYR34110KR2J-3-GPDY

12 3

4

RN44

SRN0J-6-GP

RN44

SRN0J-6-GP

1 2R340 33R2J-2-GPR340 33R2J-2-GP

12 3

4

RN37

SRN0J-6-GP

RN37

SRN0J-6-GP

12

R14510KR2J-3-GPR14510KR2J-3-GP

1 2L18

MLB-160808-18-GP

L18

MLB-160808-18-GP 12

C610

SCD

1U16V2ZY-2G

P

C610

SCD

1U16V2ZY-2G

P

12

C30

2SC

4D7P

50V2

CN

-1G

PC

302

SC4D

7P50

V2C

N-1

GP

1 2X2

X-14D31818M-36GP

X2

X-14D31818M-36GP

12 3

4

RN36

SRN0J-6-GP

RN36

SRN0J-6-GP12

C337

SC10U

10V5ZY-1GP

C337

SC10U

10V5ZY-1GP

12

C603

SCD

1U16V2ZY-2G

P

DYC603

SCD

1U16V2ZY-2G

P

DY

12


12

C341

SC10U

10V5ZY-1GP

C341

SC10U

10V5ZY-1GP

12

C30

1SC

4D7P

50V2

CN

-1G

PC

301

SC4D

7P50

V2C

N-1

GP

1 2R149 33R2J-2-GPR149 33R2J-2-GP

12


1 2R334 1KR2J-1-GPR334 1KR2J-1-GP

12

C596

SCD

1U16V2ZY-2G

P

C596

SCD

1U16V2ZY-2G

P

GN

D_R

EF

1

XOUT2XIN3

VD

D_R

EF

4

FSLC/TEST_SEL/REF5

SDATA6SCLK7

CR#_A/PCI-08

VD

D_P

CI

9

CR#_B/PCI-110TME/PCI-211SRC-5_EN/PCI-31227M_SEL/PCI-413ITP_EN/PCIF-514

GN

D_P

CI

15V

DD

_48

16

FSLA/USB4817

GN

D_4

818

VD

D_I

O19

SRC-0/DOT96 20SRC-0#/DOT96# 21

GN

D_I

O22

VD

D_P

LL3

23

SRC-1/SE1 24SRC-1#/SE2 25

GN

D_P

LL3

26V

DD

_PLL

3_IO

27

SRC-2/SATA 28SRC-2#/SATA# 29

GN

D_S

RC

30

CR#_C/SRC-3 31CR#_D/SRC-3# 32

VD

D_S

RC

_IO

33

SRC-4 34SRC-4# 35

GN

D_S

RC

36

SRC-9 37SRC-9# 38

CR#_G/SRC-11# 39CR#_H/SRC-11 40

SRC-10 41SRC-10# 42

VD

D_S

RC

_IO

43

CPU_STOP#/SRC-5#44PCI_STOP#/SRC-545

VD

D_S

RC

46

SRC-6# 47SRC-6 48

GN

D_S

RC

49

SRC-7#/CR#_E 50SRC-7/CR#_F 51

VD

D_S

RC

_IO

52

SRC-8#/CPU_ITP# 53SRC-8/CPU_ITP 54

RESET#55

VD

D_C

PU

_IO

56

CPU-1# 57CPU-1 58

GN

D_C

PU

59

CPU-0# 60CPU-0 61V

DD

_CP

U62

CK_PWRGD/PD#63

FSLB/TEST_MODE64

GN

D65

U24

RTM875-606-LF-GP

U24

RTM875-606-LF-GP

1 2R16910KR2J-3-GP

DYR16910KR2J-3-GP

DY

12

C343

SC1U

10V3KX-3GP

C343

SC1U

10V3KX-3GP

1 2R155 33R2J-2-GPR155 33R2J-2-GP

1 2R153 33R2J-2-GPR153 33R2J-2-GP

12

C599

SCD

1U16V2ZY-2G

P

C599

SCD

1U16V2ZY-2G

P

12 3

4

RN33SRN33J-5-GP-U

RN33SRN33J-5-GP-U

12

C322

SC33P50V2JN-3GP

C322

SC33P50V2JN-3GP

12

C321

SC33P50V2JN-3GP

C321

SC33P50V2JN-3GP

1 2R335 1KR2J-1-GPR335 1KR2J-1-GP

12 3

4

RN29

SRN0J-6-GP

RN29

SRN0J-6-GP

1 2

R338 33R2J-2-GPR338 33R2J-2-GP

1 2R339 10KR2J-3-GPR339 10KR2J-3-GP

12

C330

SC10U

10V5ZY-1GP

C330

SC10U

10V5ZY-1GP

1 2R154 33R2J-2-GPR154 33R2J-2-GP

12

R33610KR2J-3-GP

DYR33610KR2J-3-GP

DY

1 2R163 2K2R2J-2-GPR163 2K2R2J-2-GP

1 2R367 10KR2J-3-GPR367 10KR2J-3-GP

12

C611

SCD

1U16V2ZY-2G

P

C611

SCD

1U16V2ZY-2G

P

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CPU_PROCHOT#

H_A#17

H_ADSTB#1

H_A#32

H_THERMTRIP#

H_THERMDAH_THERMDC

H_IERR#

CPU_RSVD05

CPU_RSVD01

CPU_RSVD03CPU_RSVD02

CPU_RSVD04

CPU_RSVD06CPU_RSVD07CPU_RSVD08CPU_RSVD09CPU_RSVD10

CPU_RSVD11

H_RESET#

H_INIT#

H_RS#0

H_LOCK#

H_RS#1H_RS#2H_TRDY#

H_HIT#H_HITM#

H_A#33

H_REQ#0

H_REQ#2H_REQ#3

H_REQ#1

H_REQ#4

CLK_CPU_BCLKCLK_CPU_BCLK#

H_A20M#

H_IGNNE#H_FERR#

H_A#34H_A#35

H_A#18H_A#19

H_ADS#H_BNR#H_BPRI#

H_DBSY#

H_DEFER#

H_A#20H_A#21H_A#22H_A#23H_A#24H_A#25

H_DRDY#

H_BR0#

H_A#26H_A#27H_A#28H_A#29H_A#30H_A#31

XDP_BPM#5XDP_TCKXDP_TDIXDP_TDOXDP_TMSXDP_TRST#

XDP_DBRESET#

H_A#3H_A#4H_A#5H_A#6H_A#7H_A#8H_A#9H_A#10H_A#11H_A#12H_A#13H_A#14H_A#15H_A#16

H_ADSTB#0

XDP_TRST#

XDP_TCK

XDP_DBRESET#

XDP_TDI

XDP_TDO

XDP_BPM#5

XDP_TMS

1D05V_S0

1D05V_S0

1D05V_S0

3D3V_S0

1D05V_S0

H_SMI#

H_ADSTB#17

H_THERMTRIP# 7,19

CPU_PROCHOT# 38

H_INIT# 19,32

H_RESET# 7

H_TRDY# 7

H_HITM# 7H_HIT# 7

H_LOCK# 7

CLK_CPU_BCLK 3CLK_CPU_BCLK# 3

H_A20M#19

H_IGNNE#19

H_STPCLK#19H_INTR19H_NMI19

H_FERR#19

H_BPRI# 7

H_DBSY# 7H_DRDY# 7

H_BR0# 7

H_BNR# 7H_ADS# 7

H_DEFER# 7

XDP_DBRESET# 20

H_ADSTB#07

H_RS#0 7H_RS#1 7H_RS#2 7

H_REQ#07H_REQ#17H_REQ#27H_REQ#37H_REQ#47

OCP# 20

H_THERMDA 22H_THERMDC 22

H_A#[3..35]7

Title


Date: Sheet of


ME3-Discrete

Meron(1/3)-AGTL+/XDPCustom

4 51Wednesday, August 15, 2007

Title


Date: Sheet of


ME3-Discrete



Title


Date: Sheet of


ME3-Discrete



H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil

original value:BGA479-SKT6-GPU1

layout note:Zo =55ohm , 0.5" MAX forGTLREF

layout note : Change R237 to 649 ohm if using XTP to ITP adapter

A3#J4A4#L5A5#L4A6#K5A7#M3A8#N2A9#J1A10#N3A11#P5A12#P2A13#L2A14#P4A15#P1A16#R1

A20M#A6

ADS# H1

ADSTB0#M1

REQ0#K3REQ1#H2REQ2#K2REQ3#J3REQ4#L1

A17#Y2A18#U5A19#R3A20#W6A21#U4A22#Y5

A30#U2

A24#R4A25#T5A26#T3

A32#W3

A28#W5A29#Y4

A27#W2

A31#V4

A33#AA4A34#AB2A35#AA3

FERR#A5IGNNE#C4

RSVD#M4M4RSVD#N5N5RSVD#T2T2RSVD#V3V3RSVD#B2B2RSVD#C3C3

BNR# E2BPRI# G5

DEFER# H5

DBSY# E1DRDY# F21

BR0# F1

IERR# D20INIT# B3

LOCK# H4

RS0# F3RS1# F4RS2# G3

TRDY# G2

HIT# G6HITM# E4

BPM0# AD4BPM1# AD3BPM2# AD1BPM3# AC4PRDY# AC2PREQ# AC1

TCK AC5TDI AA6

TDO AB3TMS AB5

TRST# AB6DBR# C20

PROCHOT# D21THRMDA A24

THERMTRIP# C7

BCLK0 A22BCLK1 A21

RSVD#D2D2

RSVD#F6F6RSVD#D3D3RSVD#D22D22

STPCLK#D5LINT0C6LINT1B4SMI#A3

A23#U1

ADSTB1#V1

RESET# C1

KEY_NCB1

THRMDC B25

1 OF 4

RESERVED

HCLK

THERMAL

ADDR GROUP 1

XDP/ITP SIGNALS

CONTROL

ADDR GROUP 0

ICH

U56A

BGA479-SKT6-GPU3

1 OF 4

RESERVED

HCLK

THERMAL

ADDR GROUP 1

XDP/ITP SIGNALS

CONTROL

ADDR GROUP 0

ICH

U56A

BGA479-SKT6-GPU3

TP28TPAD28 TP28TPAD28TP19TPAD28 TP19TPAD28

1 2R112 54D9R2F-L1-GPR112 54D9R2F-L1-GP

C

B

EQ7

MMBT3904WT1G-GP

DYQ7

MMBT3904WT1G-GP

DY

12

R13156R2J-4-GPR13156R2J-4-GP

TP25TPAD28 TP25TPAD28

12

R13556R2J-4-GPDYR13556R2J-4-GPDY

1 2

R129

1KR2J-1-GP

R129

1KR2J-1-GP




1 2R114 54D9R2F-L1-GPR114 54D9R2F-L1-GP

TP21 TPAD28TP21 TPAD28


1 2R111 51R2F-2-GPR111 51R2F-2-GP

1 2R115 54D9R2F-L1-GPR115 54D9R2F-L1-GP

1 2R116 54D9R2F-L1-GPR116 54D9R2F-L1-GP


1 2R132 68R3J-GPR132 68R3J-GP

1 2R110 54D9R2F-L1-GPR110 54D9R2F-L1-GP

TP14 TPAD28TP14 TPAD28TP22 TPAD28TP22 TPAD28TP12 TPAD28TP12 TPAD28


TP16 TPAD28TP16 TPAD28



5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CPU_BSEL0CPU_BSEL1CPU_BSEL2

H_DSTBN#0H_DSTBP#0H_DINV#0

H_D#0H_D#1H_D#2H_D#3H_D#4H_D#5H_D#6H_D#7H_D#8H_D#9H_D#10H_D#11H_D#12H_D#13H_D#14H_D#15

COMP0COMP1COMP2COMP3

H_DPSLP#H_DPRSTP#

H_DPWR#H_PWRGOODH_PWRGOODH_PWRGOODH_PWRGOODH_CPUSLP#PSI#



TEST4





TEST1TEST2

V_CPU_GTLREF

VCC_SENSE

VSS_SENSE

CPU_VID0CPU_VID1CPU_VID2CPU_VID3CPU_VID4CPU_VID5CPU_VID6

VCC_SENSE

TEST3

VSS_SENSE

TEST5TEST6

V_CPU_GTLREF

1D05V_S0

1D5V_S0

VCC_CORE_S0 VCC_CORE_S0

VCC_CORE_S0

1D05V_S0

H_DINV#07

H_DSTBN#07H_DSTBP#07

H_DPRSTP# 7,19,38H_DPSLP# 19

H_CPUSLP# 7

H_DPWR# 7H_PWRGOOD 19

PSI# 38

H_DINV#17

H_DSTBN#17H_DSTBP#17

CPU_BSEL03CPU_BSEL13

H_DINV#2 7

H_DINV#3 7

H_DSTBN#2 7H_DSTBP#2 7

H_DSTBN#3 7H_DSTBP#3 7

CPU_BSEL23

CPU_VID[0..6] 38

VSS_SENSE 38

VCC_SENSE 38

H_D#[0..63]7

Title


Date: Sheet of


ME3-Discrete

Meron(2/3)-AGTL+/PWRA3


Title


Date: Sheet of


ME3-Discrete



Title


Date: Sheet of


ME3-Discrete



PLACE C173 close to the TEST4 PIN, make sure TEST3,TEST4,TEST5 tracerouting is reference to GND andaway other noisy signals

Close to CPUpin AD26Z0=55 ohmwith in500mils .

CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0

166

200

0

0 0

11

1

Resistor Placedwithin 0.5" of CPUpin. Trace shouldbe at least 25 milsaway from any othertoggling signal .COMP[0,2] tracewidth is 18 mils.COMP[1,3] tracewidth is 4 mils .

Close to CPU pinwithin 500mils

layout note: place C3 nearPIN B26

Length match within25 mils . The tracewidth/space/other is20/7/25 .


1 2R122 100R2F-L1-GP-UR122 100R2F-L1-GP-U

TP33TPAD28 TP33TPAD28 1 2R109 54D9R2F-L1-GPR109 54D9R2F-L1-GP

1 2R136 27D4R2F-L1-GPR136 27D4R2F-L1-GP

12

TC13

SE330U2VD

M-6-G

P

DY

TC13

SE330U2VD

M-6-G

P

DY

12

C587

SCD

01U

16V2

KX-3

GP

C587

SCD

01U

16V2

KX-3

GP

1 2R121 100R2F-L1-GP-UR121 100R2F-L1-GP-U


1 2 C586

SCD1U16V2KX-3GP

DY

C586

SCD1U16V2KX-3GP

DY

1 2R1300R0402-PAD

R1300R0402-PAD

12

R3311KR2F-3-GPR3311KR2F-3-GP


VCCA7VCCA9

VCCAC10

VCCA10VCCA12VCCA13VCCA15VCCA17VCCA18VCCA20VCCB7VCCB9VCCB10VCCB12VCCB14VCCB15VCCB17VCCB18VCCB20VCCC9VCCC10VCCC12VCCC13VCCC15VCCC17VCCC18VCCD9VCCD10VCCD12VCCD14VCCD15VCCD17VCCD18VCCE7VCCE9VCCE10VCCE12VCCE13VCCE15

VCCAA7VCCAA9VCCAA10VCCAA12VCCAA13VCCAA15VCCAA17VCCAA18VCCAA20VCCAB9

VCCAB12VCCAB14VCCAB15VCCAB17VCCAB18

VCCE17VCCE18VCCE20VCCF7VCCF9VCCF10VCCF12VCCF14VCCF15VCCF17VCCF18VCCF20

VCC AB20VCC AB7VCC AC7VCC AC9VCC AC12VCC AC13VCC AC15VCC AC17VCC AC18VCC AD7VCC AD9VCC AD10VCC AD12VCC AD14VCC AD15VCC AD17VCC AD18VCC AE9VCC AE10VCC AE12VCC AE13VCC AE15VCC AE17VCC AE18VCC AE20VCC AF9VCC AF10VCC AF12VCC AF14VCC AF15VCC AF17VCC AF18VCC AF20

VCCP G21

VCCP J6

VCCP J21

VCCP K6

VCCP K21

VCCP M6

VCCP M21

VCCP N6VCCP N21

VCCP R6VCCP R21

VCCP T6VCCP T21

VCCP V6

VCCP V21VCCP W21

VCCA B26VCCA C26

VID0 AD6

VID6 AE2

VID4 AE3

VID2 AE5

VID5 AF3

VID3 AF4

VID1 AF5

VSSSENSE AE7

VCCSENSE AF7

VCCAB10

3 OF 4U56C

BGA479-SKT6-GPU3

3 OF 4U56C

BGA479-SKT6-GPU3

1 2R1230R0402-PAD

R1230R0402-PAD

12

R332

2KR2F-3-GP

R332

2KR2F-3-GP

1 2R113 27D4R2F-L1-GPR113 27D4R2F-L1-GP

D16#N22D17#K25D18#P26D19#R23D20#L23D21#M24D22#L22D23#M23D24#P25D25#P23D26#P22D27#T24D28#R24D29#L25D30#T25D31#N25

DINV0#H25

DINV1#N24

DSTBN0#J26

DSTBN1#L26

DSTBP0#H26

DSTBP1#M26

D0#E22D1#F24D2#E26D3#G22D4#F23D5#G25D6#E25D7#E23D8#K24D9#G24D10#J24D11#J23D12#H22D13#F26D14#K22D15#H23

D53# AC26

D60# AC22

D63# AC23

GTLREFAD26

TEST2D25

BSEL0B22BSEL1B23BSEL2C21

DINV2# U22

D32# Y22D33# AB24D34# V24D35# V26D36# V23

D38# U25D39# U23D40# Y25D41# W22D42# Y23D43# W24D44# W25D45# AA23D46# AA24D47# AB25

DSTBP2# AA26DSTBN2# Y26

D48# AE24D49# AD24

D52# AB21

D54# AD20D55# AE22D56# AF23D57# AC25D58# AE21D59# AD21

D61# AD23

DINV3# AC20

DSTBN3# AE25

D51# AB22D50# AA21

D62# AF22

COMP0 R26COMP1 U26

DPRSTP# E5DPSLP# B5DPWR# D24

PWRGOOD D6SLP# D7PSI# AE6

TEST1C23

TEST6A26

TEST3C24

TEST5AF1TEST4AF26

D37# T22

DSTBP3# AF24

COMP2 AA1COMP3 Y1

2 OF 4

DATA GRP0

DATA GRP1

DATA GRP2

DATA GRP3

MISC

U56B

BGA479-SKT6-GPU3

2 OF 4

DATA GRP0

DATA GRP1

DATA GRP2

DATA GRP3

MISC

U56B

BGA479-SKT6-GPU3


1 2R137 54D9R2F-L1-GPR137 54D9R2F-L1-GP

12

C289SC10U10V5ZY-1GPC289SC10U10V5ZY-1GP

12

C282

SCD

01U

16V2

KX-3

GP

C282

SCD

01U

16V2

KX-3

GP

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VCC_CORE_S0

VCC_CORE_S0

1D05V_S0

Title


Date: Sheet of


ME3-Discrete

Meron(3/3)-GND&BypassA3


Title


Date: Sheet of


ME3-Discrete



Title


Date: Sheet of


ME3-Discrete



Place these capacitors on L1(North side ,Secondary Layer)

Place these capacitors on L1(North side ,Secondary Layer)

Mid FrequencdDecoupling

Place theseinside socketcavity on L1(North sideSecondary)

12

C258

SC10

U10

V5KX

-2G

P

C258

SC10

U10

V5KX

-2G

P

12

C540

SC10

U10

V5KX

-2G

P

C540

SC10

U10

V5KX

-2G

P

12

C271

SC10

U10

V5KX

-2G

P

C271

SC10

U10

V5KX

-2G

P

12

C559

SC10

U10

V5KX

-2G

P

C559

SC10

U10

V5KX

-2G

P

12

C249SCD1U16V2KX-3GPC249SCD1U16V2KX-3GP

12

C263

SC10

U10

V5KX

-2G

PDY

C263

SC10

U10

V5KX

-2G

PDY

12

C532

SC10

U10

V5KX

-2G

P

C532

SC10

U10

V5KX

-2G

P

12

C268

SC10

U10

V5KX

-2G

P

C268

SC10

U10

V5KX

-2G

P

12

C257

SC10

U10

V5KX

-2G

P

C257

SC10

U10

V5KX

-2G

P

12

C251

SC10

U10

V5KX

-2G

P

C251

SC10

U10

V5KX

-2G

P 12

C267

SC10

U10

V5KX

-2G

PDY

C267

SC10

U10

V5KX

-2G

PDY

12

C256

SC10

U10

V5KX

-2G

P

C256

SC10

U10

V5KX

-2G

P

12

C274

SC10

U10

V5KX

-2G

P

C274

SC10

U10

V5KX

-2G

P

12

C275

SC10

U10

V5KX

-2G

P

C275

SC10

U10

V5KX

-2G

P

12


12

C558

SC10

U10

V5KX

-2G

P

C558

SC10

U10

V5KX

-2G

P

12

C272

SC10

U10

V5KX

-2G

P

C272

SC10

U10

V5KX

-2G

P

VSSAF2

VSSA4VSSA8VSSA11VSSA14VSSA16VSSA19VSSA23

VSSB6VSSB8VSSB11VSSB13VSSB16VSSB19VSSB21VSSB24VSSC5VSSC8VSSC11VSSC14VSSC16VSSC19VSSC2VSSC22VSSC25VSSD1VSSD4VSSD8VSSD11VSSD13VSSD16VSSD19VSSD23VSSD26VSSE3VSSE6VSSE8VSSE11VSSE14VSSE16VSSE19VSSE21VSSE24VSSF5VSSF8VSSF11VSSF13VSSF16VSSF19VSSF2VSSF22VSSF25VSSG4VSSG1VSSG23VSSG26VSSH3VSSH6VSSH21VSSH24VSSJ2VSSJ5VSSJ22VSSJ25VSSK1VSSK4VSSK23VSSK26VSSL3VSSL6VSSL21VSSL24VSSM2VSSM5VSSM22VSSM25VSSN1VSSN4VSSN23VSSN26VSSP3

VSS P6VSS P21VSS P24VSS R2VSS R5VSS R22VSS R25VSS T1VSS T4VSS T23VSS T26VSS U3VSS U6VSS U21VSS U24VSS V2VSS V5VSS V22VSS V25VSS W1VSS W4VSS W23VSS W26VSS Y3VSS Y6VSS Y21VSS Y24VSS AA2VSS AA5VSS AA8VSS AA11VSS AA14VSS AA16VSS AA19VSS AA22VSS AA25VSS AB1VSS AB4VSS AB8VSS AB11VSS AB13VSS AB16VSS AB19VSS AB23VSS AB26VSS AC3VSS AC6VSS AC8VSS AC11VSS AC14VSS AC16VSS AC19VSS AC21VSS AC24VSS AD2VSS AD5VSS AD8VSS AD11VSS AD13VSS AD16VSS AD19VSS AD22VSS AD25VSS AE1VSS AE4VSS AE8VSS AE11VSS AE14VSS AE16VSS AE19VSS AE23VSS AE26VSS A2VSS AF6VSS AF8VSS AF11VSS AF13VSS AF16VSS AF19VSS AF21VSS A25VSS AF25

4 OF 4U56D

BGA479-SKT6-GPU3

4 OF 4U56D

BGA479-SKT6-GPU3

12

C248SCD1U16V2KX-3GPC248SCD1U16V2KX-3GP1

2

C247SCD1U16V2KX-3GPC247SCD1U16V2KX-3GP 1

2

C279SCD1U16V2KX-3GPC279SCD1U16V2KX-3GP1

2


5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DDR_B_MA14

H_SWNGH_VREF

SM_RCOMP_VOL

PLT_RST_R#

CFG6CFG7

CFG10

MCH_CLKSEL1

CFG11

MCH_CLKSEL0

MCH_CLKSEL2

DMI_RXP3DMI_RXP2

DMI_RXP0

CLPWROK_MCH

DMI_RXP1

M_ODT2

PM_EXTTS#0

M_ODT1M_ODT0

M_ODT3

PM_POK_R

H_THERMTRIP#

PM_BMBUSY#

PM_EXTTS#1PM_EXTTS#0

CLK_MCH_3GPLLCLK_MCH_3GPLL#

MCH_ICH_SYNC#

DPRSLPVR

DFGT_VID2DFGT_VID3DFGT_VR_EN

DFGT_VID0DFGT_VID1

ICH_SDVO_DATA

M_CLK_DDR0

ICH_SDVO_CLK

M_CLK_DDR#0

M_CLK_DDR1

CFG18

DDR_CS3_DIMMB#DDR_CS2_DIMMB#

M_CLK_DDR#1

DDR_CKE3_DIMMBDDR_CKE2_DIMMB

DDR_VREF_S3

DDR_CS1_DIMMA#DDR_CS0_DIMMA#

DDR_CKE1_DIMMADDR_CKE0_DIMMA

M_CLK_DDR3M_CLK_DDR2

SM_RCOMP_VOH

M_CLK_DDR#3M_CLK_DDR#2

CL_VREF

SM_RCOMP_VOL

TEST1_GMCH

H_DPRSTP#

DMI_TXN1DMI_TXN0

DMI_TXN3DMI_TXN2

PM_EXTTS#1

H_RCOMP

PLT_RST_R#

SM_RCOMP

DMI_TXP1DMI_TXP0

DMI_TXP3DMI_TXP2

DMI_RXN0

SM_RCOMP#

DMI_RXN2DMI_RXN1

CFG5

DMI_RXN3

TEST2_GMCH

CFG8

CLKREQ#_B

CFG9

CFG13CFG12

CFG19

CFG16

CFG20

H_VREF

H_D#0

H_D#3H_D#2H_D#1

H_D#34H_D#33H_D#32

H_D#36H_D#35

H_D#39H_D#38H_D#37

H_D#42H_D#41H_D#40

H_D#44H_D#43

H_D#47H_D#46H_D#45

H_D#50H_D#49H_D#48

H_D#52H_D#51

H_D#55H_D#54H_D#53

H_D#58H_D#57H_D#56

H_D#60H_D#59

H_D#63H_D#62H_D#61

H_D#6H_D#5H_D#4

H_D#8H_D#7

H_D#11H_D#10H_D#9

H_D#14H_D#13H_D#12

H_D#16H_D#15

H_D#19H_D#18H_D#17

H_D#22H_D#21H_D#20

H_D#24H_D#23

H_D#27H_D#26H_D#25

H_D#30H_D#29H_D#28

H_A#33H_D#31

H_A#3

H_A#35H_A#34

H_A#6H_A#5H_A#4

H_A#8H_A#7

H_A#11H_A#10H_A#9

H_A#14H_A#13H_A#12

H_A#16H_A#15

H_A#19H_A#18H_A#17

H_A#22H_A#21H_A#20

H_A#24H_A#23

H_A#27H_A#26H_A#25

H_A#30H_A#29H_A#28

H_A#32H_A#31

H_RCOMP

H_SCOMPH_SCOMP#

H_RESET#H_CPUSLP#

H_SWNG

H_LOCK#

H_HIT#

H_ADS#

H_ADSTB#1

H_HITM#

H_BPRI#H_BNR#

H_ADSTB#0

H_DBSY#

H_BR0#

H_DRDY#H_DPWR#

H_DEFER#

CLK_MCH_BCLKCLK_MCH_BCLK#

H_DSTBN#0

H_RS#2

H_TRDY#

H_DINV#1H_DINV#0

H_DSTBN#1

H_DINV#3H_DINV#2

H_REQ#1

H_DSTBN#3H_DSTBN#2

H_DSTBP#1H_DSTBP#0

H_REQ#2

H_DSTBP#3H_DSTBP#2

H_RS#0

H_REQ#4H_REQ#3

H_REQ#0

H_RS#1

PM_POK_R

DDR_A_MA14

SM_RCOMP_VOH

ICH_SDVO_DATAICH_SDVO_CLK

CFG9

ICH_SDVO_DATA

1D05V_S0

1D05V_S0

1D25V_S0

1D05V_S0

1D8V_S3

3D3V_S0

DDR_VREF_S3

1D8V_S3

2D5V_S0H_DSTBN#1 5

H_HITM# 4

H_DSTBN#2 5

H_DSTBP#0 5

H_DSTBN#3 5

CLK_MCH_BCLK 3

H_DSTBN#0 5

H_DEFER# 4

H_ADS# 4

H_BPRI# 4

H_ADSTB#0 4

H_DSTBP#1 5

H_ADSTB#1 4

H_DINV#0 5

H_BNR# 4

H_DSTBP#2 5

H_DRDY# 4

H_BR0# 4

H_DSTBP#3 5

H_DPWR# 5

H_DBSY# 4

H_TRDY# 4H_LOCK# 4

H_HIT# 4

H_DINV#2 5H_DINV#1 5

CLK_MCH_BCLK# 3

PM_PWROK20,22

H_DINV#3 5

H_RESET#4

VGATE_PWRGD20,38

H_CPUSLP#5

H_A#[3..35] 4H_D#[0..63]5

H_REQ#0 4

H_REQ#2 4H_REQ#1 4

H_REQ#4 4H_REQ#3 4

H_RS#0 4

H_RS#2 4H_RS#1 4

DMI_RXP0 20

DMI_RXP2 20DMI_RXP1 20

M_ODT0 13

DMI_RXP3 20

M_ODT1 13

M_ODT3 14M_ODT2 14

M_CLK_DDR0 13

M_CLK_DDR2 14M_CLK_DDR1 13

CL_RST# 20

M_CLK_DDR#0 13

M_CLK_DDR3 14

M_CLK_DDR#1 13

M_CLK_DDR#3 14M_CLK_DDR#2 14

CLK_MCH_3GPLL 3

MCH_ICH_SYNC# 20

CLK_MCH_3GPLL# 3

DMI_TXN0 20DMI_TXN1 20

DMI_TXN3 20DMI_TXN2 20

VGATE_PWRGD 20,38CL_DATA0 20CL_CLK0 20

DMI_TXP1 20DMI_TXP0 20

DMI_TXP2 20

DDR_CKE0_DIMMA 13

DMI_TXP3 20

DDR_CKE1_DIMMA 13

DDR_CKE3_DIMMB 14DDR_CKE2_DIMMB 14

DMI_RXN0 20

CLKREQ#_B 3

DMI_RXN1 20DMI_RXN2 20

DDR_CS0_DIMMA# 13

DMI_RXN3 20

DDR_CS2_DIMMB# 14DDR_CS1_DIMMA# 13

DDR_CS3_DIMMB# 14

DPRSLPVR20,38

PM_EXTTS#114

H_THERMTRIP#4,19

H_DPRSTP#5,19,38PM_EXTTS#013

PM_BMBUSY#20

MCH_CLKSEL13MCH_CLKSEL03

MCH_CLKSEL23

DDR_A_MA1413

PLT_RST1# 18,20,23,29,31,32,45

DDR_B_MA1414

Title


Date: Sheet of


ME3-DiscreteCRESTLINE(1/6)-AGTL+/DMI/DDR2

Custom


Title


Date: Sheet of



Custom


Title


Date: Sheet of



Custom


layout note :Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces

Layout Note :H_RCOMP / H_VREF / H_SWNGtrace width and spacing is 10/20

CFG[17:3] have internal pull upCFG[19:18] have internal pull down

Layout Note :Place C151 within 100 mils of NB

FOR Calero: 80.6 ohm Crestline: 20 ohm

Layout Note :Place C153 near pin B3 of NB

From Astro demo schematic

TP91TP91

TP102TP102

H_D#0E2H_D#1G2H_D#2G7H_D#3M6H_D#4H7H_D#5H3H_D#6G4H_D#7F3H_D#8N8H_D#9H2H_D#10M10H_D#11N12H_D#12N9H_D#13H5H_D#14P13H_D#15K9H_D#16M2H_D#17W10H_D#18Y8H_D#19V4H_D#20M3H_D#21J1H_D#22N5H_D#23N3H_D#24W6H_D#25W9H_D#26N2H_D#27Y7H_D#28Y9H_D#29P4H_D#30W3H_D#31N1H_D#32AD12H_D#33AE3H_D#34AD9H_D#35AC9H_D#36AC7H_D#37AC14H_D#38AD11H_D#39AC11H_D#40AB2H_D#41AD7H_D#42AB1H_D#43Y3H_D#44AC6H_D#45AE2H_D#46AC5H_D#47AG3H_D#48AJ9H_D#49AH8H_D#50AJ14H_D#51AE9H_D#52AE11H_D#53AH12H_D#54AJ5H_D#55AH5H_D#56AJ6H_D#57AE7H_D#58AJ7H_D#59AJ2H_D#60AE5H_D#61AJ3H_D#62AH2H_D#63AH13

H_SWINGB3H_RCOMPC2

H_SCOMPW1H_SCOMP#W2

H_CPURST#B6H_CPUSLP#E5

H_AVREFB9H_DVREFA9

H_A#23 D17

H_A#31 E17

H_A#28 E19

H_A#33 A19

H_A#4 B11

H_A#13 B13

H_A#16 B14

H_A#30 B15

H_A#20 B16

H_A#29 B17

H_A#27 B18

H_A#34 B19

H_A#5 C11

H_A#11 C14

H_A#7 C15

H_A#32 C18

H_A#8 F16

H_A#10 G17

H_A#21 H20

H_A#3 J13

H_A#15 J17

H_A#26 J19

H_A#12 K16

H_A#17 K19

H_A#9 L13

H_A#14 L16

H_A#22 L19

H_A#25 N16

H_A#35 N19

H_A#18 P15H_A#19 R17

H_A#6 M11

H_A#24 M17

H_ADS# G12H_ADSTB#0 H17H_ADSTB#1 G20

H_BNR# C8H_BPRI# E8

H_BREQ# F12H_DEFER# D6

H_DBSY# C10HPLL_CLK AM5

HPLL_CLK# AM7H_DPWR# H8H_DRDY# K7

H_HIT# E4H_HITM# C6

H_TRDY# B7H_LOCK# G10

H_DINV#2 AD13H_DINV#3 AE13

H_DINV#0 K5H_DINV#1 L2

H_DSTBN#2 AD2H_DSTBN#3 AH11

H_DSTBN#1 K3H_DSTBN#0 M7

H_DSTBP#2 AC2H_DSTBP#1 K2

H_DSTBP#3 AJ10

H_DSTBP#0 L7

H_REQ#1 E13H_REQ#2 A11

H_REQ#4 B12H_REQ#3 H13

H_REQ#0 M14

H_RS#1 D7H_RS#2 D8

H_RS#0 E12

1 OF 10

HOST

U18A

CRESTLINE-GP-U-NF

1 OF 10

HOST

U18A

CRESTLINE-GP-U-NF

1 2R300 10KR2J-3-GPR300 10KR2J-3-GP

12

R98392R2F-GPR98392R2F-GP

TP100TP100

12C

252

SC2D

2U10

V3ZY

-1G

P

C25

2

SC2D

2U10

V3ZY

-1G

P

12

R325

100R

2F-L

1-G

P-U

R325

100R

2F-L

1-G

P-U

1 2R315 20R2F-GPR315 20R2F-GP

1 2R291 2K2R2J-2-GPR291 2K2R2J-2-GP

12

R133

54D

9R2F

-L1-

GP

R133

54D

9R2F

-L1-

GP

TP95TP95

TP98TP98

1 2

R316

100R2J-2-GP

R316

100R2J-2-GP

12

R1263K01R2F-3-GPR1263K01R2F-3-GP

1 2R314 2K2R2J-2-GPR314 2K2R2J-2-GP

12

R3192KR2F-3-GP

R3192KR2F-3-GP

1 2R277

0R2J-2-GP DYR277

0R2J-2-GP DY

TP106TP106

TP101TP101

12


1 2R308 0R0402-PADR308 0R0402-PAD

1 2R298

20KR2J-L2-GP

R298

20KR2J-L2-GP

12

R14424D9R2F-L-GPR14424D9R2F-L-GP

TP105TP105

12


TP96TP96

12

R323221R2F-2-GPR323221R2F-2-GP

1 2R288 10KR2J-3-GPR288 10KR2J-3-GP

TP87TP87

12

C26

4

SCD

01U

25V2

KX-3

GP

C26

4

SCD

01U

25V2

KX-3

GP

TP27TP27

TP97TP97TP99TP99

RSVD#A35A35

RSVD#B34B34RSVD#B36B36RSVD#B37B37

RSVD#C34C34

RSVD#P36P36RSVD#P37P37RSVD#R35R35RSVD#N35N35RSVD#AR12AR12RSVD#AR13AR13RSVD#AM12AM12RSVD#AN13AN13RSVD#J12J12RSVD#AR37AR37RSVD#AM36AM36RSVD#AL36AL36RSVD#AM37AM37RSVD#D20D20

RSVD#H10H10RSVD#B51B51RSVD#BJ20BJ20RSVD#BK22BK22RSVD#BF19BF19RSVD#BH20BH20RSVD#BK18BK18RSVD#BJ18BJ18RSVD#BF23BF23RSVD#BG23BG23RSVD#BC23BC23RSVD#BD24BD24RSVD#BJ29BJ29RSVD#BE24BE24RSVD#BH39BH39RSVD#AW20AW20RSVD#BK20BK20RSVD#C48C48RSVD#D47D47RSVD#B44B44RSVD#C44C44

CFG0P27CFG1N27CFG2N24CFG3C21CFG4C23CFG5F23CFG6N23CFG7G23CFG8J20CFG9C20CFG10R24CFG11L23CFG12J23CFG13E23CFG14E20CFG15K23CFG16M20CFG17M24CFG18L32CFG19N33CFG20L35

PM_BM_BUSY#G41PM_DPRSTP#L39PM_EXT_TS#0L36PM_EXT_TS#1J36PWROKAW49RSTIN#AV20THERMTRIP#N20DPRSLPVRG36

NC#BJ51BJ51NC#BK51BK51NC#BK50BK50NC#BL50BL50NC#BL49BL49NC#BL3BL3NC#BL2BL2NC#BK1BK1NC#BJ1BJ1NC#E1E1NC#A5A5NC#C51C51NC#B50B50NC#A50A50NC#A49A49NC#BK2BK2

SM_CK4 AV23

SM_CK0 AV29

SM_CK#4 AW23SM_CK#3 AW25

SM_CK#0 AW30

SM_CKE1 AY32

SM_CK#1 BA23

SM_CK3 BA25SM_CK1 BB23

SM_CKE3 BD39

SM_CKE0 BE29

SM_CKE4 BG37

SM_CS#2 BG16

SM_CS#0 BG20SM_CS#1 BK16

SM_CS#3 BE13

SM_ODT3 BE16

SM_ODT0 BH18

SM_ODT2 BJ14SM_ODT1 BJ15

SM_RCOMP BL15SM_RCOMP# BK14

SM_VREF#AR49 AR49SM_VREF#AW4 AW4

DPLL_REF_CLK B42DPLL_REF_CLK# C42

DPLL_REF_SSCLK H48DPLL_REF_SSCLK# H47

PEG_CLK K44PEG_CLK# K45

DMI_RXN1 AJ38DMI_RXN2 AN42DMI_RXN3 AN46

DMI_RXN0 AN47

DMI_RXP1 AJ39DMI_RXP0 AM47

DMI_RXP2 AN41DMI_RXP3 AN45

DMI_TXN1 AJ41DMI_TXN0 AJ46

DMI_TXN2 AM40DMI_TXN3 AM44

DMI_TXP1 AJ42DMI_TXP0 AJ47

DMI_TXP2 AM39DMI_TXP3 AM43

GFX_VID2 C38

GFX_VID0 E35GFX_VID1 A39

GFX_VID3 B39GFX_VR_EN E36

CL_CLK AM49CL_DATA AK50

CL_PWROK AT43CL_RST# AN49CL_VREF AM50

TEST1 A37TEST2 R32

SDVO_CTRL_CLK H35SDVO_CTRL_DATA K36

CLKREQ# G39ICH_SYNC# G40

SM_RCOMP_VOH BK31SM_RCOMP_VOL BL31

2 OF 10

RSVD

DDR MUXING

CLK

DMI

CFG

PM

NC

MISC

ME

GRAPHICS VID

U18B

CRESTLINE-GP-U-NF

2 OF 10

RSVD

DDR MUXING

CLK

DMI

CFG

PM

NC

MISC

ME

GRAPHICS VID

U18B

CRESTLINE-GP-U-NF

12

R2902K2R2J-2-GP

DY

R2902K2R2J-2-GP

DY

TP89TP89

12

C25

5

SCD

01U

25V2

KX-3

GP

C25

5

SCD

01U

25V2

KX-3

GP

12


12

C577SCD1U16V2ZY-2GPC577SCD1U16V2ZY-2GP

TP92TP92

12

C26

5SC

2D2U

10V3

ZY-1

GP

C26

5SC

2D2U

10V3

ZY-1

GP

1 2R124 0R0402-PADR124 0R0402-PAD

12


TP104TP104

1 2R128 20R2F-GPR128 20R2F-GP

12

C215

SCD

1U16

V2KX

-3G

P

C215

SCD

1U16

V2KX

-3G

PTP90TP90

1 2R278 0R0402-PADR278 0R0402-PAD

12

R141

54D

9R2F

-L1-

GP

R141

54D

9R2F

-L1-

GP

TP93TP93

TP94TP94

12

C568

SCD

1U16

V2ZY

-2G

P

C568

SCD

1U16

V2ZY

-2G

P

TP88TP88

1 2R284 10KR2J-3-GPR284 10KR2J-3-GP

12

R292

2K2R2J-2-GPDY

R292

2K2R2J-2-GPDY

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DDR_A_D0

DDR_A_D26

DDR_A_D17

DDR_A_D14

DDR_A_D21

DDR_A_D18DDR_A_D19DDR_A_D20

DDR_A_D15

DDR_A_D25

DDR_A_D22DDR_A_D23

DDR_A_D24

DDR_A_D16

DDR_A_D52

DDR_A_D43

DDR_A_D40

DDR_A_D47


DDR_A_D41

DDR_A_D51


DDR_A_D42

DDR_A_D39

DDR_A_D30

DDR_A_D27

DDR_A_D34


DDR_A_D28

DDR_A_D38


DDR_A_D29

DDR_A_D13

DDR_A_D4

DDR_A_D1

DDR_A_D8


DDR_A_D2

DDR_A_D12


DDR_A_D3

DDR_A_D56

DDR_A_D53

DDR_A_D60


DDR_A_D54


DDR_A_D55

DDR_A_RAS#SA_RCVEN#

DDR_A_WE#

DDR_A_MA13

DDR_A_MA4

DDR_A_MA1

DDR_A_MA8

DDR_A_MA5DDR_A_MA6DDR_A_MA7

DDR_A_BS0DDR_A_BS1DDR_A_BS2

DDR_A_CAS#

DDR_A_DM0DDR_A_DM1DDR_A_DM2DDR_A_DM3DDR_A_DM4DDR_A_DM5DDR_A_DM6DDR_A_DM7

DDR_A_MA2

DDR_A_DQS0DDR_A_DQS1DDR_A_DQS2DDR_A_DQS3DDR_A_DQS4DDR_A_DQS5DDR_A_DQS6DDR_A_DQS7DDR_A_DQS#0DDR_A_DQS#1DDR_A_DQS#2DDR_A_DQS#3DDR_A_DQS#4DDR_A_DQS#5DDR_A_DQS#6DDR_A_DQS#7

DDR_A_MA0

DDR_A_MA12


DDR_A_MA3

DDR_B_D0

DDR_B_D26

DDR_B_D17

DDR_B_D14

DDR_B_D21

DDR_B_D18DDR_B_D19DDR_B_D20

DDR_B_D15

DDR_B_D25

DDR_B_D22DDR_B_D23

DDR_B_D24

DDR_B_D16

DDR_B_D52

DDR_B_D43

DDR_B_D40

DDR_B_D47


DDR_B_D41

DDR_B_D51


DDR_B_D42

DDR_B_D39

DDR_B_D30

DDR_B_D27

DDR_B_D34


DDR_B_D28

DDR_B_D38


DDR_B_D29

DDR_B_D13

DDR_B_D4

DDR_B_D1

DDR_B_D8


DDR_B_D2

DDR_B_D12


DDR_B_D3

DDR_B_D56

DDR_B_D53

DDR_B_D60


DDR_B_D54


DDR_B_D55

DDR_B_RAS#

DDR_B_WE#

SB_RCVEN#

DDR_B_BS0DDR_B_BS1DDR_B_BS2

DDR_B_CAS#

DDR_B_DM0DDR_B_DM1DDR_B_DM2DDR_B_DM3DDR_B_DM4DDR_B_DM5DDR_B_DM6DDR_B_DM7

DDR_B_DQS0DDR_B_DQS1DDR_B_DQS2DDR_B_DQS3DDR_B_DQS4DDR_B_DQS5DDR_B_DQS6DDR_B_DQS7DDR_B_DQS#0DDR_B_DQS#1DDR_B_DQS#2DDR_B_DQS#3DDR_B_DQS#4DDR_B_DQS#5DDR_B_DQS#6DDR_B_DQS#7

DDR_B_MA0

DDR_B_MA4

DDR_B_MA13

DDR_B_MA1

DDR_B_MA8

DDR_B_MA5DDR_B_MA6DDR_B_MA7

DDR_B_MA2

DDR_B_MA12

DDR_B_MA9DDR_B_MA10DDR_B_MA11

DDR_B_MA3

DDR_A_DQS#[0..7] 13

DDR_A_MA[0..13] 13

DDR_A_D[0..63] 13

DDR_A_BS[0..2] 13

DDR_A_DM[0..7] 13

DDR_A_DQS[0..7] 13

DDR_B_RAS# 14

DDR_B_WE# 14

DDR_B_DQS#[0..7] 14

DDR_B_MA[0..13] 14

DDR_B_D[0..63] 14

DDR_B_BS[0..2] 14

DDR_B_DM[0..7] 14

DDR_B_DQS[0..7] 14

DDR_A_RAS# 13

DDR_A_WE# 13

DDR_A_CAS# 13 DDR_B_CAS# 14

Title


Date: Sheet of


ME3-DiscreteCRESTLINE(2/6)-DDR2 A/B CH

A3


Title


Date: Sheet of



A3


Title


Date: Sheet of



A3


TP108TP108TP107TP107

SA_DQ1AW44

SA_DQ7AW47

SA_DQ4AR41

SA_DQ0AR43

SA_DQ5AR45SA_DQ6AT42

SA_DQS0 AT46

SA_DQS#0 AT47

SA_DQ3AY46

SA_DQS#4 BA16SA_DQS#3 BA37

SA_DQ2BA45

SA_DQS4 BB16

SA_DQS6 BB2

SA_DQS2 BB43

SA_DQS#6 BC1

SA_DQS3 BC37

SA_DQS#2 BC41SA_DQS#1 BD47

SA_DQS#5 BH7

SA_DQS1 BE48

SA_DQ9BF48

SA_DQS#7 AP2

SA_DQS7 AP3

SA_DQ8BB45

SA_DQ10BG47SA_DQ11BJ45SA_DQ12BB47SA_DQ13BG50SA_DQ14BH49

SA_DQS5 BH6

SA_DQ16AW43SA_DQ15BE45

SA_BS0 BB19SA_BS1 BK19SA_BS2 BF29

SA_CAS# BL17

SA_DM4 AW13SA_DM3 AW38

SA_DM0 AT45

SA_DM6 AY5

SA_DM2 BD42SA_DM1 BD44

SA_DM5 BG8

SA_DM7 AN6

SA_DQ17BE44SA_DQ18BG42SA_DQ19BE40SA_DQ20BF44SA_DQ21BH45SA_DQ22BG40SA_DQ23BF40SA_DQ24AR40SA_DQ25AW40SA_DQ26AT39SA_DQ27AW36SA_DQ28AW41SA_DQ29AY41SA_DQ30AV38SA_DQ31AT38SA_DQ32AV13SA_DQ33AT13SA_DQ34AW11SA_DQ35AV11SA_DQ36AU15SA_DQ37AT11SA_DQ38BA13SA_DQ39BA11SA_DQ40BE10SA_DQ41BD10SA_DQ42BD8SA_DQ43AY9SA_DQ44BG10SA_DQ45AW9SA_DQ46BD7SA_DQ47BB9SA_DQ48BB5SA_DQ49AY7SA_DQ50AT5SA_DQ51AT7SA_DQ52AY6SA_DQ53BB7SA_DQ54AR5SA_DQ55AR8SA_DQ56AR9SA_DQ57AN3SA_DQ58AM8SA_DQ59AN10SA_DQ60AT9SA_DQ61AN9SA_DQ62AM9SA_DQ63AN11

SA_MA3 BH28

SA_MA13 BJ16

SA_MA0 BJ19

SA_MA7 BJ25SA_MA6 BJ27

SA_MA12 BG30

SA_MA2 BK27

SA_MA5 BK28SA_MA4 BL24

SA_MA8 BL28SA_MA9 BA28

SA_MA10 BC19

SA_MA1 BD20

SA_MA11 BE28

SA_RAS# BE18SA_RCVEN# AY20

SA_WE# BA19

DDR SYSTEM MEMORRY A

4 OF 10U18D

CRESTLINE-GP-U-NF

DDR SYSTEM MEMORRY A

4 OF 10U18D

CRESTLINE-GP-U-NF

SB_DQ2AW50SB_DQ3AW51

SB_DQ1AR51SB_DQ0AP49

SB_DQ20BK47SB_DQ21BK49

SB_DQ19BL43

SB_DQ4AN51SB_DQ5AN50SB_DQ6AV50SB_DQ7AV49SB_DQ8BA50SB_DQ9BB50SB_DQ10BA49SB_DQ11BE50SB_DQ12BA51SB_DQ13AY49SB_DQ14BF50SB_DQ15BF49SB_DQ16BJ50SB_DQ17BJ44SB_DQ18BJ43

SB_DQ22BK43SB_DQ23BK42SB_DQ24BJ41SB_DQ25BL41SB_DQ26BJ37SB_DQ27BJ36SB_DQ28BK41SB_DQ29BJ40SB_DQ30BL35SB_DQ31BK37SB_DQ32BK13SB_DQ33BE11SB_DQ34BK11SB_DQ35BC11SB_DQ36BC13SB_DQ37BE12SB_DQ38BC12SB_DQ39BG12SB_DQ40BJ10SB_DQ41BL9SB_DQ42BK5SB_DQ43BL5SB_DQ44BK9SB_DQ45BK10SB_DQ46BJ8SB_DQ47BJ6SB_DQ48BF4SB_DQ49BH5SB_DQ50BG1SB_DQ51BC2SB_DQ52BK3SB_DQ53BE4SB_DQ54BD3SB_DQ55BJ2SB_DQ56BA3SB_DQ57BB3SB_DQ58AR1SB_DQ59AT3SB_DQ60AY2SB_DQ61AY3SB_DQ62AU2SB_DQ63AT2

SB_BS0 AY17SB_BS1 BG18SB_BS2 BG36

SB_CAS# BE17

SB_DM7 AW2

SB_DM0 AR50SB_DM1 BD49

SB_DM4 BH12

SB_DM6 BF3SB_DM5 BJ7

SB_DM2 BK45SB_DM3 BL39

SB_DQS0 AT50SB_DQS1 BD50SB_DQS2 BK46SB_DQS3 BK39SB_DQS4 BJ12SB_DQS5 BL7SB_DQS6 BE2SB_DQS7 AV2

SB_DQS#0 AU50SB_DQS#1 BC50SB_DQS#2 BL45SB_DQS#3 BK38SB_DQS#4 BK12SB_DQS#5 BK7SB_DQS#6 BF2SB_DQS#7 AV3

SB_MA11 BE37

SB_MA4 BF25

SB_MA13 BG13

SB_MA10 BG17

SB_MA2 BG25SB_MA1 BG28

SB_MA3 AW17

SB_MA8 AY28

SB_MA6 BA29

SB_MA12 BA39

SB_MA0 BC18

SB_MA7 BC28

SB_MA9 BD37

SB_MA5 BE25

SB_RAS# AV16SB_RCVEN# AY18

SB_WE# BC17

DDR SYSTEM MEMORY B

5 OF 10U18E

CRESTLINE-GP-U-NF

DDR SYSTEM MEMORY B

5 OF 10U18E

CRESTLINE-GP-U-NF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PEGCOMP

TXN13TXN14TXN15

TXN12

TXN2

TXN0

TXN5

TXN3TXN4

TXP13TXP14TXP15

TXP12

TXP2

TXP0

TXP5

TXP3TXP4

TXP1

TXP8

TXP6

TXP11

TXP9TXP10

TXP7

TXN1

TXN8

TXN6

TXN11

TXN9TXN10

TXN7

1D05V_S0

PEG_TXN8 45PEG_TXN9 45PEG_TXN10 45PEG_TXN11 45PEG_TXN12 45PEG_TXN13 45PEG_TXN14 45PEG_TXN15 45

PEG_TXP8 45PEG_TXP9 45PEG_TXP10 45PEG_TXP11 45PEG_TXP12 45PEG_TXP13 45PEG_TXP14 45PEG_TXP15 45

PEG_TXP0 45PEG_TXP1 45PEG_TXP2 45PEG_TXP3 45PEG_TXP4 45PEG_TXP5 45PEG_TXP6 45PEG_TXP7 45

PEG_TXN0 45PEG_TXN1 45PEG_TXN2 45PEG_TXN3 45PEG_TXN4 45PEG_TXN5 45PEG_TXN6 45PEG_TXN7 45

PEG_RXP3 45

PEG_RXP7 45

PEG_RXP11 45

PEG_RXP15 45

PEG_RXN3 45

PEG_RXN7 45

PEG_RXN11 45

PEG_RXN15 45

PEG_RXN4 45

PEG_RXN8 45

PEG_RXN12 45

PEG_RXN0 45

PEG_RXN5 45

PEG_RXN9 45

PEG_RXN13 45

PEG_RXN1 45PEG_RXN2 45

PEG_RXN6 45

PEG_RXN10 45

PEG_RXN14 45

PEG_RXP4 45

PEG_RXP8 45

PEG_RXP12 45

PEG_RXP0 45

PEG_RXP5 45

PEG_RXP9 45

PEG_RXP13 45

PEG_RXP1 45PEG_RXP2 45

PEG_RXP6 45

PEG_RXP10 45

PEG_RXP14 45

Title


Date: Sheet of


ME3-DiscreteCRESTLINE(3/6)-VGA/LVDS/TV

A3


Title


Date: Sheet of



A3


Title


Date: Sheet of



A3


1 = Enable *

CFG[18:17] Reversed

SDVO_CTRLDATA 0 = No SDVO Device Present *1 = SDVO Device Present

CFG19(DMI Lane Reversal)0 = Normal Operation *(Lane number in Order)1 = Reverse lane

CFG20(PCIE/SDVO consurrent)0 = Only PCIE or SDVO is operational *1 = PCIE/SDVO are operating simu.

Strap Pin TablePEGCOMP tracewidth and spacingis 20/25 mils.

CFG[2:0] FSB Freq select010 = FSB 800MHz011 = FSB 667MHzOthers = Reserved

0 = DMI x 21 = DMI x 4 *

CFG5 (DMI select)

CFG6 Reserved

CFG7 (CPU Strap)0 = Reserved1 = Mobile CPU *

CFG8 (Low power PCIE)0 = Normal mode1 = Low Power mode *

CFG9(PCIE Graphics Lane Reversal)

0 = Reverse Lane1 = Normal Operation *

CFG[11:10] Reserved

CFG[13:12] (XOR/ALLZ)

00 = Reserved01 = XOR Mode Enabled10 = All Z Mode Enabled11 = Normal Operation (Default)*

CFG[15:14] Reserved

CFG16 (FSB Dynamic ODT)0 = Disable

1 2C444 SCD1U10V2KX-5GPC444 SCD1U10V2KX-5GP











1 2R281 24D9R2F-L-GPR281 24D9R2F-L-GP












L_BKLT_CTRLJ40L_BKLT_ENH39L_CTRL_CLKE39L_CTRL_DATAE40L_DDC_CLKC37L_DDC_DATAD35L_VDD_ENK40

LVDS_IBGL41LVDS_VBGL43

LVDS_VREFLN40LVDS_VREFHN41

LVDSA_CLKC45LVDSB_CLK#D44

LVDSA_CLK#D46

LVDSB_CLKE42

LVDSB_DATA2A45LVDSB_DATA1A47

LVDSB_DATA#2B45LVDSB_DATA#1B47

LVDSB_DATA0E44

LVDSA_DATA1E50

LVDSA_DATA#1E51

LVDSA_DATA2F48

LVDSA_DATA#2F49

LVDSB_DATA#0G44

LVDSA_DATA0G50

LVDSA_DATA#0G51

TVA_DACE27

TVA_RTNF27

TVB_DACG27

TVB_RTNJ27

TVC_DACK27

TVC_RTNL27

TV_DCONSEL0M35TV_DCONSEL1P33

CRT_RED#E29

CRT_VSYNCE33CRT_TVO_IREFC32

CRT_REDF29

CRT_HSYNCF33

CRT_BLUE#G32

CRT_DDC_DATAG35

CRT_BLUEH32

CRT_GREEN#J29CRT_GREENK29

CRT_DDC_CLKK33

PEG_COMPI N43PEG_COMPO M43

PEG_RX#2 N47

PEG_RX1 L50

PEG_RX#1 L51

PEG_RX2 M47

PEG_RX5 T41

PEG_RX#3 T45

PEG_RX4 T49

PEG_RX#4 T50PEG_RX#5 U40

PEG_RX3 U44

PEG_RX#7 Y40PEG_RX#6 Y44

PEG_RX9 Y48PEG_RX8 AB50

PEG_RX#8 AB51

PEG_RX7 W41PEG_RX6 W45

PEG_RX#9 W49

PEG_RX11 AC41PEG_RX10 AC45

PEG_RX#11 AD40PEG_RX#10 AD44

PEG_RX#15 AG41

PEG_RX15 AG42

PEG_RX#14 AG45

PEG_RX#12 AG46

PEG_RX13 AG49

PEG_RX0 J50

PEG_RX#0 J51

PEG_RX14 AH45

PEG_RX12 AH47

PEG_RX#13 AH49

PEG_TX#6 Y43

PEG_TX#8 W38PEG_TX#7 W46

PEG_TX#12 AC42

PEG_TX#10 AC46PEG_TX#11 AC49

PEG_TX#9 AD39

PEG_TX#14 AE49PEG_TX#13 AH39

PEG_TX#15 AH44

PEG_TX#0 N45

PEG_TX#3 N51PEG_TX#4 R50PEG_TX#5 T42

PEG_TX#1 U39PEG_TX#2 U47

PEG_TX8 Y39PEG_TX7 Y47PEG_TX6 W42

PEG_TX9 AC38

PEG_TX11 AC50PEG_TX12 AD43

PEG_TX10 AD47

PEG_TX14 AE50PEG_TX13 AG39

PEG_TX15 AH43

PEG_TX3 N50

PEG_TX0 M45

PEG_TX4 R51

PEG_TX1 T38PEG_TX2 T46

PEG_TX5 U43

3 OF 10

LVDS

TV

VGA

PCI_EXPRESS GRAPHICS

U18C

CRESTLINE-GP-U-NF

3 OF 10

LVDS

TV

VGA

PCI_EXPRESS GRAPHICS

U18C

CRESTLINE-GP-U-NF











5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VTTLF1VTTLF2VTTLF3

1D8V_S0_TXLVDS 1D25V_S0

1D05V_S0

3D3V_S0

1D25V_S0_AXD

1D25V_S0

3D3V_S0_HV

3D3V_S0_HV

3D3V_S0

1D25V_S0_HPLL

1D25V_S0_MPLL

1D25V_S0_PEGPLL

3D3V_S0_PEG_BG

1D25V_S0_A_SM

1D25V_S0_SM_CK

1D25V_S0_HPLL

1D25V_S0_PEGPLL

1D05V_S0_D

1D05V_S0_PEG

1D8V_S3_SM_CK

1D25V_S0_DMI

1D25V_S0_AXF

1D05V_S01D25V_S0

1D25V_S0_AXF

1D8V_S3

1D8V_S3_SM_CK

1D25V_S0

1D25V_S0_DMI

1D25V_S0

1D25V_S0_PEGPLL

1D5V_S0

1D5V_S0_TVDAC

1D25V_S0

1D25V_S0_HPLL

1D25V_S0

1D25V_S0_MPLL

1D05V_S0

1D05V_S0_PEG

1D5V_S0_TVDAC

1D05V_S0_PEG

Title


Date: Sheet of


ME3-DiscreteCRESTLINE(4/6)-PWR

A3

10 51Sunday, September 09, 2007

Title


Date: Sheet of



A3


Title


Date: Sheet of



A3


20mil

20mil

Intel spec:VCC_PEX ,Imax=1200 mA

Intel spec:VCC_RXR_DMI , Imax=200 mA

60mil

MV-2

12

C506

SCD

1U16V2ZY-2G

P

C506

SCD

1U16V2ZY-2G

P

12

C535

SCD

22U

16V3

ZY-G

P

DYC535

SCD

22U

16V3

ZY-G

P

DY 12

C530

SCD

22U

16V3

ZY-G

P

C530

SCD

22U

16V3

ZY-G

P

12

C538SC10U10V5KX-2GPC538SC10U10V5KX-2GP

1 2R139

0R0603-PAD

R139

0R0603-PAD

12

C552

SC1U

10V3

KX-3

GP

C552

SC1U

10V3

KX-3

GP

12

C499SC1KP50V2KX-1GP

C499SC1KP50V2KX-1GP

12R295

0R0402-PAD

R295

0R0402-PAD

1 2

L13

BLM18AG121SN-1GP

L13

BLM18AG121SN-1GP12

C194

SC10U

10V5KX-2GP

C194

SC10U

10V5KX-2GP

12

C544SC10U10V5KX-2GP

C544SC10U10V5KX-2GP

1 2R81

0R0805-PAD

R81

0R0805-PAD

1 2R328

0R0805-PAD

R328

0R0805-PAD

1 2

L12

BLM18PG121SN-1GP

L12

BLM18PG121SN-1GP

1 2R103

0R0805-PAD

R103

0R0805-PAD

VCC_SYNCJ32

VCCA_CRT_DACA33VCCA_CRT_DACB33

VCCA_DAC_BGA30

VSSA_DAC_BGB32

VCCA_DPLLAB49

VCCA_SMAW18

VCCA_LVDSA41

VCCA_DPLLBH49

VCCA_PEG_BGK50

VCCA_HPLLAL2

VCCA_MPLLAM2

VCCA_PEG_PLLU51

VSSA_LVDSB41

VSSA_PEG_BGK49

VCCA_SMAU19VCCA_SMAV19

VCCA_TVC_DACA28

VCCA_TVA_DACB25

VCCA_TVB_DACB27VCCA_TVC_DACB28

VCCA_SMAT17VCCA_SMAT18VCCA_SMAT19VCCA_SMAT21VCCA_SMAT22

VCCA_TVA_DACC25

VCCA_TVB_DACC27

VCCA_SM_CKBB29VCCA_SM_CKBC29

VCCA_SM_NCTFAR16VCCA_SM_NCTFAR17

VCCA_SMAU18VCCA_SMAU17

VCCD_CRTM32VCCD_TVDACL29

VCCD_QDACN28

VCCD_HPLLAN2

VCCD_PEG_PLLU48

VCCD_LVDSJ41VCCD_LVDSH42

VTT R1VTT R2VTT R3

VTT T10VTT T11VTT T13

VTT T2VTT T3VTT T5VTT T6VTT T7VTT T9

VTT U1

VTT U11VTT U12VTT U13

VTT U2VTT U3VTT U5VTT U7VTT U8VTT U9

VCC_AXD AU24VCC_AXD AU28VCC_AXD AT23

VCC_AXD AT25VCC_AXD AT29

VCC_AXD AT30

VCC_AXD_NCTF AR29

VCC_AXF A21VCC_AXF B21VCC_AXF B23

VCC_DMI AJ50

VCC_SM_CK BJ23VCC_SM_CK BJ24VCC_SM_CK BK23VCC_SM_CK BK24

VCC_TX_LVDS A43

VCC_HV C40VCC_HV B40

VCC_PEG V49VCC_PEG V50

VCC_PEG W50VCC_PEG W51

VCC_PEG AD51

VCC_RXR_DMI AH50VCC_RXR_DMI AH51

VTTLF A7

VTTLF AH1VTTLF F2

8 OF 10

LVDS

TV/CRT

VTTLF

DMI

PEG

HV

TV

A CK

A SM

SM CK

AXF

A PEG AXD

A LVDS

PLL

CRT

VTT

POWER

U18H

CRESTLINE-GP-U-NF

8 OF 10

LVDS

TV/CRT

VTTLF

DMI

PEG

HV

TV

A CK

A SM

SM CK

AXF

A PEG AXD

A LVDS

PLL

CRT

VTT

POWER

U18H

CRESTLINE-GP-U-NF

12

C547

SCD

1U16V2ZY-2G

P

C547

SCD

1U16V2ZY-2G

P

12

C582

SC4D

7U25

V5KX

-GP

C582

SC4D

7U25

V5KX

-GP

12

C539SC1U16V3ZY-GPC539SC1U16V3ZY-GP

12

C503

SCD

47U

16V3

ZY-3

GP

C503

SCD

47U

16V3

ZY-3

GP

12

TC3

ST22

0U2V

BM-3

GP

TC3

ST22

0U2V

BM-3

GP

12

TC18

ST220U2VBM-3GP

DY TC18

ST220U2VBM-3GP

DY

12

C201SCD

1U16V2ZY-2G

PDYC201SC

D1U

16V2ZY-2GP

DY

12

C581

ST22

U6D

3VBM

-1G

P

C581

ST22

U6D

3VBM

-1G

P

12

C283

SCD

47U

16V3

ZY-3

GP

C283

SCD

47U

16V3

ZY-3

GP

12

C525

SCD

022U16V2KX-3G

P

C525

SCD

022U16V2KX-3G

P

12

C526

SCD

1U16V2ZY-2G

P

C526

SCD

1U16V2ZY-2G

P1

2

C524

SC1U

10V3

KX-3

GP

DY

C524

SC1U

10V3

KX-3

GP

DY

12

C509

SC4D

7U6D

3V3K

X-G

P

C509

SC4D

7U6D

3V3K

X-G

P

12

C281

SCD

1U16V2ZY-2G

P

C281

SCD

1U16V2ZY-2G

P

1 2R311

0R0603-PAD

R311

0R0603-PAD

12


12

C504

SC4D

7U6D

3V3K

X-G

P

C504

SC4D

7U6D

3V3K

X-G

P

12

C205

SC10U10V5KX-2GP

C205

SC10U10V5KX-2GP

12

C512

SC1U

10V3

KX-3

GP

C512

SC1U

10V3

KX-3

GP

12

C519

SCD

22U

16V3

ZY-G

P

DY

C519

SCD

22U

16V3

ZY-G

P

DY

12

C207

SCD

1U16V2ZY-2G

P

C207

SCD

1U16V2ZY-2G

P

12

TC17

ST22

0U2V

BM-3

GP

TC17

ST22

0U2V

BM-3

GP

21

D19

SSM5818SLPT-GP

D19

SSM5818SLPT-GP

12

C198

SCD

1U16V2ZY-2G

P

DYC198

SCD

1U16V2ZY-2G

P

DY

1 2

L29

BLM18AG121SN-1GP

L29

BLM18AG121SN-1GP

12

C218SCD1U16V2ZY-2GPC218SCD1U16V2ZY-2GP

1 2R97

0R0603-PAD

R97

0R0603-PAD

12

C565

SC2D

2U6D

3V3M

X-1-

GPC565

SC2D

2U6D

3V3M

X-1-

GP

12R108

10R2J-2-GP

R108

10R2J-2-GP

12

C571

SCD

47U

16V3

ZY-3

GP

C571

SCD

47U

16V3

ZY-3

GP

12

C562

SCD

22U

16V3

ZY-G

P

C562

SCD

22U

16V3

ZY-G

P

12

C573

SCD

1U16V2ZY-2G

P

C573

SCD

1U16V2ZY-2G

P

12

C527

SCD

1U16V2ZY-2G

P

C527

SCD

1U16V2ZY-2G

P

1 2R102

0R0603-PAD

R102

0R0603-PAD

12

C545

SC1U

10V3

KX-3

GP

C545

SC1U

10V3

KX-3

GP

12

C214

SCD

1U16V2ZY-2G

P

C214

SCD

1U16V2ZY-2G

P

12

C575

SC10U10V5KX-2GP

C575

SC10U10V5KX-2GP

1 2R140

0R0805-PAD

R140

0R0805-PAD

12

C284SC

D47

U16

V3ZY

-3G

PC284

SCD

47U

16V3

ZY-3

GP

12

C288

SC10U

10V5KX-2GP

C288

SC10U

10V5KX-2GP

1 2R143

0R0805-PAD

R143

0R0805-PAD

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VCCSM_LF5

VCC_GMCH1

VCCSM_LF6VCCSM_LF7

VCCSM_LF1VCCSM_LF2VCCSM_LF3VCCSM_LF4

1D05V_S01D05V_S0

1D05V_S0

1D8V_S3

1D05V_S0

1D05V_S0

1D05V_S0

1D05V_S0 3D3V_S0

Title


Date: Sheet of


ME3-DiscreteCRESTLINE(5/6)-PWR/GND

Custom

11 51Monday, July 30, 2007

Title


Date: Sheet of



Custom

11 51Monday, July 30, 2007

Title


Date: Sheet of



Custom

11 51Monday, July 30, 2007

LIB C

12

C54

8SC

10U

10V5

KX-2

GP

C54

8SC

10U

10V5

KX-2

GP

12

C550

SC4D

7U6D

3V3K

X-G

P

C550

SC4D

7U6D

3V3K

X-G

P

12

C47

6SC

1U10

V3KX

-3G

PC

476

SC1U

10V3

KX-3

GP

KA

D29

CH751H-40PT-1GP

D29

CH751H-40PT-1GP

12

C563

SC10U10V5KX-2GP

C563

SC10U10V5KX-2GP

12

TC4

ST22

0U2V

BM-3

GPDY

TC4

ST22

0U2V

BM-3

GPDY

12

C49

5SC

D47

U16

V3ZY

-3G

PC

495

SCD

47U

16V3

ZY-3

GP

12

C510

SCD

22U10V2KX-1G

P

C510

SCD

22U10V2KX-1G

P

12

C55

5SC

1U10

V3KX

-3G

PC

555

SC1U

10V3

KX-3

GP

12

TC12

ST22

0U2V

BM-3

GP

TC12

ST22

0U2V

BM-3

GP

1 2

R305

0R0603-PAD

R305

0R0603-PAD

12

C537

SCD

22U

10V2

KX-1

GP

C537

SCD

22U

10V2

KX-1

GP

12

TC19

ST22

0U2V

BM-3

GP

TC19

ST22

0U2V

BM-3

GP

12

C566

SC10U10V5KX-2GP

C566

SC10U10V5KX-2GP

12

C514

SC22

U6D

3V5M

X-2G

P

C514

SC22

U6D

3V5M

X-2G

P

VCCAT34VCCAT35

VCCAC31VCCAC32

VCCAF32

VCCAH28

VCCAH29VCCAH31VCCAH32

VCCAK32

VCCR30

VCCAJ28VCCAJ31

VCC_SMBE32VCC_SMBE33VCC_SMBE35

VCC_SMAU32VCC_SMAU33VCC_SMAU35VCC_SMAV33VCC_SMAW33VCC_SMAW35VCC_SMAY35VCC_SMBA32VCC_SMBA33VCC_SMBA35VCC_SMBB33VCC_SMBC32VCC_SMBC33VCC_SMBC35VCC_SMBD32VCC_SMBD35

VCC_SMBF33VCC_SMBF34VCC_SMBG32VCC_SMBG33VCC_SMBG35

VCC_SMBJ32VCC_SMBJ33VCC_SMBJ34

VCC_SMBH32VCC_SMBH34VCC_SMBH35

VCC_SMBK32VCC_SMBK33VCC_SMBK34VCC_SMBK35VCC_SMBL33VCC_SMAU30

VCC_AXGAA20VCC_AXGAA23VCC_AXGAA26VCC_AXGAA28

VCC_AXGAA31

VCC_AXGAB21VCC_AXGAB24VCC_AXGAB29VCC_AXGAC20VCC_AXGAC21VCC_AXGAC23VCC_AXGAC24VCC_AXGAC26VCC_AXGAC28VCC_AXGAC29VCC_AXGAD20VCC_AXGAD23VCC_AXGAD24VCC_AXGAD28

VCC_AXGAD31

VCC_AXGAF21VCC_AXGAF26

VCC_AXGAH20VCC_AXGAH21VCC_AXGAH23VCC_AXGAH24VCC_AXGAH26

VCC_AXGR20VCC_AXGT14VCC_AXGW13VCC_AXGW14VCC_AXGY12

VCC_AXGAJ20VCC_AXGAN14

VCC_AXG_NCTF AA16VCC_AXG_NCTF AA17VCC_AXG_NCTF AB16VCC_AXG_NCTF AB19VCC_AXG_NCTF AC16VCC_AXG_NCTF AC17VCC_AXG_NCTF AC19

VCC_SM_LF AW45VCC_SM_LF BC39VCC_SM_LF BE39VCC_SM_LF BD17VCC_SM_LF BD4VCC_SM_LF AW8VCC_SM_LF AT6

VCC_AXG_NCTF T17VCC_AXG_NCTF T18VCC_AXG_NCTF T19VCC_AXG_NCTF T21VCC_AXG_NCTF T22VCC_AXG_NCTF T23VCC_AXG_NCTF T25VCC_AXG_NCTF U15VCC_AXG_NCTF U16VCC_AXG_NCTF U17VCC_AXG_NCTF U19VCC_AXG_NCTF U20VCC_AXG_NCTF U21VCC_AXG_NCTF U23VCC_AXG_NCTF U26VCC_AXG_NCTF V16VCC_AXG_NCTF V17VCC_AXG_NCTF V19VCC_AXG_NCTF V20VCC_AXG_NCTF V21VCC_AXG_NCTF V23VCC_AXG_NCTF V24VCC_AXG_NCTF Y15VCC_AXG_NCTF Y16VCC_AXG_NCTF Y17VCC_AXG_NCTF Y19VCC_AXG_NCTF Y20VCC_AXG_NCTF Y21VCC_AXG_NCTF Y23VCC_AXG_NCTF Y24VCC_AXG_NCTF Y26VCC_AXG_NCTF Y28VCC_AXG_NCTF Y29

VCC_AXG_NCTF AD15VCC_AXG_NCTF AD16VCC_AXG_NCTF AD17VCC_AXG_NCTF AF16VCC_AXG_NCTF AF19VCC_AXG_NCTF AH15VCC_AXG_NCTF AH16VCC_AXG_NCTF AH17VCC_AXG_NCTF AH19VCC_AXG_NCTF AJ16VCC_AXG_NCTF AJ17VCC_AXG_NCTF AJ19VCC_AXG_NCTF AK16VCC_AXG_NCTF AK19VCC_AXG_NCTF AL16VCC_AXG_NCTF AL17VCC_AXG_NCTF AL19VCC_AXG_NCTF AL20VCC_AXG_NCTF AL21VCC_AXG_NCTF AL23VCC_AXG_NCTF AM15VCC_AXG_NCTF AM16VCC_AXG_NCTF AM19VCC_AXG_NCTF AM20VCC_AXG_NCTF AM21VCC_AXG_NCTF AM23VCC_AXG_NCTF AP15VCC_AXG_NCTF AP16VCC_AXG_NCTF AP17VCC_AXG_NCTF AP19VCC_AXG_NCTF AP20VCC_AXG_NCTF AP21VCC_AXG_NCTF AP23VCC_AXG_NCTF AP24VCC_AXG_NCTF AR20VCC_AXG_NCTF AR21VCC_AXG_NCTF AR23VCC_AXG_NCTF AR24

VCC_AXG_NCTF V26VCC_AXG_NCTF V28VCC_AXG_NCTF V29VCC_AXG_NCTF Y31

VCC_AXG_NCTF AR26

6 OF 10

POWER

VCC CORE

VCC SM

VCC GFX NCTF

VCC GFX

VCC SM LF

U18F

CRESTLINE-GP-U-NF

6 OF 10

POWER

VCC CORE

VCC SM

VCC GFX NCTF

VCC GFX

VCC SM LF

U18F

CRESTLINE-GP-U-NF

TP37TP37

12

C549

SCD

22U10V2KX-1G

P

C549

SCD

22U10V2KX-1G

P

VCC_NCTFAK33VCC_NCTFAK35VCC_NCTFAK36VCC_NCTFAK37

VCC_NCTFAL33VCC_NCTFAL35

VCC_NCTFAJ33VCC_NCTFAJ35

VCC_NCTFAJ36VCC_NCTFAM35

VCC_NCTFT30VCC_NCTFT34VCC_NCTFT35VCC_NCTFU29

VCC_NCTFAP35VCC_NCTFAP36VCC_NCTFAR35VCC_NCTFAR36VCC_NCTFY32VCC_NCTFY33VCC_NCTFY35VCC_NCTFY36VCC_NCTFY37

VCC_NCTFAA33VCC_NCTFAA35VCC_NCTFAA36

VCC_NCTFAD33

VCC_NCTFAF36

VCC_NCTFAB33VCC_NCTFAB36VCC_NCTFAB37VCC_NCTFAC33VCC_NCTFAC35VCC_NCTFAC36VCC_NCTFAD35VCC_NCTFAD36VCC_NCTFAF33

VCC_NCTFAH33VCC_NCTFAH35VCC_NCTFAH36VCC_NCTFAH37

VCC_NCTFU31VCC_NCTFU32VCC_NCTFU33VCC_NCTFU35VCC_NCTFU36VCC_NCTFV32VCC_NCTFV33VCC_NCTFV36VCC_NCTFV37

VCC_AXM_NCTFAL24VCC_AXM_NCTFAL26VCC_AXM_NCTFAL28VCC_AXM_NCTFAM26VCC_AXM_NCTFAM28VCC_AXM_NCTFAM29VCC_AXM_NCTFAM31VCC_AXM_NCTFAM32VCC_AXM_NCTFAM33VCC_AXM_NCTFAP29VCC_AXM_NCTFAP31VCC_AXM_NCTFAP32VCC_AXM_NCTFAP33VCC_AXM_NCTFAL29VCC_AXM_NCTFAL31VCC_AXM_NCTFAL32VCC_AXM_NCTFAR31VCC_AXM_NCTFAR32VCC_AXM_NCTFAR33

VSS_NCTF T27VSS_NCTF T37VSS_NCTF U24VSS_NCTF U28VSS_NCTF V31VSS_NCTF V35VSS_NCTF AA19VSS_NCTF AB17VSS_NCTF AB35VSS_NCTF AD19VSS_NCTF AD37VSS_NCTF AF17VSS_NCTF AF35

VSS_NCTF AM17VSS_NCTF AK17

VSS_NCTF AM24VSS_NCTF AP26VSS_NCTF AP28VSS_NCTF AR15VSS_NCTF AR19VSS_NCTF AR28

VSS_SCB A3VSS_SCB B2VSS_SCB C1VSS_SCB BL1VSS_SCB BL51VSS_SCB A51

VCC_AXM AT31VCC_AXM AT33

VCC_AXM AK29

VCC_AXM AJ23VCC_AXM AJ26VCC_AXM AK23VCC_AXM AK24

7 OF 10

POWER

VCC NCTF

VSS NCTF

VSS SCB

VSS AXM

VSS AXM NCTF

U18G

CRESTLINE-GP-U-NF

7 OF 10

POWER

VCC NCTF

VSS NCTF

VSS SCB

VSS AXM

VSS AXM NCTF

U18G

CRESTLINE-GP-U-NF

12

C55

4SC

10U

10V5

KX-2

GP

C55

4SC

10U

10V5

KX-2

GP

12

C574

SC22

U6D

3V5M

X-2G

P

C574

SC22

U6D

3V5M

X-2G

P

12R303

10R2J-2-GP

R303

10R2J-2-GP

TP38TP38

12

C534

SCD

22U10V2KX-1G

PC

534SC

D22U

10V2KX-1GP

12

C516

SCD

1U16V2ZY-2G

PC

516SC

D1U

16V2ZY-2GP

TP32TP32

TP9TP9

12

C49

8SC

1U10

V3KX

-3G

PC

498

SC1U

10V3

KX-3

GP

12

C553

SCD

1U16V2ZY-2G

PC

553SC

D1U

16V2ZY-2GP

12

C529

SCD

1U16V2ZY-2G

PC

529SC

D1U

16V2ZY-2GP

TP36TP36

TP11TP11

12

C56

7SC

D1U

16V2

ZY-2

GP

C56

7SC

D1U

16V2

ZY-2

GP

12

C56

9SC

D1U

16V2

ZY-2

GP

C56

9SC

D1U

16V2

ZY-2

GP

12

C259

SC22

U6D

3V5M

X-2G

P

C259

SC22

U6D

3V5M

X-2G

P

12

C57

6SC

D22

U10

V2KX

-1G

PC

576

SCD

22U

10V2

KX-1

GP

12

C513

SCD

1U16V2ZY-2G

PC

513SC

D1U

16V2ZY-2GP 1

2

C55

7SC

D22

U10

V2KX

-1G

PC

557

SCD

22U

10V2

KX-1

GP

12

C533

SCD

1U16V2ZY-2G

PC

533SC

D1U

16V2ZY-2GP

12

C520

SCD

22U10V2KX-1G

PC

520SC

D22U

10V2KX-1GP

12

C518

SCD

1U16V2ZY-2G

PC

518SC

D1U

16V2ZY-2GP

12

C508

SCD

01U16V2KX-3G

PC

508SC

D01U

16V2KX-3GP

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of



A3

12 51Monday, July 30, 2007

Title


Date: Sheet of



A3

12 51Monday, July 30, 2007

Title


Date: Sheet of



A3

12 51Monday, July 30, 2007

VSSC46VSSC50VSSC7VSSD13VSSD24VSSD3VSSD32VSSD39VSSD45VSSD49VSSE10VSSE16VSSE24VSSE28VSSE32VSSE47VSSF19VSSF36VSSF4VSSF40VSSF50VSSG1VSSG13VSSG16VSSG19VSSG24VSSG28VSSG29VSSG33VSSG42VSSG45VSSG48VSSG8VSSH24VSSH28VSSH4VSSH45VSSJ11VSSJ16VSSJ2VSSJ24VSSJ28VSSJ33VSSJ35VSSJ39VSSK12VSSK47VSSK8VSSL1VSSL17VSSL20VSSL24VSSL28VSSL3VSSL33VSSL49VSSM28VSSM42VSSM46VSSM49VSSM5VSSM50VSSM9VSSN11VSSN14VSSN17VSSN29VSSN32VSSN36VSSN39VSSN44VSSN49VSSN7VSSP19VSSP2VSSP23VSSP3VSSP50VSSR49VSST39VSST43VSST47VSSU41VSSU45VSSU50VSSV2VSSV3

VSS W11VSS W39VSS W43VSS W47VSS W5VSS W7VSS Y13VSS Y2VSS Y41VSS Y45VSS Y49VSS Y5VSS Y50VSS Y11VSS P29VSS T29VSS T31VSS T33VSS R28

VSS AB32VSS AD32VSS AF28VSS AF29VSS AT27VSS AV25VSS H50

VSS AA32

10 OF 10

VSS

U18J

CRESTLINE-GP-U-NF

10 OF 10

VSS

U18J

CRESTLINE-GP-U-NF

VSS AW24VSS AW29VSS AW32VSS AW5VSS AW7VSS AY10VSS AY24VSS AY37VSS AY42VSS AY43VSS AY45VSS AY47VSS AY50VSS B10VSS B20VSS B24VSS B29VSS B30VSS B35VSS B38VSS B43VSS B46VSS B5VSS B8VSS BA1VSS BA17VSS BA18VSS BA2VSS BA24VSS BB12VSS BB25VSS BB40VSS BB44VSS BB49VSS BB8VSS BC16VSS BC24VSS BC25VSS BC36VSS BC40VSS BC51VSS BD13VSS BD2VSS BD28VSS BD45VSS BD48VSS BD5VSS BE1VSS BE19VSS BE23VSS BE30VSS BE42VSS BE51VSS BE8VSS BF12VSS BF16VSS BF36VSS BG19VSS BG2VSS BG24VSS BG29VSS BG39VSS BG48VSS BG5VSS BG51VSS BH17VSS BH30VSS BH44VSS BH46VSS BH8VSS BJ11VSS BJ13VSS BJ38VSS BJ4VSS BJ42VSS BJ46VSS BK15VSS BK17VSS BK25VSS BK29VSS BK36VSS BK40VSS BK44VSS BK6VSS BK8VSS BL11VSS BL13VSS BL19VSS BL22VSS BL37VSS BL47VSS C12VSS C16VSS C19VSS C28VSS C29VSS C33VSS C36VSS C41

VSSA13VSSA15VSSA17VSSA24VSSAA21VSSAA24VSSAA29VSSAB20VSSAB23VSSAB26VSSAB28VSSAB31VSSAC10VSSAC13VSSAC3VSSAC39VSSAC43VSSAC47VSSAD1VSSAD21VSSAD26VSSAD29VSSAD3VSSAD41VSSAD45VSSAD49VSSAD5VSSAD50VSSAD8VSSAE10VSSAE14VSSAE6VSSAF20VSSAF23VSSAF24VSSAF31VSSAG2VSSAG38VSSAG43VSSAG47VSSAG50VSSAH3VSSAH40VSSAH41VSSAH7VSSAH9VSSAJ11VSSAJ13VSSAJ21VSSAJ24VSSAJ29VSSAJ32VSSAJ43VSSAJ45VSSAJ49VSSAK20VSSAK21VSSAK26VSSAK28VSSAK31VSSAK51VSSAL1VSSAM11VSSAM13VSSAM3VSSAM4VSSAM41VSSAM45VSSAN1VSSAN38VSSAN39VSSAN43VSSAN5VSSAN7VSSAP4VSSAP48VSSAP50VSSAR11VSSAR2VSSAR39VSSAR44VSSAR47VSSAR7VSSAT10VSSAT14VSSAT41VSSAT49VSSAU1VSSAU23VSSAU29VSSAU3VSSAU36VSSAU49VSSAU51VSSAV39VSSAV48VSSAW1VSSAW12VSSAW16

9 OF 10

VSS

U18I

CRESTLINE-GP-U-NF

9 OF 10

VSS

U18I

CRESTLINE-GP-U-NF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A ADDR_A_MA11

DDR_A_MA7DDR_A_MA6

DDR_A_RAS#DDR_CS0_DIMMA#

DDR_A_MA4DDR_A_MA2

DDR_A_MA0DDR_A_BS1

M_ODT0DDR_A_MA13

DDR_A_D13

DDR_A_D35

DDR_A_D56

DDR_A_D14DDR_A_D15

DDR_A_D36

DDR_A_D57

DDR_A_D37

DDR_A_D58

DDR_A_D16DDR_A_D17

DDR_A_D38

DDR_A_D59

DDR_A_D39

DDR_A_D60

DDR_A_D18DDR_A_D19

DDR_A_D40

DDR_A_D61

DDR_A_D41

DDR_A_DQS#6

DDR_A_BS1DDR_A_DM4

DDR_A_DQS#7

DDR_A_DM5

DDR_A_DQS0

DDR_A_DM6

DDR_A_D20

DDR_A_DM7

DDR_A_D62

DDR_A_DQS1

ICH_SMBDATA

DDR_A_DQS2

DDR_A_RAS#

DDR_A_DQS3

DDR_A_D0

DDR_A_DQS4

ICH_SMBCLK

DDR_A_DQS5

DDR_A_WE#

DDR_A_DQS6DDR_A_DQS7

M_ODT0

DDR_A_CAS#

DDR_A_D42

M_ODT1

DDR_VREF_S3

DDR_CS0_DIMMA#

DDR_A_MA0

DDR_A_D21

DDR_CS1_DIMMA#

DDR_A_MA1

DDR_CKE0_DIMMA

DDR_A_D63


DDR_CKE1_DIMMA

DDR_A_D43

DDR_A_MA5

M_CLK_DDR0


M_CLK_DDR#0

DDR_A_MA9

DDR_A_D22

M_CLK_DDR1

DDR_A_MA10

DDR_A_MA13

DDR_A_DQS#0

M_CLK_DDR#1

DDR_A_BS2 DDR_A_DM0

DDR_A_DQS#1DDR_A_DQS#2

DDR_A_BS0DDR_A_DM1

DDR_A_DQS#3DDR_A_DQS#4

DDR_A_DM2

DDR_A_D44

DDR_A_DQS#5

DDR_A_DM3

DDR_A_D23

DDR_A_D1DDR_A_D2

DDR_A_D24

DDR_A_D45DDR_A_D46

DDR_A_D3

DDR_A_D25

DDR_A_D47

DDR_A_D4

DDR_A_D26

DDR_A_D5

DDR_A_D48

DDR_A_D27

DDR_A_D6

DDR_A_D49

DDR_A_D28

DDR_A_D7

DDR_A_D50

DDR_A_D29

DDR_A_MA14

DDR_A_D8

DDR_A_D30

DDR_A_D51

DDR_A_D9DDR_A_D10

DDR_A_D31

DDR_A_D52

DDR_A_D11

DDR_A_D32

DDR_A_D53

DDR_A_D33

DDR_A_D12

DDR_A_D54

DDR_A_D34

DDR_A_D55

DDR_A_BS0DDR_A_MA10

DDR_A_MA12DDR_A_MA9

DDR_A_MA3DDR_A_MA1

DDR_CKE1_DIMMA DDR_A_MA14

DDR_A_MA5DDR_A_MA8

DDR_A_WE#

DDR_A_MA12DDR_A_MA11

DDR_CKE0_DIMMADDR_A_BS2

M_ODT1DDR_A_CAS#

DDR_CS1_DIMMA#

1D8V_S3

DDR_VREF_S0

DDR_VREF_S0

1D8V_S3

3D3V_S0

DDR_VREF_S3

DDR_A_DQS#[0..7]8

DDR_A_D[0..63]8

DDR_A_DM[0..7]8

DDR_A_DQS[0..7]8

DDR_A_MA[0..13]8

DDR_A_BS[0..2]8

M_CLK_DDR#0 7

M_ODT07

DDR_CKE1_DIMMA 7

DDR_CS0_DIMMA# 7

M_CLK_DDR#1 7M_CLK_DDR1 7

DDR_CKE0_DIMMA 7

DDR_A_WE# 8DDR_A_CAS# 8

DDR_CS1_DIMMA# 7

M_CLK_DDR0 7

DDR_A_RAS# 8

M_ODT17

ICH_SMBDATA 3,14,20

PM_EXTTS#0 7

ICH_SMBCLK 3,14,20

DDR_A_MA147

Title


Date: Sheet of


DDRII-SODIMM SLOT1Custom

13 51Wednesday, August 15, 2007ME3-Discrete

Title


Date: Sheet of




Title


Date: Sheet of




Layout Note:Place these resistorsclosely DM1,alltrace length Max=1.5"

Layout Note:Place near DM1

Layout Note:Place one cap close to every 2 pullupresistors terminated to +0.9VS

12

C223

SC2D

2U16V5ZY-2G

P

C223

SC2D

2U16V5ZY-2G

P

123


123


12

C231

SCD

1U16V2ZY-2G

P

C231

SCD

1U16V2ZY-2G

P

12

C228

SCD

1U16V2ZY-2G

P

DY

C228

SCD

1U16V2ZY-2G

P

DY

12

C234

SCD

1U16V2ZY-2G

P

C234

SCD

1U16V2ZY-2G

P

12

C497

SCD

1U16V2ZY-2G

P

DY

C497

SCD

1U16V2ZY-2G

P

DY

12 3


12

C219

SCD

1U16V2ZY-2G

P

C219

SCD

1U16V2ZY-2G

P

12

C227

SCD

1U16V2ZY-2G

P

C227

SCD

1U16V2ZY-2G

P

A0102A1101A2100A399A498A597A694A792A893A991A10/AP105A1190A1289A13116A1486A1584A16/BA285

BA0107BA1106

DQ05DQ17DQ217DQ319DQ44DQ56DQ614DQ716DQ823DQ925DQ1035DQ1137DQ1220DQ1322DQ1436DQ1538DQ1643DQ1745DQ1855DQ1957DQ2044DQ2146DQ2256DQ2358DQ2461DQ2563DQ2673DQ2775DQ2862DQ2964DQ3074DQ3176DQ32123DQ33125DQ34135DQ35137DQ36124DQ37126DQ38134DQ39136DQ40141DQ41143DQ42151DQ43153DQ44140DQ45142DQ46152DQ47154DQ48157DQ49159DQ50173DQ51175DQ52158DQ53160DQ54174DQ55176DQ56179DQ57181DQ58189DQ59191DQ60180DQ61182DQ62192DQ63194

DQS0#11DQS1#29DQS2#49DQS3#68DQS4#129DQS5#146DQS6#167DQS7#186

DQS013DQS131DQS251DQS370DQS4131DQS5148DQS6169DQS7188

OTD0114OTD1119

VREF1VSS2

GND202

RAS# 108WE# 109

CAS# 113

CS0# 110CS1# 115

CKE0 79CKE1 80

CK0 30CK0# 32

CK1 164CK1# 166

DM0 10DM1 26DM2 52DM3 67DM4 130DM5 147DM6 170DM7 185

SDA 195SCL 197

VDDSPD 199

SA0 198SA1 200

NC#50 50NC#69 69NC#83 83

NC#120 120NC#163/TEST 163

VDD 81VDD 82VDD 87VDD 88VDD 95VDD 96VDD 103VDD 104VDD 111VDD 112VDD 117VDD 118

VSS 3VSS 8VSS 9VSS 12VSS 15VSS 18VSS 21VSS 24VSS 27VSS 28VSS 33VSS 34VSS 39VSS 40VSS 41VSS 42VSS 47VSS 48VSS 53VSS 54VSS 59VSS 60VSS 65VSS 66VSS 71VSS 72VSS 77VSS 78VSS 121VSS 122VSS 127VSS 128VSS 132VSS 133VSS 138VSS 139VSS 144VSS 145VSS 149VSS 150VSS 155VSS 156VSS 161VSS 162VSS 165VSS 168VSS 171VSS 172VSS 177VSS 178VSS 183VSS 184VSS 187VSS 190VSS 193VSS 196

GND 201

MH1MH1 MH2 MH2

DM2

DDR2-200P-20-GP-U

DM2

DDR2-200P-20-GP-U

123


12

C250

SC2D

2U16V5ZY-2G

P

DY

C250

SC2D

2U16V5ZY-2G

P

DY

12

C483

SCD

1U16V2ZY-2G

P

DY

C483

SCD

1U16V2ZY-2G

P

DY

12

C502

SCD

1U16V2ZY-2G

P

DY

C502

SCD

1U16V2ZY-2G

P

DY

12 3

4RN19 SRN56J-4-GPRN19 SRN5

ME3 Block Diagram Intel CPU Project code : 91.4X601.001...

Documents

Transcript of ME3 Block Diagram Intel CPU Project code : 91.4X601.001...