“DESIGN AND IMPLEMENTATION OF BOLT-BERANEK-NEWMAN (BBN) BUTTERFLY IN REALIZATION OF A MULTIPROCESSOR

SYSTEM”

Project Submitted by Pallab Kumar Ray Roll No. ME CSE 2014-10001 Registration No. 2324 of 2010-11

Under the Guidance of SOMAK DAS Assistant Professor Department Of Computer Science & Engineering University Institute of Technology The University of Burdwan

Introduction

• The BBN Butterfly was a massively parallel computer built by Bolt, Beranek and Newman in the 1980s.

• Each machine had up to 512 CPUs, each processing node in the Butterfly has a 16-bit user-micro programmable bit-slice control processor, based on the AMD 2901 which could be connected to allow every CPU access to every other CPU's memory, although with a substantially greater latency (roughly 15:1) than for its own. The CPUs were commodity microprocessors. The memory address space was shared [1].

16-port Butterfly switchFigure shows NUMA machine, the BBN Butterfly. In this design, each CPU is coupled directly to one memory. Each of small squares in this Figure represents a CPU plus memory pair. The CPUs are wired up via eight switches, each having four input ports and four output ports. Local memory requests are handled directly; remote requests are turned into request packets and sent to the appropriate memory via switching network. Here, too programs can run remotely, but at a tremendous penalty in performance [3].

Butterfly Processing Node• each processing node in the Butterfly has a 16-bit user-micro programmable bit-slice control processor, based on

the AMD 2901, known as the Processor Node Controller (PNC)• The local memory associated with each processing node consists of 1 Mbyte of dynamic memory, expandable to

4 Mbyte with the addition of a daughter board. Each processing node also has a bi-directional interface to the Butterfly Switch, and its own private Input-Output bus.

• The basic I/O functionality of the CPU has been implemented in the CPU.v module. Each CPU also has an associated 256-byte memory, and a MMU to translate from global to local addresses. We have implemented a 16-node Butterfly system with 4KB of shared-memory

The Routing Function A composite sequence of permutations,  Bn

i, which is applied to an input packet n-bit destination label D = {dn... d1}. intermediate label given by P = {pn, ..., p1}The radix determines how many channels are switched within a single switch node, and this is given by c = 2i. number of active stages in the network is given by s = log2

i N = n/i for an N-port Butterfly switch. D when at an intermediate label P . Exchange permutation perform

Eni (<P, D>)= <{pn, pn-1, ..., pi+1, di, di-1, ..., d1} , {di,, di-1, ..., d1, dn, dn-1, ..., di+1}>

and the shuffle permutation applied to the connections from stage k to stage k+1 is then Sn,ik (<P, D>) =

<σn-(n-ik) (P), D>

where σn-x(P) is the xth inverse sub-shuffle applied to P. This permutation is defined formally as

σ-(n-ik)n(P) = {pn, pn-1, ..., pik+1, pi, pi-1, ..., p1, pik, pik-1, ..., pi+1}

Eni and Sn,

ik map from <P, D> to <P', D'>, where P and P' entry and exit labels of the packet  D and D' are

the target (destination) labels before and after the routing.

The Butterfly switch as a whole can now be defined as the composition of Eni and Sn,

ik over n/i stages, thus

Bni = (En

i Sn,ik)n/i

k=l [2].

Implementing BBN ButterflyThere is 4x4 switches. 4 switches are for input those are A0, A1,A2,A3 and the output switch is B0, B1,B2,B3. In every switch there are 4 CPU means total 4x4 =16 CPUs connected for input switch and those 16 CPUs are connected for output. The data is passed through the interconnection line in both 4x4 switches. When the given address is ask to CPU then the data of the address is given as output. The BBN Butterfly the output port of given switches are connected to another switch.

Theory for Inter Switch Connections of BBN ButterflyThe output of each of the 16 CPUs are connected to the group A switches. While the output of the group B switches are connected to the input of CPUs.

the interconnections between the CPUs and group A switches can be summarized by following equations

Where ( 0 <= P < 16 ) and ‘/’ represents integer division

Example : where P=11 ; input port 3 of switch A2

The inter connection between the CPUs and Group B switches can be summarized by the following equations

Where P= 0 to 15

Example : p= 13 ; output as B3 and from port 1

The interconnection between group A and Group B switches can be represent by the equation

Where 0<= n and i< 4

Example : output as B3 input port 1 . Where 0<= n and i<4

Block Diagram

There is 16 bit address and Data input line in this block diagram. Also 4 bit request CPU address that which CPU is asked to give the output among those 16 CPUs and 1 enable switch and 1 read/write switch that data can be read or write the data.

In this block diagram there is 16 bit output data line.

Generated Expected Simulation Result of BBN Butterfly

Simulation Behavioral model of BBN Butterfly

Conclusion and Future Scope

The BBN Butterfly family can support a distributed memory multicomputer environment in which communication are conduct by message-passing through the network. The parallel task may be distributed and processed without regard to the physical location of with the tasks using the uniform system as a parallel programming environment . In this BBN butterfly network there is use 16 CPUs. The memory take by the BBN network is 256 kb to 4 MB. BBN network will make using 128 CPUs. The memory for the BBN network (128 *256 kb) that is 32,768 kb up to (128*4 mb) 512.

Reference[1] Architecture of High Performance Computers Volume II Array processors and multiprocessor by by R. IBBETT

[2] Distributed Operating System by Andrew S. Tanenbum

[3] Architecture of High Performance Computers Volume II Array processors and multiprocessor by by R. IBBETT

Thank you