MCS51 - part 1. Lecture 1 2/47 Architecture MCS51 Addressing spaces & modes Instruction list.

MCS51 - part 1

Lecture 1 2/47

Architecture MCS51

Addressing spaces & modes

Instruction list

History 3/47

1980

1990

MCS48 family8048/49/508020/21/22

6MHz

1983

MCS51 family8051/5212MHz

1976

8085MCS96 family

families: MCS151 MCS251

Architecture MCS51 4/47

Features: 8-bit CPU; built-in bit-processor; 255 instructions, including fast multiplying & dividing 1B×1B, 1B/1B; built-in clock generator;32 I/O lines; built-in data memory SRAM of 128B; built-in 4kB of program memory ROM (8051) or EPROM (8751); 64kB of external data memory space (RAM); 64kB of external program memory space (ROM,EPROM); 2 16b timers/counters; built-in bidirectional serial port; priority & vector interrupt system.


Structure of 8051

128B SRAM reg. P2

RAM addr.reg.

PC incrementer

PC reg.

DPTR reg.

clock gen.

instr. reg. & decoder

control unit

XTAL1 XTAL2

PSENALE

EARST

Acc

PSW

TMP1 TMP2

ALU

reg. B

reg. P1

PCON SCON SBUFTCONTH0 TL0

TH1 TL1 TMOD

IP IE SP

interrupts, serial port timer/counters

reg. P0

reg. P3

4kBROM

programme addr. reg.

P1.7 ... P1.0 P3.7 ... P3.0

P0.7 ... P0.0 P2.7 ... P2.0Vcc GND

SFR


Structure of 8052

256B SRAM

reg. P2RAM

addr.reg.

PC incrementer

PC reg.

DPTR reg.

clock gen.

instr. reg. & decoder

control unit

XTAL1 XTAL2

PSENALE

EARST

Acc

PSW

TMP1 TMP2

ALU

reg. B

reg. P1

PCON SCON SBUFTCONTH0 TL0

TH1 TL1 TMOD

IP IE SP

interrupts, serial port timer/counters

reg. P0

reg. P3

8kBROM

programme addr. reg.

P1.7 ... P1.0 P3.7 ... P3.0

P0.7 ... P0.0 P2.7 ... P2.0Vcc GND

SFR

TH2 TL2 T2CONRCAP2H RCAP2L


Standard packages of 8051/52


Memory spaces of MCS51

0FFFFh

externalRAM

0000h

internalRAM

ROM ext. ROM int.

0000h

0FFFFh

externalROM

ROMMAXEA=0 EA=1

0FFh

80h

bank #000h

bank #108h

bank #210h

bank #318h

7Fh 78h bits direct

addressable 07h 00h

2Fh

20h

RAM

7Fh

30h

additionalRAM SFR

program start address = 0000h

addresses = k*8+3 - interrupt vectors

Architecture MCS51 - working registers 9/47

Register banks

RAM bytes of address range: 00h..1Fh are available as 4 register banks:

R000h: R101h: R202h: R303h: R404h: R505h: R606h: R707h:

bank00R008h: R109h: R20Ah: R30Bh: R40Ch: R50Dh: R60Eh: R70Fh:

bank01R010h: R111h: R212h: R313h: R414h: R515h: R616h: R717h:

bank10R018h: R119h: R21Ah: R31Bh: R41Ch: R51Dh: R61Eh: R71Fh:

bank11

Active bank number is store in bits RS1,RS0 in PSW.

Typical application of register banks is interrupt service..

Architecture MCS51 - direct addressable bits 10/47

Direct addressable bits

They are stored in fragment of internal RAM and some SFR registers.

They are accessible for bit instructions.

They act as 1-bit logic variables.

Bits of RAM byte from 20h to 2Fh have direct addresses from 0 to 127,

according to formula:

bit_addr = (byte_addr - 20h)*8 + position_in_byte

In SFR, direct addressable bits are placed in registers,

which addresses equals multiple 8 (example 80h, C8h).

Architecture MCS51 - SFR 11/47

SFR - special function registers:

• address space: from 80h to 0FFh;

• registers control: - access to built-in devices; - processor work; - interrupt system;

• extensive address using in standard (8051) allows to design many different extensions (additional devices);

• registers defined by Intel as 8051 standard, have the same addresses in other members of MCS51 family.

... - PT2 BD PS BC ...IP B8h

bitnot implemented

italic -additional object

in 8052

address of direct

addressable bit

register address in SFR

register name

bitname


P2.7 A7 P2.6 A6 P2.5 A5 P2.4 A4 P2.3 A3 P2.2 A2 P2.1 A1 P2.0 A0P2 A0h

EA AF - AE ET2 AD ES AC ET1 AB EX1 AA ET0 A9 EX0 A8IE A8h

P3.7 B7 P3.6 B6 P3.5 B5 P3.4 B4 P3.3 B3 P3.2 B2 P3.1 B1 P3.0 B0P3 B0h

- BF - BE PT2 BD PS BC PT1 BB PX1 BA PT0 B9 PX0 B8IP B8h

TF2 CF EXF2CE RCLKCD TCLKCC EXEN2CB TR2 CA C/T2 C9 CP/RL2C8T2CON C8h

CAhRCAP2LCBhRCAP2HCChTL2CDhTH2

CY D7 AC D6 F0 D5 RS1 D4 RS0 D3 OV D2 - D1 P D0PSW D0h

A.7 E7 A.6 E6 A.5 E5 A.4 E4 A.3 E3 A.2 E2 A.1 E1 A.0 E0A E0h

B.7 F7 B.6 F6 B.5 F5 B.4 F4 B.3 F3 B.2 F2 B.1 F1 B.0 F0B F0h


P0.7 87 P0.6 86 P0.5 85 P0.4 84 P0.3 83 P0.2 82 P0.1 81 P0.0 80P0 80h81hSP82hDPL83hDPH

SMOD - - - GF1 GF0 PD IDLPCON 87h

TF1 8F TR1 8E TF0 8D TR0 8C IE1 8B IT1 8A IE0 89 IT0 88TCON 88hGATE C/T M1 M0 GATE C/T M1 M0TMOD 89h

8AhTL08BhTL18ChTH08DhTH1

P1.7 97 P1.6 96 P1.5 95 P1.4 94 P1.3 93 P1.2 92 P1.1 91 P1.0 90P1 90h

SM0 9F SM1 9E SM2 9D REN 9C TB8 9B RB8 9A TI 99 RI 98SCON 98h99hSBUF

Architecture MCS51 - SFR - PSW 14/47

CY D7 AC D6 F0 D5 RS1 D4 RS0 D3 OV D2 - D1 P D0PSW D0h

CY - carry flag

AC - auxiliary carry flag (during adding from bit 3rd to bit 4th)

F0 - user flag

OV - arithmetic overflow flag

P - parity flag (parity of ones in ACC)

RS1,RS0 - register bank select bits: RS1,RS0 = 00 01 10 11 active bank 0 1 2 3

There is no zero flag! Conditional jump instructions: JZ, JNZ directly check the accumulator.

Architecture MCS51 - SFR - A, B 15/47

Used by ALU.

It contains direct addressable bits.

Used during access to external data memory.

A.7 E7 A.6 E6 A.5 E5 A.4 E4 A.3 E3 A.2 E2 A.1 E1 A.0 E0A E0h

B.7 F7 B.6 F6 B.5 F5 B.4 F4 B.3 F3 B.2 F2 B.1 F1 B.0 F0B F0h

Additional working registers.

Use in multiplication and dividing instructions.

It contains direct addressable bits.

Architecture MCS51 - SFR - SP i stos 16/47

81hSP

Addresses the top of stack - points the last written byte.

After reset it has value 07h !

Stack

Acts only in internal RAM (! limited area).Writing to stack moves the top of the stack to the higher addresses, reading - vice versa.! Writing can cause overlapping the stack on lowest RAM addresses.

2BhB:

11hA:

58hSP:

x59h:0Dh58h:34h57h:

x5Ah:

RAM

stac

k

PUSH B

stac

k

59h

2BhPOP A

stac

k

58h

2Bh2Bh

MCS51 acting - adressing modes 17/47

Addressing modes for byte-operands

• immediately instr. code argument

mov r6,#130

• register operand instr. codeRx:

mov a,r6

• direct instr. code operandaddress

intern.RAM

inc 20h


• register indirectint./ext.RAM

address8binstr. code operandR0/R1:

address16binstr. code

DPTR:ext.

RAM

operand

mov b,@r0movx @r1,a

movx a,@dptr

• index-relative

PC/DPTR:

d

instr. code operandROM

base

A:

movc a,@a+dptrmovc a,@a+pc

Addressing mode for bit-operands

• direct instr. code

internalRAM

mov c,20h

address


ROM ext. ROM int.

0000h

0FFFFh

externalROM

ROMMAXEA=0 EA=1

0FFh

80h

bank #000h

bank #108h

bank #210h

bank #318h

7Fh 78h bits direct

addressable 07h 00h

2Fh

20h

RAM

7Fh

30h

additionalRAM SFR

register indirect

direct

register

bit-direct

register indirect by DPTR

register indirect by R0/R1

0FFFFh

externalRAM

0000h

internalRAM

index-relative

addressing modes - ranges of usage


Instruction list MCS51 21/47

A D D A ,R r

A D D A ,d ir

A D D A ,@ R j

A D D A ,# d 8

A := A + R r

A := A + d ir

A := A + in tR A M ( R j)

A := A + d 8

R r= R 0 ,R 1 ,R 2 ,R 3 ,R 4 ,R 5 ,R 6 ,R 7

d ir = d ire c t a d d re s s o f in t . R A M

R j= R 0 ,R 1

d 8 = 1 B im m e d ia te d a ta

C Y A = 2 9 R 0 = 7 1 A C P O V

x 0 0 0 1 1 1 0 1 b e fo re 0 1 0 0 0 1 1 1 x 0 x

a d d a ,r0

0 0 1 1 0 0 1 0 0 a f te r 0 1 0 0 0 1 1 1 1 1 0

A = 1 0 0

1. Arithmetic instructions


ADDC A,Rr

ADDC A,dir

ADDC A,@Rj

ADDC A,#d8

A:=A+Rr+CY

A:=A+dir+CY

A:=A+intRAM(Rj)+CY

A:=A+d8+CY

CY A = 100 R1 = 30 AC P OV

0 01100100 before 00011110 1 1 0

addc a,r1

0 10000010 after 00011110 1 0 1

A = -126

CY A = 100 R1 = 30 AC P OV

1 01100100 before 00011110 1 1 0

addc a,r1

0 10000011 after 00011110 1 1 1

A = -125


SUBB A,Rr

SUBB A,dir

SUBB A,@Rj

SUBB A,#d8

A:=A-Rr-CY

A:=A-dir-CY

A:=A-intRAM(Rj)-CY

A:=A-d8-CY

CY A = -125 AC P OV

1 10000011 before 1 1 1

subb a,#-10 ; (-125)-(-10)-1

1 10001100 after 1 1 0

A = -116

CY A = 125 AC P OV

0 01111101 before 1 0 1

subb a,#15 ; (125)-(15)-0

0 01101110 after 1 1 0

A = 110


I N C a r g a r g : = a r g + 1 a r g = A , R r , d i r , @ R j

D E C a r g a r g : = a r g - 1 a r g = A , R r , d i r , @ R j

I N C D P T R D P T R : = D P T R + 1

D A A d e c i m a l a d j u s t o f A ( o n l y a f t e r a d d i t i o n )

M U L A B B A : = A * B p r o d u c t w i t h o u t s i g n

C Y A = 1 0 0 B = 3 0 A C P O V

x 0 1 1 0 0 1 0 0 b e f o r e 0 0 0 1 1 1 1 0 x 1 x

m u l a b

0 1 0 1 1 1 0 0 0 a f t e r 0 0 0 0 1 0 1 1 0 0 1

B A = 3 0 0 0

D I V A B A : = A / B , B : = A m o d B


2. Logic instructions

A N L A ,R r A := A R r R r= R 0 ,R 1 ,R 2 ,R 3 ,R 4 ,R 5 ,R 6 ,R 7

A N L A ,d ir A := A d ir d ir= d ire c t a d d re ss o f in t. R A M

A N L A ,@ R j A := A in t.R A M (R j) R j= R 0 ,R 1

A N L A ,# d 8 A := A d 8 d 8 = 1 B im m e d ia te d a ta

A N L d ir ,A d ir := d ir A

A N L d ir ,# d 8 d ir := d ir d 8

A = 8 3 h A C P O V C Y

1 0 0 0 0 0 11 be fo re x 1 x x

an l a ,# 0 F h ;

0 0 0 0 0 0 11 a fte r x 0 x x

A = 0 3 h


O R L A ,R r A := A R r

O R L A ,d ir A := A d ir

O R L A ,@ R j A := A in t.R A M (R j)

O R L A ,# d8 A := A d8

O R L d ir ,A d ir := d ir A

O R L d ir ,#d8 d ir := d ir d8

A = 83h A C P O V C Y

10000011 befo re x 1 x x

o rl a ,#23h ;

10100011 a fter x 0 x x

A = 0A 3h


X R L A ,R r A := A R r x y = /x y x /y

X R L A ,d ir A := A d ir

X R L A ,@ R j A := A in t.R A M (R j)

X R L A ,# d 8 A := A d 8

X R L d ir ,A d ir := d ir A

X R L d ir ,# d 8 d ir := d ir d 8

A = 8 3 h A C P O V C Y

1 0 0 0 0 0 11 befo re x 1 x x

xrl a ,# 0 Fh ;

1 0 0 0 1 1 0 0 a fte r x 1 x x

A = 8 C h


mov P1,#0FEh

repeat: xrl P1,#03h

sjmp repeat

mov P1,#0FEh

repeat: cpl P1.0

cpl P1.1

sjmp repeat

P1:=11111110

rectangular waveform

on P1.0 & P1.1 (opposite states)

CLR A A:=0

CPL A A:=not A

Example:


3. Rotation instructionsRL A

RLC A

RR A

RRC A

SWAP A A7..4 A3..0

CY 7 A 0

7 A 0

7 A 0

CY 7 A 0

7 6 5 4 3 2 1 0


4. Bit instructions

CLR C CY:=0

CLR bit bit:=0 bit - direct addressable bit

CPL C CY:=not CY

CPL bit bit:=not bit

ANL C, bit CY:=CY bit

ANL C,/bit CY:=CY (not bit)

ORL C, bit CY:=CY bit

ORL C,/bit CY:=CY (not bit)

MOV C,bit CY bit

MOV bit,C bit CY


5. Transfer instructions

MOV A,Rr A Rr Rr=R0,R1,R2,R3,R4,R5,R6,R7

MOV A,dir A dir dir= direct address of int.RAM

MOV A,@Rj A int.RAM(Rj) Rj=R0,R1

MOV A,#d8 A d8 d8=1B immediate data

MOV Rr,A Rr A

MOV Rr,dir Rr dir

MOV Rr,#d8 Rr d8

MOV dir,A dir A

MOV dir,Rr dir Rr

MOV dir,@Rj dir int.RAM(Rj)

MOV dir,#d8 dir d8

MOV dird,dirs dird dirs dird,dirs = dir


M O V @ R j,A R A M w ( R j) A

M O V @ R j,d ir R A M w ( R j) d ir

M O V @ R j,# d 8 R A M w ( R j) d 8

S B U FT L 0

A

m o v r0 ,# 8 6 h m o v @ r0 ,A

8 6 h :8 5 h :

7 D h :

7 9 h :7 8 h :

m o v r1 ,# 8 5 h m o v B ,@ r1

B

m o v 7 9 h ,7 D h

m o v 7 8 h ,S B U F m o v T L 0 ,7 9 h

R A M w


MOV DPTR,#d16 DPTR d16 d16=2B immediate data

MOVC A,@A+DPTR A ROM(DPTR+A)

MOVC A,@A+PC A ROM(PC+A)

201h:

203h:

206h:207h:208h:

20Ah:

210h:

212h:

ROM

mov a,#2

mov dptr,#210h

movc a,@a+dptr ;1)

movc a,@a+pc ;2)

ajmp 300h

A

7402900210938371000A

::

101112

2)

1)


M O V X A ,@ D P T R A e x t.R A M (D P T R )

M O V X @ D P T R ,A e xt.R A M (D P T R ) A

M O V X A ,@ R j A e x t.R A M (R j)

M O V X @ R j,A e xt.R A M (R j) A

R A M z

AA

0 0 8 0 h:

1 0 9 0 h :

m o v r0 ,# 8 0 hm o v p 2 ,# 0m o vx @ r0 ,a

m o v d p t r ,# 1 0 9 0 hm o vx @ d p tr ,a

m o v d p t r ,# 8 0 hm o vx a ,@ d p tr

m o v r1 ,# 9 0 hm o v p 2 ,# 1 0 hm o vx a ,@ r1


X C H A , R r A R r

X C H A , d i r A d i r

X C H A , @ R j A i n t . R A M ( R j )

i n t . R A M

A R 3x c h a , r 3

A

m o v r 1 , # 4 0 h x c h d a , @ r 1 4 0 h :

X C H D A , @ R j A 3 . . 0 i n t . R A M ( R j ) 3 . . 0

P U S H d i r S P : = S P + 1 , i n t . R A M ( S P ) d i r

P O P d i r d i r i n t . R A M ( S P ) , S P : = S P - 1

N O P n o o p e r a t e


AJMP a11 PC10..0 a11 a11-address inside actual 2kB program page

LJMP a16 PC a16 a16-full address

JMP @A+DPTR PC:=DPTR+A, A=0..255

; example of switched-jump implementation; Assume: jump number (0..k) placed in A

.........RL A ; k:=k*2MOV DPTR,#jmptab ;DPTR table containing jump addressesJMP @A+DPTR.........

jmptab: AJMP proc0AJMP proc1.........AJMP prock.........

6. Jump instructions


SJMP r8 PC:=PC+r8 r8:= -128..127

JZ r8 if A=0 then PC:=PC+r8

JNZ r8 if A0 then PC:=PC+r8

JC r8 if CY=1 then PC:=PC+r8

JNC r8 if CY=0 then PC:=PC+r8

JB bit,r8 if bit=1 then PC:=PC+r8

JNB bit,r8 if bit=0 then PC:=PC+r8

JBC bit,r8 if bit=1 then (PC:=PC+r8, bit:=0)

CJNE arg1,arg2,r8 if arg1 < arg2 then CY:=1 else CY:=0 possible:if arg1 arg2 then PC:=PC+r8 arg1 arg2 A dir A #d8 Rr #d8 @Rj #d8

DJNZ arg,r8 arg := arg-1 arg = Rr, dirif arg 0 then PC:=PC+r8

ACALL a11 SP:=SP+1, RAMw(SP) PCL,SP:=SP+1, RAMw(SP) PCH

PC10..0 a11 a11- address inside actual 2kB program page

LCALL a16 SP:=SP+1, RAMw(SP) PCL,SP:=SP+1, RAMw(SP) PCH

PC a16 a16-full address

RET PCH RAMw(SP), SP:=SP-1

PCL RAMw(SP), SP:=SP-1

RETI PCH RAMw(SP), SP:=SP-1

PCL RAMw(SP), SP:=SP-1,

enabling interrupts

7. Call & return instructions


instruction type CY AC OV P commentz z z z any instruction using PSW as memory byte or set of bits

z any instruction changing AADD A,...ADDC A,...

z z z z CY - overflow after adding in NBOV- overflow after adding in U2

SUBB A,... z z z z CY - needed borrow for bit #7OV - overflow after subtracting in U2

MUL AB 0 z z OV - set if product > 255DIV AB 0 z z OV - set if divisor = 0DA A z zRRC ARLC A

z z

CJNE arg1,arg2 z CY:=1 if arg1 < arg2CLR C 0 CY:=0CPL C z CY:=not CYSETB C 1 CY:=1ANL C,... z according to resultORL C,... z according to resultMOV C,... z according to result

8. Influence of instructions on PSW state


MCS51 - programming examples 40/47; Procedure converting 1B NB number in Acc into 2 ASCII chars (hexadecimal digits); parameters: A = number;; R1 -> buffer for chars;; results: M(R1),M(R1+1) = 2 ASCII chars;; changes: A, R1:=R1+2;; length: 32B;; execution time: 28-30 m.c.TOASCII:PUSH B ;B stored on stack MOV B,#16 DIV AB ;A:=A/16, B:=A mod 16 ORL A,#30H ;generating ASCII char CJNE A,#3AH,TA1 ;for higher hex digit.TA1: JC TA2 ;jump if char = ‘0’..’9’ ADD A,#7 ;modification of char codeTA2: MOV @R1,A ;char to buffer INC R1 ;next position in buffer MOV A,B ORL A,#30H ;generating ASCII char CJNE A,#3AH,TA3 ;for lower hex digitTA3: JC TA4 ;jump if char = ‘0’..’9’ ADD A,#7 ;modification of char codeTA4: MOV @R1,A ;char to buffer INC R1 ;next position in buffer POP B ;restoring reg. B RET

MCS51 - programming examples 41/47

; Procedure of program time delay. ; parameters: R7 = delay constant; ; results: procedure execution time depends on R7 value; ; changes: PSW, R7:=0; ; length: 12B; ; execution time: 10+6*R7 m.c. ; (component 10 caused by: PUSH, POP & RET; factor 6 caused by MUL & DJNZ); ; stack usage: 4. DELAY: PUSH ACC ;A & B stored on stack PUSH B DELAY1: MUL AB ;delay loop DJNZ R7,DELAY1 POP B ;restoring B & A POP ACC RET example of use (additional 1+2 m.c.): MOV R7,#100 ;R7=delay coefficient ACALL DELAY


; Procedure of program time delay. ; parameters: R7 = delay constant; ; results: procedure execution time depends on R7 value; ; changes: PSW, R7:=0; ; length: 7B; ; execution time: 2+6*R7c.m. ; (component 2 is caused by RET; factor 6 is caused by 4xNOP i DJNZ). ; stack usage: 2 DELAY: NOP ;delay loop NOP NOP NOP DJNZ R7,DELAY RET example of use (additional 1+2 m.c.): MOV R7,#100 ;R7=delay coefficient ACALL DELAY


; Part of programme with swith-jump.

; switch-parameter placed in accumulator. ..... RL A ;parameter value twiced MOV DPTR,#JMPTAB JMP @A+DPTR .....JMPTAB: AJMP PROC1 AJMP PROC2 .... AJMP PROCN


; Procedure converting binary number from Acc ; into 3 separated BCD digits in buffer. ; parameters: A = number; ; R0 -> buffer for BCD digits ; results: M(R0),M(R0+1),M(R0+2) = 3 BCD digits; ; changes: A, R0:=R0+2; ; length: 21B; ; execution time: 25 m.c. TOBCD: PUSH B ;storing reg. B on stack MOV B,#100 DIV AB ;A=hundreds digit MOV @R0,A ;digit to buffer INC R0 MOV A,B MOV B,#10 DIV AB ;A=tens digit, B=ones digit MOV @R0,A ;digits to buffer INC R0 MOV @R0,B POP B ;restoring reg. B RET


; Procedure adding 2B numbers in BCD; LSB placed on lower addresses.; parameters: R0 -> number1;; R1 -> number2;; results: M(R0),M(R0+1) = number1+ number2;; changes: PSW, R1:=R1+1, R0:=R0+1;; length: 16B;; execution time: 17 m.c.DODBCD: PUSH ACC ;storing A on stack CLR C MOV A,@R0 ;A:=LSB of number1 ADD A,@R1 ;adding LSB of number2 DA A ;decimal adjust MOV @R0,A ;LSB of sum INC R0 ;next bytes of numbers INC R1 MOV A,@R0 ;A:=MSB of number1 ADDC A,@R1 ;adding MSB of number2 DA A ;decimal adjust MOV @R0,A ;MSB of sum POP ACC ;restoring reg. A RET ;CY=1 means overflow


; Program reading timer during counting.; Timer state can change between two reads of lower and higher byte of timer;; ..... MOV R1,TH0 ;R1:=MSB of timer MOV R0,TL0 ;R0:=LSB of timer MOV A,TH0 ;repeated read of TH0 XRL A,R1 ;is it the same as previous JZ RDOK ;jump if the same INC R1 ;R1 adjust if no

Case „safe”:

state of T0: executed instruction:

8877h MOV R1,TH0

8878h

MOV R0,TL0

R1R0=8878h

Case „critical”:

state of T0: executed instruction:

88FFh MOV R1,TH0

8900h

MOV R0,TL0

! R1R0=8800h - error


; Procedure converting hex digit into code of 7-segment display.; Display segments are assigned do bits in byte as follow:; hgfedcba.; parameters: A = hex digit;; results: A = segment code;; changes: - ;; length: 19B (including code table);; execution time: 5 m.c.HEXDISP:INC A ;adding code table offset ;according to instruction RET MOVC A,@A+PC ;download display code RETKODY: DEFB 00111111b,00000110b,01011011b,01001111b DEFB 01100110b,01101101b,01111101b,00000111b DEFB 01111111b,01101111b,00000001b,01000000b DEFB 00001000b,01010000b,01111001b,01110001b

MCS51 - part 1. Lecture 1 2/47 Architecture MCS51 Addressing spaces & modes Instruction list.

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Transcript of MCS51 - part 1. Lecture 1 2/47 Architecture MCS51 Addressing spaces & modes Instruction list.