McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore...
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![Page 1: McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures Runjie Zhang Dec.3 S. Li et al. in MICRO’09.](https://reader035.fdocuments.net/reader035/viewer/2022062516/56649e455503460f94b3a4c4/html5/thumbnails/1.jpg)
McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures
Runjie ZhangDec.3
S. Li et al. in MICRO’09
![Page 2: McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures Runjie Zhang Dec.3 S. Li et al. in MICRO’09.](https://reader035.fdocuments.net/reader035/viewer/2022062516/56649e455503460f94b3a4c4/html5/thumbnails/2.jpg)
Motivation“Tools both limit and drive
research directions”
New demands◦Multicore/manycore◦Evaluate power, timing and area◦Different source of power dissipation◦Deep-submicron
![Page 3: McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures Runjie Zhang Dec.3 S. Li et al. in MICRO’09.](https://reader035.fdocuments.net/reader035/viewer/2022062516/56649e455503460f94b3a4c4/html5/thumbnails/3.jpg)
Related WorkWattch:
◦Enabling a tremendous surge in power-related research
Orion:◦Combined Wattch’s core power
model with a router power modelCACTI:
◦First tool in rapid power, area, and timing estimation
![Page 4: McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures Runjie Zhang Dec.3 S. Li et al. in MICRO’09.](https://reader035.fdocuments.net/reader035/viewer/2022062516/56649e455503460f94b3a4c4/html5/thumbnails/4.jpg)
What’s wrong with previous work?Wattch
◦No timing and area models◦Only models dynamic power
consumption◦Use simple linear scaling model
Orion2◦No short circuit power or timing◦“Incomplete”
CACTI◦???
![Page 5: McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures Runjie Zhang Dec.3 S. Li et al. in MICRO’09.](https://reader035.fdocuments.net/reader035/viewer/2022062516/56649e455503460f94b3a4c4/html5/thumbnails/5.jpg)
ContributionsFirst integrated power, area, and
timing modeling frameworkModel all three types of power
dissipationComplete, integrated solution for
multithreaded and multicore processor power
Deep-submicron tech. that no longer linear
![Page 6: McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures Runjie Zhang Dec.3 S. Li et al. in MICRO’09.](https://reader035.fdocuments.net/reader035/viewer/2022062516/56649e455503460f94b3a4c4/html5/thumbnails/6.jpg)
Overview
![Page 7: McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures Runjie Zhang Dec.3 S. Li et al. in MICRO’09.](https://reader035.fdocuments.net/reader035/viewer/2022062516/56649e455503460f94b3a4c4/html5/thumbnails/7.jpg)
Integrated Approach
Power Dynamic: Similar to WattchShort Circuit: IEEE TCAD’00Leakage: MASTAR & Intel
Timing CACTI with extension
Area CACTIEmpirical modeling for complex logic
![Page 8: McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures Runjie Zhang Dec.3 S. Li et al. in MICRO’09.](https://reader035.fdocuments.net/reader035/viewer/2022062516/56649e455503460f94b3a4c4/html5/thumbnails/8.jpg)
Hierarchical Approach
![Page 9: McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures Runjie Zhang Dec.3 S. Li et al. in MICRO’09.](https://reader035.fdocuments.net/reader035/viewer/2022062516/56649e455503460f94b3a4c4/html5/thumbnails/9.jpg)
Architecture LevelCore Divided into several main units:
e.g. IFU, EXU, LSU, OOO issue/dispatch unit
NoC Signal links and routers
On-Chip Caches
Coherent cache
Memory Controller
3 main hardware structureEmpirical model for physical interface (PHY)
Clocking PLL and clock distribution networkEmpirical model for PLL power
![Page 10: McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures Runjie Zhang Dec.3 S. Li et al. in MICRO’09.](https://reader035.fdocuments.net/reader035/viewer/2022062516/56649e455503460f94b3a4c4/html5/thumbnails/10.jpg)
Circuit Level
Wires Short wires as one-section Pi-RC model
Long wires as a buffered wire model
Arrays Based on CACTI with extensions
Logic Highly regular: CACTILess regular: Model from Intel, AMD and SunHighly customized: Empirical, from Intel and Sun
Clock Distribution Network
Separate circuit model
Global, Domain, and Local
![Page 11: McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures Runjie Zhang Dec.3 S. Li et al. in MICRO’09.](https://reader035.fdocuments.net/reader035/viewer/2022062516/56649e455503460f94b3a4c4/html5/thumbnails/11.jpg)
Validation
![Page 12: McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures Runjie Zhang Dec.3 S. Li et al. in MICRO’09.](https://reader035.fdocuments.net/reader035/viewer/2022062516/56649e455503460f94b3a4c4/html5/thumbnails/12.jpg)
Validation
Average error 1st ContributorError / % in total pwr
Niagara 1.47W / 23% 74% / 1%
Niagara2 1.87W / 26% 47% / 5%
Alpha 21364 3.4W / 26% 45% / 3%
Xeon Tulsa 4.2W / 17% 29% / 3%
![Page 13: McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures Runjie Zhang Dec.3 S. Li et al. in MICRO’09.](https://reader035.fdocuments.net/reader035/viewer/2022062516/56649e455503460f94b3a4c4/html5/thumbnails/13.jpg)
Scaling & Clustering
New generation:Double # of coresKeep the same micro-architecture
![Page 14: McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures Runjie Zhang Dec.3 S. Li et al. in MICRO’09.](https://reader035.fdocuments.net/reader035/viewer/2022062516/56649e455503460f94b3a4c4/html5/thumbnails/14.jpg)
Parameters and Benchmarks
![Page 15: McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures Runjie Zhang Dec.3 S. Li et al. in MICRO’09.](https://reader035.fdocuments.net/reader035/viewer/2022062516/56649e455503460f94b3a4c4/html5/thumbnails/15.jpg)
Area and Power
![Page 16: McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures Runjie Zhang Dec.3 S. Li et al. in MICRO’09.](https://reader035.fdocuments.net/reader035/viewer/2022062516/56649e455503460f94b3a4c4/html5/thumbnails/16.jpg)
Performance and Efficiency
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Performance and Efficiency
![Page 18: McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures Runjie Zhang Dec.3 S. Li et al. in MICRO’09.](https://reader035.fdocuments.net/reader035/viewer/2022062516/56649e455503460f94b3a4c4/html5/thumbnails/18.jpg)
In-order vs. OOO with M5