May 17, 20001 Design Option Trade-Offs w Transceiver Design - Dr. Zong Liang Wu, Philips.

May 17, 2000 1

Design Option Trade-OffsDesign Option Trade-Offs

Transceiver Design - Dr. Zong Liang Wu, PhilipsTransceiver Design - Dr. Zong Liang Wu, Philips

May 17, 2000 2

USB 2.0 PeripheralDesign Options

USB 2.0 PeripheralDesign Options

Zong Liang WuZong Liang Wu

Philips Philips

USB2.0 Transceiver and Device Architecture

USB2.0 Transceiver and Device Architecture

May 17, 2000 3

Functional Building Blocks of a USB 2.0 ApplicationFunctional Building Blocks of a USB 2.0 Application

System on a Chip of a USB 2.0 Function

USB HS USB HS AnalogAnalog

TransceiverTransceiver

Application Application Specific LogicSpecific Logic

Micro-ProcessorMicro-Processor

HS PIEHS PIEParallelParallel

InterfaceEngineInterfaceEngine

USBUSB

1.1 SIE1.1 SIESerial Interface Serial Interface

EngineEngine

USB backendUSB backend

((endpoint endpoint configuration, configuration, system bus system bus interface, DMA interface, DMA etc.)etc.)

USB FS/LS USB FS/LS AnalogAnalog

TransceiverTransceiver

Tx:Tx: P-->S,P-->S,BS, BS,

NRZI, NRZI, SYNC SYNC gen.gen.

Rx:Rx: DLL, DLL, NRZI, NRZI, BS, BS,

SYNC SYNC detectdetectS-->PS-->P

Clock circuitry, system logicClock circuitry, system logic

D+D+

D-D-

May 17, 2000 4

Q: How to Make Architectural Partitioning?Q: How to Make Architectural Partitioning?

Purpose: Speed up the time to marketPurpose: Speed up the time to marketfor USB chips and USB applicationfor USB chips and USB application

This can be achieved byThis can be achieved by– Reusing existing cores / blocks (from 1.x)Reusing existing cores / blocks (from 1.x)– Reducing risks due to functional errorsReducing risks due to functional errors

(through FPGA-based prototyping) (through FPGA-based prototyping) – Making reusable IP cores (for differentMaking reusable IP cores (for different

application environments)application environments) Background/reasons of PhilipsBackground/reasons of Philips

USB2.0 partitioning USB2.0 partitioning

May 17, 2000 5

HDLHDLCodingCoding

HDLHDLCodingCoding

SimulationSimulation

FPGAFPGAReal-time Real-time EmulationEmulation

Tape-Out

Main System Clock Main System Clock Must Allow HDL to Be Must Allow HDL to Be Fpga-able (30mhz ?)Fpga-able (30mhz ?)

Within an Within an Application Application EnvironmentEnvironment

Normal Digital BlockDesign Flow Normal Digital BlockDesign Flow

Minimizing Risk ThroughFPGA Verification

Minimizing Risk ThroughFPGA Verification

May 17, 2000 6

USB2.0 Device Prototyping USB2.0 Device Prototyping

Need a discrete 2.0 Transceiver Need a discrete 2.0 Transceiver Map USB digital (& application specific) logic into an FPGAMap USB digital (& application specific) logic into an FPGA Use a standard discrete micro-controller Use a standard discrete micro-controller

USB 2.0 USB 2.0 (FS/HS)(FS/HS)AnalogAnalog

TransceiverTransceiver++

Low-Level Low-Level Digital LogicDigital Logic

++ClockingClocking



Low-Level Low-Level Digital LogicDigital Logic

++ClockingClocking

FPGAFPGA

Application Application SpecificSpecific

LogicLogic

FPGAFPGA


LogicLogic

HS PIEHS PIEParallel Parallel

InterfaceEInterfaceEnginengine

USBUSB

1.1 SIE1.1 SIESerial Serial

Interface Interface EngineEngine

USB USB backendbackend

Standard Interface

FPGAFPGA Discrete ICDiscrete IC

Discrete ICMicro-

Processor

Discrete ICMicro-

Processor

May 17, 2000 7

USB2.0 Device: First Generation ProductUSB2.0 Device: First Generation Product



Low-Level Low-Level Digital Digital LogicLogic

++ClockingClocking




++ClockingClocking

FPGAFPGA


LogicLogic

FPGAFPGA


LogicLogic


InterfaceInterfaceEngineEngine

USBUSB




Standard Standard InterfaceInterface

Discrete ICDiscrete IC

Discrete ICMicro-

Processor

Discrete ICMicro-

Processor

USB ASICUSB ASIC

Two/Three-Chip Solution: USB ASIC(+Micro-Processor) + Discrete 2.0 Transceiver

Two/Three-Chip Solution: USB ASIC(+Micro-Processor) + Discrete 2.0 Transceiver

May 17, 2000 8

USB2.0 IP CoresUSB2.0 IP Cores

USB2.0 digital coreUSB2.0 digital core– Generic interface on the backendGeneric interface on the backend

side for wide application spaceside for wide application space

USB2.0 Transceiver coreUSB2.0 Transceiver core– Standard interface to the digitalStandard interface to the digital

core (no change from prototypingcore (no change from prototypingto silicon integration)to silicon integration)

Generic Generic InterfaceInterface

FPGA or Silicon ProvenFPGA or Silicon Proven

Standard Standard InterfaceInterface




++ClockingClocking




++ClockingClocking


LogicLogic


LogicLogic



USBUSB




Silicon ProvenSilicon Proven

Micro-Processor

May 17, 2000 9

Transceiver (IC/IP) Architectural OptionsTransceiver (IC/IP) Architectural Options

Clock-Switching: High speed clock for HS mode and scaled Clock-Switching: High speed clock for HS mode and scaled down clock for USB1.1 :down clock for USB1.1 :– Scale clock to 750 KHz @ 16 bits data-busScale clock to 750 KHz @ 16 bits data-bus– Scale clock to 1.5 MHz @ 8 bits data-busScale clock to 1.5 MHz @ 8 bits data-bus– Scale clock to 3 MHz @ 4 bits data-busScale clock to 3 MHz @ 4 bits data-bus

Over-Clocking: High speed clock for both HS and FS mode Over-Clocking: High speed clock for both HS and FS mode – --> Over-sampled parallel data bus for FS mode. (Intel’s USB2.0 --> Over-sampled parallel data bus for FS mode. (Intel’s USB2.0

Interface for IP)Interface for IP) Separate-Clocking: HS and FS use separate interfacesSeparate-Clocking: HS and FS use separate interfaces

– No digital clocking in the Transceiver for FS modeNo digital clocking in the Transceiver for FS mode– Single parallel data interface for HS only (+chirping)Single parallel data interface for HS only (+chirping)

Fact: HS and FS Need Different Clock for Sampler,Data Recovery, Bit-stuffing, Data Coding in NRZI, etc.

May 17, 2000 10

Basic Considerations on Transceiver Architecture: Philips Perspective

Design reuseDesign reuse– Reuse knowledge and experiences of 1.1 TransceiverReuse knowledge and experiences of 1.1 Transceiver– Reuse 1.1 digital front-end (SIE) in a 2.0 deviceReuse 1.1 digital front-end (SIE) in a 2.0 device– Separate Full-Speed and High-Speed transceiver logicSeparate Full-Speed and High-Speed transceiver logic

and interfacesand interfaces Enable easy reset, suspend, resume, transition betweenEnable easy reset, suspend, resume, transition between

speed modes, and chirpingspeed modes, and chirping One basic Transceiver architecture for all (function,One basic Transceiver architecture for all (function,

Host Controller & hub)Host Controller & hub) Making a discrete Transceiver IC to Making a discrete Transceiver IC to

– Enable quick prototyping and testing/debuggingEnable quick prototyping and testing/debuggingof 2.0 devices and host controllerof 2.0 devices and host controller

– Enable two-chip solution productsEnable two-chip solution products

May 17, 2000 11

OUT TokenOUT Token

6.5 bits for FS6.5 bits for FS192 bits for HS192 bits for HS

EOPEOP SYNCSYNC

ACKACK

Basic Considerations on Transceiver Architecture: Philips perspective Basic Considerations on Transceiver Architecture: Philips perspective

Device Response Time ConstraintsDevice Response Time Constraints– During a transaction, the device must respond within a time During a transaction, the device must respond within a time

interval, otherwise the host will timeoutinterval, otherwise the host will timeout– This time is from the end of the token’s EOP to the first synch This time is from the end of the token’s EOP to the first synch

bit of device’s responsebit of device’s response– This time is 6.5 bits for FS/LS device and This time is 6.5 bits for FS/LS device and – 192 HS bits for HS devices192 HS bits for HS devices

The Transceiver should minimize the latency time (for The Transceiver should minimize the latency time (for both receive and transmit paths) for both FS and HS, in both receive and transmit paths) for both FS and HS, in order to leave more time space for the digital coreorder to leave more time space for the digital core

May 17, 2000 12









Clock CircuitryClock Circuitry

+ System Control Logic + System Control Logic

Clock CircuitryClock Circuitry

+ System Control Logic + System Control Logic

FS FS

Analog Analog Drivers & Drivers & ReceiversReceivers

FS FS


HS HS


HS HS


HS Tx parallel->serial, BS, NRZI HS Tx parallel->serial, BS, NRZI encodingencodingHS Tx parallel->serial, BS, NRZI HS Tx parallel->serial, BS, NRZI encodingencoding

HS Rx DLL, NRZI, BS, SYNC HS Rx DLL, NRZI, BS, SYNC detection, serial-> paralleldetection, serial-> parallelHS Rx DLL, NRZI, BS, SYNC HS Rx DLL, NRZI, BS, SYNC detection, serial-> paralleldetection, serial-> parallel

Legacy 1.1 Legacy 1.1 interfaceinterface D+D+

D-D-

Standard Interface Standard Interface for Function, Hub US Port for Function, Hub US Port and Host DS Portand Host DS Port

Transceiver ArchitectureTransceiver Architecture

30MHz

May 17, 2000 13

Transceiver Architecture: Reset, Chirping, Suspend & ResumeTransceiver Architecture: Reset, Chirping, Suspend & Resume

Detection of bus reset, suspend condition: doneDetection of bus reset, suspend condition: donein the digital core, with the RX_Inactive signaling from in the digital core, with the RX_Inactive signaling from the HS Transceiverthe HS Transceiver

When in suspend, all blocks are shut-off, only the When in suspend, all blocks are shut-off, only the single-ended receivers of the FS transceiver remain single-ended receivers of the FS transceiver remain on, and the whole USB device termination is 1.1on, and the whole USB device termination is 1.1

(Remote) Wakeup is done through FS transceiver(Remote) Wakeup is done through FS transceiver Chirping control logic can be done in either the Chirping control logic can be done in either the

Transceiver or the digital core (just at theTransceiver or the digital core (just at theinterface level between the two cores)interface level between the two cores)

May 17, 2000 14

Details About Philips Transceiver ICDetails About Philips Transceiver IC

Test samples available for key partnersTest samples available for key partners Contact Marketing Manager W.L.Chui (see Contact Marketing Manager W.L.Chui (see

Marketing session) Marketing session) [email protected] Tel: +65 [email protected] Tel: +65 3517357

May 17, 20001 Design Option Trade-Offs w Transceiver Design - Dr. Zong Liang Wu, Philips.

Documents

Transcript of May 17, 20001 Design Option Trade-Offs w Transceiver Design - Dr. Zong Liang Wu, Philips.