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  • MAX10 - Architecture

    Last updated 7/11/20

  • 2 © tjEE 3921

    FPGA MAX10

    These slides review Intel/Altera MAX10 architecture

    Upon completion: You should be able to describe the MAX10 architecture and each of the major

    subsystems

  • 3 © tjEE 3921

    FPGA MAX10

    • Top Level View

    Src: MAX 10 Device Handbook

  • 4 © tjEE 3921

    FPGA MAX10

    • Top Level View • 10M50DAF484C7G

    Src: MAX 10 Device Overview

    10M 50 DA F 484 C 7 G

  • 5 © tjEE 3921

    FPGA MAX10

    • Top Level View • 10M50DAF484C7G

    Src: MAX 10 Device Overview

  • 6 © tjEE 3921

    FPGA MAX10

    • Logic Array • Array of Logic Elements (LEs) – 50K LEs

    Src: MAX 10 Device Handbook

  • 7 © tjEE 3921

    FPGA MAX10

    • Logic Elements • 1 LE can have both an asynchronous and synchronous

    path

    Src: MAX 10 Device Handbook

  • 8 © tjEE 3921

    FPGA MAX10

    • Logic Elements • Look-Up Table (LUT) • Multiplexor

    b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

    In p

    u t

    1 In

    p u

    t 2

    In p

    u t

    3 In

    p u

    t 4

    LUT Mask Output

    4 3 2 1 OUT

    0 0 0 0 b0

    0 0 0 1 b1

    0 0 1 0 b2

    0 0 1 1 b3

    0 1 0 0 b4

    0 1 0 1 b5

    0 1 1 0 b6

    0 1 1 1 b7

    1 0 0 0 b8

    1 0 0 1 b9

    1 0 1 0 b10

    1 0 1 1 b11

    1 1 0 0 b12

    1 1 0 1 b13

    1 1 1 0 b14

    1 1 1 1 b15

    Inputs

  • 9 © tjEE 3921

    FPGA MAX10

    • Logic Elements • Look-Up Table (LUT)

    (In1 | In2) & (In2 | In3) & !(In4)

    4 3 2 1 OUT

    0 0 0 0 0

    0 0 0 1 0

    0 0 1 0 1

    0 0 1 1 1

    0 1 0 0 0

    0 1 0 1 1

    0 1 1 0 1

    0 1 1 1 1

    1 0 0 0 0

    1 0 0 1 0

    1 0 1 0 0

    1 0 1 1 0

    1 1 0 0 0

    1 1 0 1 0

    1 1 1 0 0

    1 1 1 1 0

    Inputs

    0 0 0 0 0 0 0 0 1 1 1 0 1 1 0 0

    In p

    u t

    1 In

    p u

    t 2

    In p

    u t

    3 In

    p u

    t 4

    Out

    0 0 0 0 0 0 0 0 1 1 1 0 1 1 0 0

    1 1 0 0

    1

  • 10 © tjEE 3921

    FPGA MAX10

    • Logic Array • Normal Mode

    Src: MAX 10 Device Handbook

  • 11 © tjEE 3921

    FPGA MAX10

    • Logic Array • Arithmetic Mode • 1 LUT can implement an adder

    Src: MAX 10 Device Handbook

  • 12 © tjEE 3921

    FPGA MAX10

    • Logic Array • Arithmetic Mode • 3 input LUTs

    In 1

    In 2

    In 3

    In 4

    b15

    b14

    b13

    b12

    b11

    b10

    b9

    b8

    b7

    b6

    b5

    b4

    b3

    b2

    b1

    b0

  • 13 © tjEE 3921

    FPGA MAX10

    • Logic Array Block (LAB) • 16 LEs

    • LAB control signals

    • LE carry chains

    • Register chains

    • Local interconnect

  • 14 © tjEE 3921

    FPGA MAX10

    • LAB

    Src: MAX 10 Device Handbook

  • 15 © tjEE 3921

    FPGA MAX10

    • Multiple Levels of Interconnect • Local Interconnect

    Src: MAX 10 Device Handbook

  • 16 © tjEE 3921

    FPGA MAX10

    • Multiple Levels of Interconnect • Direct Link Interconnect

    Src: MAX 10 Device Handbook

  • 17 © tjEE 3921

    FPGA MAX10

    • Multiple Levels of Interconnect • Global Interconnect - direct

    Src: MAX 10 Device Handbook

  • 18 © tjEE 3921

    FPGA MAX10

    • Multiple Levels of Interconnect • Global Interconnect - indirect

    Src: MAX 10 Device Handbook

  • 19 © tjEE 3921

    FPGA MAX10

    • Multiple Levels of Interconnect • Row/Column Interconnect

    Src: MAX 10 Device Handbook

  • 20 © tjEE 3921

    FPGA MAX10

    • Additional Fixed Blocks - Clocks

    Src: MAX 10 Device Handbook

  • 21 © tjEE 3921

    FPGA MAX10

    • Additional Fixed Blocks – Clocks • PLL

    Src: MAX 10 Device Handbook

  • 22 © tjEE 3921

    FPGA MAX10

    • Additional Fixed Blocks - Clocks • PLL locations

    Src: MAX 10 Device Handbook

  • 23 © tjEE 3921

    FPGA MAX10

    • Additional Fixed Blocks - Memory • M9K Block • 8192 RAM bits (9216 including parity)

    • 284-MHz performance

    • True dual-port memory

    • Simple dual-port memory

    • Single-port memory

    • Byte enable

    • Parity bits

    • Shift register

    • FIFO buffer

    • ROM

    • Various clock modes

    • Address clock enable

  • 24 © tjEE 3921

    FPGA MAX10

    • Additional Fixed Blocks - Multiplier • 144 - 18 x 18 multipliers

    • Can be configured as 2 – 9 x 9 multipliers

    Src: MAX 10 Device Handbook

  • 25 © tjEE 3921

    FPGA MAX10

    • Additional Fixed Blocks - Multiplier • Configured as 2 – 9 x 9 multipliers

    Src: MAX 10 Device Handbook

  • 26 © tjEE 3921

    FPGA MAX10

    • Additional Fixed Blocks - ADC • 12 bit

    • 1Mbps

    Src: MAX 10 Device Handbook

  • 27 © tjEE 3921

    FPGA MAX10

    • Additional Fixed Blocks - User Flash • 2 user partitions

    • 5888Kb total memory

    Src: MAX 10 Device Handbook

  • 28 © tjEE 3921

    FPGA MAX10

    • Additional Fixed Blocks - IO

    Src: MAX 10 Device Handbook

  • 29 © tjEE 3921

    FPGA MAX10

    • Additional Fixed Blocks - IO

    Src: Max 10 Device Handbook

  • 30 © tjEE 3921

    FPGA MAX10

    • Additional Fixed Blocks - IO

    Src: Max 10 Device Handbook

  • 31 © tjEE 3921

    FPGA MAX10

    • Dual Power Supply

    Src: MAX 10 Device Handbook

  • 32 © tjEE 3921

    FPGA MAX10

    • FPGA – programmable • JTAG Programming Configurations • Load programming information (xx.sof file)

    • Directly into the Configuration RAM via the JTAG interface

    • Configuration FLASH holds the default program

    Src: MAX 10 FPGA Configuration Guide

    xx.sof file SRAM Object File

    Configuration RAM